#
5fc1f76a |
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23-Nov-2022 |
Nir Levy <bhr166@gmail.com> |
ARM: OMAP2+: Fix spelling typos in comment Fix spelling: adress -> address Signed-off-by: Nir Levy <bhr166@gmail.com> Message-Id: <20221123131720.79978-1-bhr166@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
d85d5247 |
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29-Mar-2020 |
Stefan Agner <stefan@agner.ch> |
ARM: OMAP2+: drop unnecessary adrl The adrl instruction has been introduced with commit dd31394779aa ("ARM: omap3: Thumb-2 compatibility for sleep34xx.S"), back when this assembly file was considerably longer. Today adr seems to have enough reach, even when inserting about 60 instructions between the use site and the label. Replace adrl with conventional adr instruction. This allows to build this file using Clang's integrated assembler (which does not support the adrl pseudo instruction). Link: https://github.com/ClangBuiltLinux/linux/issues/430 Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
3fe1ee40 |
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27-May-2019 |
Stefan Agner <stefan@agner.ch> |
ARM: use arch_extension directive instead of arch argument The LLVM Target parser currently does not allow to specify the security extension as part of -march (see also LLVM Bug 40186 [0]). When trying to use Clang with LLVM's integrated assembler, this leads to build errors such as this: clang-8: error: the clang compiler does not support '-Wa,-march=armv7-a+sec' Use ".arch_extension sec" to enable the security extension in a more portable fasion. Also make sure to use ".arch armv7-a" in case a v6/v7 multi-platform kernel is being built. Note that this is technically not exactly the same as the old code checked for availabilty of the security extension by calling as-instr. However, there are already other sites which use ".arch_extension sec" unconditionally, hence de-facto we need an assembler capable of ".arch_extension sec" already today (arch/arm/mm/proc-v7.S). The arch extension "sec" is available since binutils 2.21 according to its documentation [1]. [0] https://bugs.llvm.org/show_bug.cgi?id=40186 [1] https://sourceware.org/binutils/docs-2.21/as/ARM-Options.html Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Mans Rullgard <mans@mansr.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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#
1a59d1b8 |
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27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 156 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1334 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.113240726@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
d09220a8 |
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27-Nov-2017 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Fix SRAM virt to phys translation for save_secure_ram_context With the CMA changes from Joonsoo Kim <iamjoonsoo.kim@lge.com>, it was noticed that n900 stopped booting. After investigating it turned out that n900 save_secure_ram_context does some whacky virtual to physical address translation for the SRAM data address. As we now only have minimal parts of omap3 idle code copied to SRAM, running save_secure_ram_context() in SRAM is not needed. It only gets called on PM init. And it seems there's no need to ever call this from SRAM idle code. So let's just keep save_secure_ram_context() in DDR, and pass it the physical address of the parameters. We can do everything else in omap-secure.c like we already do for other secure code. And since we don't have any documentation, I still have no clue what the values for 0, 1 and 1 for the parameters might be. If somebody has figured it out, please do send a patch to add some comments. Debugged-by: Joonsoo Kim <iamjoonsoo.kim@lge.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
1abd3502 |
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25-Jul-2017 |
Russell King <rmk+kernel@armlinux.org.uk> |
ARM: align .data section Robert Jarzmik reports that his PXA25x system fails to boot with 4.12, failing at __flush_whole_cache in arch/arm/mm/proc-xscale.S:215: 0xc0019e20 <+0>: ldr r1, [pc, #788] 0xc0019e24 <+4>: ldr r0, [r1] <== here with r1 containing 0xc06f82cd, which is the address of "clean_addr". Examination of the System.map shows: c06f22c8 D user_pmd_table c06f22cc d __warned.19178 c06f22cd d clean_addr indicating that a .data.unlikely section has appeared just before the .data section from proc-xscale.S. According to objdump -h, it appears that our assembly files default their .data alignment to 2**0, which is bad news if the preceding .data section size is not power-of-2 aligned at link time. Add the appropriate .align directives to all assembly files in arch/arm that are missing them where we require an appropriate alignment. Reported-by: Robert Jarzmik <robert.jarzmik@free.fr> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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#
0a0b1327 |
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14-Jan-2016 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Fix l2_inv_api_params for rodata We don't want to write to .text, so let's move l2_inv_api_params to .data and access it via a pointer. Cc: Kees Cook <keescook@chromium.org> Cc: Laura Abbott <labbott@redhat.com> Cc: Nishanth Menon <nm@ti.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tero Kristo <t-kristo@ti.com> Acked-by: Nicolas Pitre <nico@linaro.org> Cc: stable@vger.kernel.org # v4.0+ Fixes: 1e6b48116a95 ("ARM: mm: allow non-text sections to be non-executable") Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
a5311d4d |
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14-Jan-2016 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Fix save_secure_ram_context for rodata We don't want to write to .text and we can move save_secure_ram_context into .data as it all gets copied into SRAM anyways. Cc: Kees Cook <keescook@chromium.org> Cc: Laura Abbott <labbott@redhat.com> Cc: Nishanth Menon <nm@ti.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Cc: Tero Kristo <t-kristo@ti.com> Acked-by: Nicolas Pitre <nico@linaro.org> Cc: stable@vger.kernel.org # v4.0+ Fixes: 1e6b48116a95 ("ARM: mm: allow non-text sections to be non-executable") Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
eeaf9646 |
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14-Jan-2016 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Fix l2dis_3630 for rodata We don't want to write to .text section. Let's move l2dis_3630 to .data and access it via a pointer. For calculating the offset, let's optimize out the add and do it in ldr/str as suggested by Nicolas Pitre <nicolas.pitre@linaro.org>. Cc: Kees Cook <keescook@chromium.org> Cc: Laura Abbott <labbott@redhat.com> Cc: Nishanth Menon <nm@ti.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tero Kristo <t-kristo@ti.com> Cc: stable@vger.kernel.org # v4.0+ Acked-by: Nicolas Pitre <nico@linaro.org> Cc: stable@vger.kernel.org # v4.0+ Fixes: 1e6b48116a95 ("ARM: mm: allow non-text sections to be non-executable") Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
d9db5910 |
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14-Jan-2016 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Fix wait_dll_lock_timed for rodata We don't want to be writing to .text so it can be set rodata. Fix error "Unable to handle kernel paging request at virtual address c012396c" in wait_dll_lock_timed if CONFIG_DEBUG_RODATA is selected. As these counters are for debugging only and unused, we can just remove them. Cc: Kees Cook <keescook@chromium.org> Cc: Laura Abbott <labbott@redhat.com> Cc: Nishanth Menon <nm@ti.com> Cc: Richard Woodruff <r-woodruff2@ti.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tero Kristo <t-kristo@ti.com> Acked-by: Nicolas Pitre <nico@linaro.org> Cc: stable@vger.kernel.org # v4.0+ Fixes: 1e6b48116a95 ("ARM: mm: allow non-text sections to be non-executable") Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
d8a50941 |
|
28-May-2015 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP3: Fix booting with thumb2 kernel We get a NULL pointer dereference on omap3 for thumb2 compiled kernels: Internal error: Oops: 80000005 [#1] SMP THUMB2 ... [<c046497b>] (_raw_spin_unlock_irqrestore) from [<c0024375>] (omap3_enter_idle_bm+0xc5/0x178) [<c0024375>] (omap3_enter_idle_bm) from [<c0374e63>] (cpuidle_enter_state+0x77/0x27c) [<c0374e63>] (cpuidle_enter_state) from [<c00627f1>] (cpu_startup_entry+0x155/0x23c) [<c00627f1>] (cpu_startup_entry) from [<c06b9a47>] (start_kernel+0x32f/0x338) [<c06b9a47>] (start_kernel) from [<8000807f>] (0x8000807f) The power management related assembly on omaps needs to interact with ARM mode bootrom code, so we need to keep most of the related assembly in ARM mode. Turns out this error is because of missing ENDPROC for assembly code as suggested by Stephen Boyd <sboyd@codeaurora.org>. Let's fix the problem by adding ENDPROC in two places to sleep34xx.S. Let's also remove the now duplicate custom code for mode switching. This has been unnecessary since commit 6ebbf2ce437b ("ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+"). And let's also remove the comments about local variables, they are now just confusing after the ENDPROC. The reason why ENDPROC makes a difference is it sets .type and then the compiler knows what to do with the thumb bit as explained at: https://wiki.ubuntu.com/ARM/Thumb2PortingHowto Reported-by: Kevin Hilman <khilman@kernel.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
bf027ca1 |
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29-Oct-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP: Split sram.h to local headers and minimal shared header Most of the defines are specific to omap1 and omap2+, and should be in the local headers. Only minimal function prototypes need to be shared. As discussed on linux-arm-kernel, we want to avoid relative includes for the arch/arm/*omap* shared code: http://www.spinics.net/lists/linux-omap/msg80520.html So this patch re-adds a minimal plat/sram.h. The new plat/sram.h must not be included from drivers, that will break build for omap2+ CONFIG_MULTIPLATFORM. Note that this patch temporarily adds two more relative includes; Those will be removed in the following patch. Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
ff4ae5d9 |
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21-Oct-2012 |
Paul Walmsley <paul@pwsan.com> |
ARM: OMAP2+: CM/hwmod: split CM functions into OMAP2, OMAP3-specific files Move OMAP3xxx-specific CM functions & macros into cm3xxx.[ch] and OMAP2xxx-specific macros into cm2xxx.[ch]. Move basic CM register access functions into static inline functions in cm2xxx_3xxx.h, leaving only OMAP2/3 hardreset functions in cm2xxx_3xxx.c. As part of this, split the CM and hwmod code that waits for devices to become ready into SoC-specific functions. This is in preparation for the upcoming move of this code to drivers/. Signed-off-by: Paul Walmsley <paul@pwsan.com> Reviewed-by: Russ Dill <Russ.Dill@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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#
139563ad |
|
21-Oct-2012 |
Paul Walmsley <paul@pwsan.com> |
ARM: OMAP2+: PRM: split PRM functions into OMAP2, OMAP3-specific files Move OMAP3xxx-specific PRM functions & macros into prm3xxx.[ch] and OMAP2xxx-specific macros into prm2xxx.h. (prm2xxx.c will be created by a subsequent patch when it's needed.) Move basic PRM register access functions into static inline functions in prm2xxx_3xxx.h, leaving only OMAP2/3 hardreset functions in prm2xxx_3xxx.c. Also clarify the initcall function naming to reinforce that this code is specifically for the PRM IP block. This is in preparation for the upcoming powerdomain series and the upcoming move of this code to drivers/. Signed-off-by: Paul Walmsley <paul@pwsan.com> Reviewed-by: Russ Dill <Russ.Dill@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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#
622297fd |
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02-Oct-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP: Make plat/sram.h local to plat-omap We can move this from plat to be local to plat-omap for common ARM zImage support. Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
c49f34bc |
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31-Aug-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+ Move SoC specific headers to be local to mach-omap2 These can now be moved to be local headers in mach-omap2. Note that this patch removes arch/arm/plat-omap/devices.c as it will get removed anyways with Paul Walmsley's patch "ARM: OMAP: split OMAP1, OMAP2+ RNG device registration". Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
dbc04161 |
|
31-Aug-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP: Split plat/hardware.h, use local soc.h for omap2+ As the plat and mach includes need to disappear for single zImage work, we need to remove plat/hardware.h. Do this by splitting plat/hardware.h into omap1 and omap2+ specific files. The old plat/hardware.h already has omap1 only defines, so it gets moved to mach/hardware.h for omap1. For omap2+, we use the local soc.h that for now just includes the related SoC headers to keep this patch more readable. Note that the local soc.h still includes plat/cpu.h that can be dealt with in later patches. Let's also include plat/serial.h from common.h for all the board-*.c files. This allows making the include files local later on without patching these files again. Note that only minimal changes are done in this patch for the drivers/watchdog/omap_wdt.c driver to keep things compiling. Further patches are needed to eventually remove cpu_is_omap usage in the drivers. Also only minimal changes are done to sound/soc/omap/* to remove the unneeded includes and to define OMAP44XX_MCPDM_L3_BASE locally so there's no need to include omap44xx.h. While at it, also sort some of the includes in the standard way. Cc: linux-watchdog@vger.kernel.org Cc: alsa-devel@alsa-project.org Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Jarkko Nikula <jarkko.nikula@bitmer.com> Cc: Liam Girdwood <lrg@ti.com> Acked-by: Wim Van Sebroeck <wim@iguana.be> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
2c799cef |
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24-Feb-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP: Remove plat/io.h by splitting it into mach/io.h and mach/hardware.h This is needed to minimize io.h so the SoC specific io.h for ARMs can removed. Note that minimal driver changes for DSS and RNG are needed to include cpu.h for SoC detection macros. Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Matt Mackall <mpm@selenic.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
ee0839c2 |
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24-Feb-2012 |
Tony Lindgren <tony@atomide.com> |
ARM: OMAP2+: Move most of plat/io.h into local iomap.h There's no need to have these defines in plat/io.h. Note that we now need to ifdef omap_read/write calls as they will be available for omap1 only. While at it, clean up the includes to group them like they typically are grouped. Signed-off-by: Tony Lindgren <tony@atomide.com>
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#
cbe26349 |
|
30-Jun-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: pm: omap3: move saving of the auxiliary control registers to C Move the saving of the auxiliary control registers into C; there's no need for this to be in assembly code. This results in less assembly code to deal with in OMAP. Kevin tested full-chip retention and off on 3430/n900, 3530/Overo and 3630/Zoom3. Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
46e130d2 |
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29-Jun-2011 |
Jean Pihet <j-pihet@ti.com> |
ARM: pm: omap3: run the ASM sleep code from DDR Most of the ASM sleep code (in arch/arm/mach-omap2/sleep34xx.S) is copied to internal SRAM at boot and after wake-up from CORE OFF mode. However only a small part of the code really needs to run from internal SRAM. This fix lets most of the ASM idle code run from the DDR in order to minimize the SRAM usage and the overhead in the code copy. The only pieces of code that are mandatory in SRAM are: - the i443 erratum WA, - the i581 erratum WA, - the security extension code. SRAM usage: - original code: . 560 bytes for omap3_sram_configure_core_dpll (used by DVFS), . 852 bytes for omap_sram_idle (used by suspend/resume in RETention), . 124 bytes for es3_sdrc_fix (used by suspend/resume in OFF mode on ES3.x), . 108 bytes for save_secure_ram_context (used on HS parts only). With this fix the usage for suspend/resume in RETention goes down 288 bytes, so the gain in SRAM usage for suspend/resume is 564 bytes. Also fixed the SRAM initialization sequence to avoid an unnecessary copy to SRAM at boot time and for readability. Tested on Beagleboard (ES2.x) in idle with full RET and OFF modes. Kevin Hilman tested retention and off on 3430/n900, 3530/Overo and 3630/Zoom3 Signed-off-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
14c79bbe |
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23-Jun-2011 |
Kevin Hilman <khilman@ti.com> |
ARM: pm: omap34xx: remove get_*_restore_pointer functions, directly use entry points Upon return from off-mode, the ROM code jumps to a restore function saved in the scratchpad. Based on SoC revision or errata, this restore entry point is different. Current code uses some helper functions in sleep34xx.S (get_*_restore_pointer) to get the restore function entry point. When returning from off-mode, this code is executed from SDRAM, so there's no reason to use these helper functions when using the SDRAM entry points directly would work just fine. This patch uses ENTRY/ENDPROC to create "real" entry points for these functions, and uses those values directly when writing the scratchpad. Tested all three entry points - restore_es3: 3430/n900 - restore_3630: 3630/Zoom3 - restore: 3530/Overo Suggested-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
076f2cc4 |
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22-Jun-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: pm: omap34xx: convert to generic suspend/resume support Convert omap34xx to use the generic CPU suspend/resume support, rather than implementing its own version. Tested on 3430 LDP. Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
2637ce30 |
|
21-Jun-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: pm: omap34xx: remove misleading comment and use of r9 The code alludes to r9 being used to indicate what was lost over the suspend/resume transition. However, although r9 is set, it is never actually used. Also, the comments before the code (which refer to the value of r9) and the comments against the assignment of r9 contradict each other, so just remove them to avoid confusion. Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
857c1b81 |
|
21-Jun-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: pm: omap34xx: no need to save all registers in sleep34xx.S The ABI allows called functions to corrupt r0-r3 and ip (r12). So its pointless saving these registers in the suspend code - the calling function will expect them to be corrupted and so won't rely on their contents after resume. Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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#
90625110 |
|
23-Jan-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
OMAP3: PM: Clear the SCTLR C bit in asm code to prevent data cache allocation On the newer ARM processors like CortexA8, CortexA9, the caches can be speculatively loaded while they are getting flushed. Clear the SCTLR C bit to prevent further data cache allocation as part of cache clean routine Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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#
46f557cb |
|
23-Jan-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
OMAP3: PM: Remove un-necessary cp15 registers form low power cpu context The current code saves few un-necessary registers which are read-only or write-only, unused CP15 registers. Remove them and keep only necessary CP15 registers part of low power context save/restore. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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#
c9749a35 |
|
23-Jan-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
OMAP3: PM: Allow the cache clean when L1 is lost. When L1 cache is suppose to be lost, it needs to be cleaned before entrering to the low power mode. While at this, also fix few comments and remove un-necessary clean_l2 lable. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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#
8409d57b |
|
23-Jan-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
OMAP3: PM: Fix the MMU on sequence in the asm code Add necessary barriers after enabling MMU. Also use the sane way to load pc and jump to it instead of executing ldma first up. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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#
4444d712 |
|
23-Jan-2011 |
Santosh Shilimkar <santosh.shilimkar@ti.com> |
OMAP3: PM: Use ARMv7 supported instructions instead of legacy CP15 ones On ARMv7 dsb, dmb instructions are supported and can be used directly instead of their cp15 equivalnet. Also remove the opcodes for smc and use the available instruction directly in OMAP3 low power asm code Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
|
#
dd313947 |
|
04-Mar-2011 |
Dave Martin <dave.martin@linaro.org> |
ARM: omap3: Thumb-2 compatibility for sleep34xx.S * Build unconditionally as ARM for correct interoperation with OMAP firmware. * Fix an out-of-range ADR when building for ARM. * Remove deprecated PC-relative stores. * Add the required ENDPROC() directive for each ENTRY(). * .align before data words. * Handle non-interworking return from v7_flush_dcache_all. Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Kevin Hilman <khilman@ti.com>
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#
76d50018 |
|
04-Mar-2011 |
Dave Martin <dave.martin@linaro.org> |
ARM: omap3: Remove hand-encoded SMC instructions For various reasons, Linux now only officially supports being built with tools which are new enough to understand the SMC instruction. Replacing the hand-encoded instructions when the mnemonic also allows for correct assembly in Thumb-2 (otherwise, the result is random data in the middle of the code). The Makefile already ensures that this file is built with a high enough gcc -march= flag (armv7-a). Signed-off-by: Dave Martin <dave.martin@linaro.org> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
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#
b6338bdc |
|
02-Feb-2011 |
Jean Pihet <j-pihet@ti.com> |
ARM: 6649/1: omap: use fncpy to copy the PM code functions to SRAM The new fncpy API is better suited* for copying some code to SRAM at runtime. This patch changes the ad-hoc code to the more generic fncpy API. *: 1. fncpy ensures that the thumb mode bit is propagated, 2. fncpy provides the security of type safety between the original function and the sram function pointer. Tested OK on OMAP3 in low power modes (RET/OFF) using omap2plus_defconfig with !CONFIG_THUMB2_KERNEL. Compile tested on OMAP1/2 using omap1_defconfig. Boot tested on OMAP1 & OMAP2 Tested OK with suspend/resume on OMAP2420/n810 Boots fine on osk5912 and n800 Signed-off-by: Jean Pihet <j-pihet@ti.com> Acked-by: Kevin Hilman <khilman@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Dave Martin <dave.martin@linaro.org> Tested-by: Kevin Hilman <khilman@ti.com> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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59fb659b |
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21-Dec-2010 |
Paul Walmsley <paul@pwsan.com> |
OMAP2/3: PRCM: split OMAP2/3-specific PRCM code into OMAP2/3-specific files In preparation for adding OMAP4-specific PRCM accessor/mutator functions, split the existing OMAP2/3 PRCM code into OMAP2/3-specific files. Most of what was in mach-omap2/{cm,prm}.{c,h} has now been moved into mach-omap2/{cm,prm}2xxx_3xxx.{c,h}, since it was OMAP2xxx/3xxx-specific. This process also requires the #includes in each of these files to be changed to reference the new file name. As part of doing so, add some comments into plat-omap/sram.c and plat-omap/mcbsp.c, which use "sideways includes", to indicate that these users of the PRM/CM includes should not be doing so. Thanks to Felipe Contreras <felipe.contreras@gmail.com> for comments on this patch. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Jarkko Nikula <jhnikula@gmail.com> Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com> Cc: Liam Girdwood <lrg@slimlogic.co.uk> Cc: Omar Ramirez Luna <omar.ramirez@ti.com> Acked-by: Omar Ramirez Luna <omar.ramirez@ti.com> Cc: Felipe Contreras <felipe.contreras@gmail.com> Acked-by: Felipe Contreras <felipe.contreras@gmail.com> Cc: Greg Kroah-Hartman <greg@kroah.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Reviewed-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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bb1c9034 |
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18-Dec-2010 |
Jean Pihet <j-pihet@ti.com> |
OMAP3: ASM sleep code format rework Cosmetic fixes to the code: - white spaces and tabs, - alignement, - comments rephrase and typos, - multi-line comments Tested on N900 and Beagleboard with full RET and OFF modes, using cpuidle and suspend. Signed-off-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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83521291 |
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18-Dec-2010 |
Jean Pihet <j-pihet@ti.com> |
OMAP3: add comments for low power code errata Errata covered: - 1.157 & 1.185 - i443 - i581 Tested on N900 and Beagleboard with full RET and OFF modes, using cpuidle and suspend. Signed-off-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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f7dfe3d8 |
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18-Dec-2010 |
Jean Pihet <j-pihet@ti.com> |
OMAP3: rework of the ASM sleep code execution paths - Reworked and simplified the execution paths for better readability and to avoid duplication of code, - Added comments on the entry and exit points and the interaction with the ROM code for OFF mode restore, - Reworked the existing comments for better readability. Tested on N900 and Beagleboard with full RET and OFF modes, using cpuidle and suspend. Signed-off-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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1e81bc01 |
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18-Dec-2010 |
Jean Pihet <j-pihet@ti.com> |
OMAP3: re-organize the ASM sleep code Organize the code in the following sections: - register access macros, - API functions, - internal functions. Tested on N900 and Beagleboard with full RET and OFF modes, using cpuidle and suspend. Signed-off-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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fe360e1c |
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18-Dec-2010 |
Jean Pihet <j-pihet@ti.com> |
OMAP3: remove hardcoded values from the ASM sleep code Using macros from existing include files for registers addresses. Tested on N900 and Beagleboard with full RET and OFF modes, using cpuidle and suspend. Based on original patch from Vishwa. Signed-off-by: Jean Pihet <j-pihet@ti.com> Cc: Vishwanath BS <vishwanath.bs@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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b4b36fd9 |
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18-Dec-2010 |
Jean Pihet <j-pihet@ti.com> |
OMAP2+: use global values for the SRAM PA addresses The SRAM PA addresses are locally defined and used at different places, i.e. SRAM management code and idle sleep code. The macros are now defined at a centralized place, for easier maintenance. Tested on N900 and Beagleboard with full RET and OFF modes, using cpuidle and suspend. Signed-off-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon<nm@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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d3cdfd2a |
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18-Dec-2010 |
Jean Pihet <j-pihet@ti.com> |
OMAP3: remove unused code from the ASM sleep code Remove unused code: - macros, - variables, - unused semaphore locking API. This API shall be added back when needed, - infinite loops for debug. Tested on N900 and Beagleboard with full RET and OFF modes, using cpuidle and suspend. Signed-off-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Tested-by: Nishanth Menon<nm@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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c4236d2e |
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20-Dec-2010 |
Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com> |
OMAP3630: PM: Disable L2 cache while invalidating L2 cache While coming out of MPU OSWR/OFF states, L2 controller is reseted. The reset behavior is implementation specific as per ARMv7 TRM and hence $L2 needs to be invalidated before it's use. Since the AUXCTRL register is also reconfigured, disable L2 cache before invalidating it and re-enables it afterwards. This is as per Cortex-A8 ARM documentation. Currently this is identified as being needed on OMAP3630 as the disable/enable is done from "public side" while, on OMAP3430, this is done in the "secure side". Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [nm@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630] Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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458e999e |
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20-Dec-2010 |
Nishanth Menon <nm@ti.com> |
OMAP3630: PM: Erratum i608: disable RTA Erratum id: i608 RTA (Retention Till Access) feature is not supported and leads to device stability issues when enabled. This impacts modules with embedded memories on OMAP3630 Workaround is to disable RTA on boot and coming out of core off. For disabling RTA coming out of off mode, we do this by overriding the restore pointer for 3630 as the first point of entry before caches are touched and is common for GP and HS devices. To disable earlier than this could be possible by modifying the PPA for HS devices, but not for GP devices. Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Jean Pihet <j-pihet@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [ambresh@ti.com: co-developer] Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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9d93b8a2 |
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20-Dec-2010 |
Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com> |
OMAP3: PM: Erratum i581 support: dll kick strategy Erratum i581 impacts OMAP3 platforms. PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing the DPLL not to be locked at times. IMPORTANT: *) This is not a complete workaround implementation as recommended by the silicon erratum. This is a support logic for detecting lockups and attempting to recover where possible and is known to provide stability in multiple platforms. *) This code is mostly important for inactive and retention. The ROM code waits for the maximum DLL lock time when resuming from off mode. So for off mode this code isn't really needed. *) counters are introduced here for eventual export to userspace once the cleanups are completed. This should eventually get refactored as part of cleanups to sleep34xx.S Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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0bd40535 |
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20-Dec-2010 |
Richard Woodruff <r-woodruff2@ti.com> |
OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all Analysis in TI kernel with ETM showed that using cache mapped flush in kernel instead of SO mapped flush cost drops by 65% (3.39mS down to 1.17mS) for clean_l2 which is used during sleep sequences. Overall: - speed up - unfortunately there isn't a good alternative flush method today - code reduction and less maintenance and potential bug in unmaintained code This also fixes the bug with the clean_l2 function usage. Reported-by: Tony Lindgren <tony@atomide.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> [nm@ti.com: ported rkw's proposal to 2.6.37-rc2] Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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4814ced5 |
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08-Oct-2010 |
Paul Walmsley <paul@pwsan.com> |
OMAP: control: move plat-omap/control.h to mach-omap2/control.h Only OMAP2+ platforms have the System Control Module (SCM) IP block. In the past, we've kept the SCM header file in plat-omap. This has led to abuse - device drivers including it; includes being added that create implicit dependencies on OMAP2+ builds; etc. In response, move the SCM headers into mach-omap2/. As part of this, remove the direct SCM access from the OMAP UDC driver. It was clearly broken. The UDC code needs an indepth review for use on OMAP2+ chips. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Cory Maccarrone <darkstar6262@gmail.com> Cc: Kyungmin Park <kyungmin.park@samsung.com>
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46cd09a7 |
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10-Jun-2010 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
fix typos concerning "acquire" Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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79dcfdd4 |
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11-Nov-2009 |
Tero Kristo <tero.kristo@nokia.com> |
OMAP3: PM: Added support for L2 aux ctrl register save and restore This patch adds a save and restore mechanism for ARM L2 auxiliary control register. The feature is enabled by default for GP devices, but for HS/EMU devices the user must enable the service and define the PPA service ID to be used for setting L2 aux ctrl, as this is not currently supported by the bootloader. If nobody alters the contents of L2 aux ctrl from its reset value, this feature is not needed. Kconfig option to enable HS/EMU L2 aux save and restore: - OMAP3_L2_AUX_SECURE_SAVE_RESTORE Kconfig option to select HS/EMU PPA service for setting L2 aux ctrl: - OMAP3_L2_AUX_SECURE_SERVICE_SET_ID Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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a89b6f00 |
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28-May-2009 |
Rajendra Nayak <rnayak@ti.com> |
OMAP3: PM: add scratchpad locking function This patch implements locking using the semaphore in scratchpad memory preventing any concurrent access to scratchpad from OMAP and Baseband/Modem processor. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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37903009 |
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26-Jan-2010 |
Abhijit Pagare <abhijitpagare@ti.com> |
ARM: OMAP4: PM: OMAP4 Power Domain Porting Related Clean-up. Module offsets were same for OMAP2 and OMAP3 while they differ for OMAP4. Hence we need different macros for identifying platform specific offsets. Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com>
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a087cad9 |
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11-Nov-2009 |
Tero Kristo <tero.kristo@nokia.com> |
OMAP3: Fixed ARM aux ctrl register save/restore Current value is stored on SDRAM and it is written back during wakeup. Previously a static value of 0x72 was written there. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Acked-by: Thara Gopinath <thara@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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89139dce |
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16-Jan-2009 |
Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com> |
OMAP3: PM: Wait for SDRC ready iso a blind delay This patch improves the wakeup SRAM code polling the SDRC to become ready instead of just waiting for a fixed amount of time. Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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0795a75a |
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13-Oct-2008 |
Tero Kristo <tero.kristo@nokia.com> |
OMAP3: PM: SDRC auto-refresh workaround for off-mode Errata: ES3.0, ES3.1 SDRC not sending auto-refresh when OMAP wakes-up from OFF mode Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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ba50ea7e |
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26-Mar-2009 |
Kalle Jokiniemi <kalle.jokiniemi@digia.com> |
OMAP3: PM: Fix secure SRAM context save/restore The secure sram context save uses dma channels 0 and 1. In order to avoid collision between kernel DMA transfers and ROM code dma transfers, we need to reserve DMA channels 0 1 on high security devices. A bug in ROM code leaves dma irq status bits uncleared. Hence those irq status bits need to be cleared when restoring DMA context after off mode. There was also a faulty parameter given to PPA in the secure ram context save assembly code, which caused interrupts to be enabled during secure ram context save. This caused the save to fail sometimes, which resulted the saved context to be corrupted, but also left DMA channels in secure mode. The secure mode DMA channels caused "DMA secure error with device 0" errors to be displayed. Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com> Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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27d59a4a |
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13-Oct-2008 |
Tero Kristo <tero.kristo@nokia.com> |
OMAP3 PM: off-mode support for HS/EMU devices For HS/EMU devices, some additional resources need to be saved/restored for off-mode support. Namely, saving the secure RAM and a pointer to it in the scratchpad. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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61255ab9 |
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26-Sep-2008 |
Rajendra Nayak <rnayak@ti.com> |
OMAP3: PM: MPU off-mode support Adds a 'save_state' option when calling into SRAM idle function and adds some minor cleanups of SRAM asm code. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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ce491cf8 |
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20-Oct-2009 |
Tony Lindgren <tony@atomide.com> |
omap: headers: Move remaining headers from include/mach to include/plat Move the remaining headers under plat-omap/include/mach to plat-omap/include/plat. Also search and replace the files using these headers to include using the right path. This was done with: #!/bin/bash mach_dir_old="arch/arm/plat-omap/include/mach" plat_dir_new="arch/arm/plat-omap/include/plat" headers=$(cd $mach_dir_old && ls *.h) omap_dirs="arch/arm/*omap*/ \ drivers/video/omap \ sound/soc/omap" other_files="drivers/leds/leds-ams-delta.c \ drivers/mfd/menelaus.c \ drivers/mfd/twl4030-core.c \ drivers/mtd/nand/ams-delta.c" for header in $headers; do old="#include <mach\/$header" new="#include <plat\/$header" for dir in $omap_dirs; do find $dir -type f -name \*.[chS] | \ xargs sed -i "s/$old/$new/" done find drivers/ -type f -name \*omap*.[chS] | \ xargs sed -i "s/$old/$new/" for file in $other_files; do sed -i "s/$old/$new/" $file done done for header in $(ls $mach_dir_old/*.h); do git mv $header $plat_dir_new/ done Signed-off-by: Tony Lindgren <tony@atomide.com>
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8bd22949 |
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28-May-2009 |
Kevin Hilman <khilman@deeprootsystems.com> |
OMAP2/3: PM: push core PM code from linux-omap This patch is to sync the core linux-omap PM code with mainline. This code has evolved and been used for a while the linux-omap tree, but the attempt here is to finally get this into mainline. Following this will be a series of patches from the 'PM branch' of the linux-omap tree to add full PM hardware support from the linux-omap tree. Much of this PM core code was written by Jouni Hogander with significant contributions from Paul Walmsley as well as many others from Nokia, Texas Instruments and linux-omap community. Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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