- Copy stable/10 (r259064) to releng/10.0 as part of the
10.0-RELEASE cycle.
- Update __FreeBSD_version [1]
- Set branch name to -RC1

[1] 10.0-CURRENT __FreeBSD_version value ended at '55', so
start releng/10.0 at '100' so the branch is started with
a value ending in zero.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Copy head (r256279) to stable/10 as part of the 10.0-RELEASE cycle.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Add some missing AR934x register definitions.

These are needed for ethernet bootstrap.

Approved by: re@ (gjb)

Fix interrupt handling from the APB periperals (ie, UART) - it
also requires an explicit acknowledgement.

Tested:

* AR9344 (DB120) SoC

Approved by: re@ (gjb)

Fix the AR933x CPU UART support by using the correct clock when calculating
the UART frequency.

Tested:

* AR933x (carambola 2 board), UART now works again

Approved by: re

Remove the hardcoded limit for the number of gpio_pins that can be used.
Allocate it dynamically.

Approved by: adrian (mentor)

Fix an off-by-one bug in ar71xx_gpio and bcm2835_gpio which makes the last
pin unavailable.

Reported and tested by: sbruno (ar71xx)
Approved by: adrian (mentor)
Pointy hat to: loos

Fix the leakage of dma tags on if_arge. The leak occur when arge_start()
add some packet(s) to tx ring and arge_stop() is called before receive the
sent packet interrupt from hardware. Fix arge_stop() to unload the in use
dma tags and free the associated mbuf.

PR: 178319, 163670
Approved by: adrian (mentor)

Prevent the full restart cycle every time arge_start() is called. Only
(re)start the interface when it is down. This change fix a race with
BOOTP where the response packet is lost because the interface is being
reset by a netmask change right after send the packet.

PR: 178318
Approved by: adrian (mentor)

Make ar71xx_spi attach the next free unit of spibus and not only spibus0.

Approved by: adrian (mentor)

Some vendors store the mac addresses of arge(4) as a literal sring in the
form xx:xx:xx:xx:xx:xx complete with ":" characters taking of 18 bytes
instead of 6 integers. Expose a "readascii" tuneable to handle this case.

Remove restriction on eepromac assignement for the first dev instance only.

Add eepromac address for DIR-825 to hints file.

Add readascii hint for DIR-825

Reviewed by: adrian@

Add a missing break.

Implement some initial AR934x support routines.

This code reads the PLL configuration registers and correctly programs
things so the UART and such can come up.

There's MIPS74k platform issues that need fixing; but this at least brings
things up enough to echo stuff out the serial port and allow for interactive
debugging with ddb.

Tested:

* AR71xx SoCs
* AR933x SoC
* AR9344 board (DB120)

Obtained from: Qualcomm Atheros; Linux/OpenWRT

Teach the GPIO code about the AR934x GPIO register and pin counts.

Use the UART frequency when programming the UART clock.

This allows the 16550 support to work correctly on the upcoming
AR934x support.

Initialise the watchdog and UART frequencies.

For all pre-AR933x chips, the frequency is just the APB frequency.
For the AR933x, the UART frequency is different but we just hacked around
it.

For the AR934x, there's a different PLL setting for these, so they have
to be broken out.

Add two new CPU specific definitions - the watchdog clock frequency and
the UART clock frequency.

The AR933x and AR934x have separate PLL settings for these.

Import the initial SoC register definitions for the AR934x MIPS74k SoC.

Obtained from: Linux/OpenWRT

Add AR9341, AR9342, AR9344 SoC types.

Add the AR933x SoC GPIO pin count limitation.

Fix undefined behaviour in several gpio_pin_setflags() routines (under
sys/arm and sys/mips), squelching the clang 3.3 warnings about this.

Noticed by: tinderbox and many irate spectators
Submitted by: Luiz Otavio O Souza <loos.br@gmail.com>
PR: kern/177759
MFC after: 3 days

Implement USB device reset and poweron.

Tested:

* Atheros AP131, AR9331 SoC

Fix AR933x USB support - this needs the same controller initialisation
as the AR7242.

Tested:

* Atheros AP121, AR9331
* ZyDas wifi device, and 64MB (yes, ew) USB flash storage

Implement the AR933x ethernet support.

Obtained from: OpenWRT

Implement the AR933x interrupt driven UART code.

* Enable RX and host interrupts during bus probe/attach
* Disable all interrupts (+ host ISR) during bus detach
* Enable TX DONE interrupt only when we start transmitting; clear it when
we're done.
* The RX/TX FIFO depth is still conjecture on my part. I'll fix this
shortly.
* The TX FIFO interrupt isn't an "empty" interrupt, it's an "almost empty"
interrupt. Sigh. So..
* .. in ar933x_bus_transmit(), wait for the FIFO to drain before
continuing.

I dislike having to wait for the FIFO to drain, alas.

Tested:

* Atheros AP121 board, AR9331 SoC.

TODO:

* RX/TX overflow, RX error, BREAK support, etc.
* Figure out the true RX/TX FIFO depth.

AR9330/AR9331 also needs to ACK the APB interrupt register, same as
AR724x.

This fixes 'stuck interrupt' problems I was having when writing the
uart interrupt code.

* Add AR9330/AR9331 to the soc identifier enum;
* Set it when probing the CPU type.

Implement AR933x polled IO uart bus code.

This implements the bus transmit/receive/sigchg/ipend methods with
a polled interrupt handler (ipend) rather than enabling hardware
interrupts.

The FIFO is faked at 16 bytes deep for now, just so the transmit
IO side doesn't suck too bad (the callout frequency limits how quickly
IO is flushed to the sender, rather than scheduling the callout more
frequently whilst there's active TX. But I digress.)

Tested:

* Atheros AP121 (AR9330) reference board, booting to multi-user interactive
mode.

AR933x CPU device improvements:

* Add baud rate and divisor programming code. See below for more
information.

* Flesh out ar933x_init() to disable interrupts and program the initial
console setup.

* Remove #if 0'ed code from ar933x_term().

* Explain what these functions do.

Now, the baud rate and divisor code comes from Linux, as a submission
to the OpenWRT project and Linux kernel from
Gabor Juhos <juhosg@openwrt.org>.

The original ticket for this code is https://dev.openwrt.org/ticket/12031 .

I've contacted Gabor and asked for his permission to also licence the patch
in question (which covers this code) to BSD lience and he's agreed.
Hence why I'm including it here in FreeBSD.

Tested:

* AP121 (AR9330)

AR933x UART updates:

* Default clock is 25MHz;
* Remove the UART register macro here - it's not needed as we don't need
to "adjust" the register offset / spacing at all;
* Remove unused fields in the softc.

Tested:

* AP121

For the AR933x UART, the serial clock is not the AHB clock, it's the
reference clock. So use that instead.

* Fix clock register definitions
* Add maximum clock register values

Print out the platform reference frequency.

This is useful for AR933x platforms where that matters.

Tie in the AR933x support into -HEAD.

Bring over the initial, CPU-only UART support for the AR933x SoC.

This implements the kernel glue needed (getc, putc, rxready).

This isn't a 16550 UART, even if the datasheet overview claims so.

The Linux ar933x support was used as a reference, however the uart code
is a reimplementation.

Attentive viewers will note that the uart code is based off of the ns8250
code and the UART bus code is a stubbed-out version of this. I'll be
replacing it with non-stubbed versions soon, making this a fully featured
driver.

Tested:

* AP121 reference board (AR933x), booting through the mountroot> prompt;
then doing some basic interactive tests in ddb.

Fix the AR933x platform device start/stop code.

This was ported from the AR724x code and I think that also doesn't
quite work. I'll investigate that soon.

With this in place the system reset path works, so 'reset' from kdb
actually resets the SoC.

Tested:

* AP121 test board

Commit initial (unfinished!) support for the AR933x series of embedded
CPUs.

The AR933x is a mips24k based SoC with an AR9380 series SoC on board,
two gigabit ethernet interfaces and an internal 10/100mbit ethernet
switch. There's also the normal interfaces (USB, ethernet, uart, GPIO.)

The downside? There's a non-ns8250 UART device.

With a very basic UART driver (not in this commit) the SoC is initialised
and boots up. I'll commit the UART code soon and then link it into the
general setup path.

This code is a re-implementation based from the Linux kernel / openwrt
AR933x support.

TODO:

* UART (obviously)
* All of the ethernet, USB and wifi SoC glue, including ethernet PLL
programming.

Add the reference clock for each supported chip.

Obtained from: Linux (openwrt)

Mips Atheros AR71XX: make PCI base slot configurable through hints.

* Mikrotik RouterBoard 433AH have PCI slot 18 wired to INT0 on the PCI Bus.
This is different from e.g. Atheros PB42 and Ubiquiti boards.
* Check for hint hint.pcib.0.baseslot=X, where X is number of base slot;
* If hint not supplied print a warning and use default AR71XX_PCI_BASE_SLOT;

PR: kern/174978
Approved by: adrian (mentor)

Mechanically substitute flags from historic mbuf allocator with
malloc(9) flags within sys.

Exceptions:

- sys/contrib not touched
- sys/mbuf.h edited manually

Make MIPS24k PMC optional on "hwpmc_mips24k."

Requested by: juli

Migrate the AR71xx UART (an 8250 derivative) to hide behind uart_ar71xx.

The AR9330/AR9331 UART is a totally different thing, so having it included
with 'uart' is not going to work out.

Ensure that BAR(0) is set for the PCI slot before the ath(4) PCI registers
are written out.

This allows EEPROM-less NICs on the AR7241 PCIe bus to be correctly
initialised.

Tested:

* AP91 (AR7240+AR9285) - the existing board support didn't break;
* AP99 (AR7241+AR9287) - this fixed the configuration of the AR9287 PCI.

The GPIO drivers were initialising their mutexes with type of
MTX_NETWORK_LOCK. This is wrong since these mutexes have nothing to do
with networking.

Disable setting the MII port speed.

This seems to break at least my test board here (AR71xx + AR8316 switch
PHY). Since I do have a whole sleuth of "normal" PHY boards (with
an AR71xx on a normal PHY port), I'll do some further testing with those
to determine whether this is a general issue, or whether it's limited
to the behaviour of the "fake" dedicated PHY port mode on these atheros
switches.

Fix a totally bone-headed, last minute bounds check snafu that somehow
I must've missed when booting a test kernel.

This has been validated on the AR7161.

Implement PLL configuration override support, similar to what openwrt
implements.

Allow the MII mode to be overridden via 'hint.arge.X.miimode'.

It takes a number at the moment, rather than a string.

Some of the Linux board configurations specify the MII mode explicitly.

Add a missing newline.

Further ar71xx MII support improvements.

* Flesh out the PLL configuration fetch function, which will return the PLL
configuration based on the unit number and speed.
* Remove the PLL speed config logic from the AR71xx/AR91xx chip PLL config
function - pass in a 'pll' value instead.
* Modify arge_set_pll() to:
+ fetch the PLL configuration
+ write the PLL configuration
+ update the MII speed configuration.

This will allow if_arge to override the PLL configuration as required.

Obtained from: Linux/Atheros/OpenWRT

MII related infrastructure changes.

* Add a new method to set the MII mode - GMII, RGMII, RMII, MII.
+ arge0 supports all four (two for non-Gige interfaces.)
+ arge1 only supports two (one for non-gige interfaces.)
* Set the MII clock speed when changing the MAC PLL speed.
+ Needed for AR91xx and AR71xx; not needed for AR724x.

Tested:

* AR71xx only, I'll do AR913x testing tonight and fix whichever issues
creep up.

TODO:

* Implement the missing AR7242 arge0 PLL configuration, but don't
adjust the MII speed accordingly.
* .. the AR7240/AR7241 don't require this, so make sure it's not set
accidentally.

Bugs (not fixed here):

* Statically configured arge speeds are still broken - investigate why
that is on the AP96 board. Autonegotiate is working fine, but there
still seems to be an occasionally heavy packet loss issue.

Obtained from: Linux/Atheros/OpenWRT

Introduce an enum which encapsulates the PHY interface types that can be
configured.

Add in the MII configuration parameters for the AR71xx.

Obtained from: Linux/OpenWRT

Break out the arge MDIO bus code into an optional argemdio device.

This is only done if the ARGE_MDIO option is included.

* Shuffle the arge MDIO bus into a separate device, that needs to be
probed early (use hint.argemdio.X.order=0)
* hint.arge.X.mdio now specifies which miiproxy to rendezvous with.
* Call MAC/MDIO bus init during MDIO attach, not arge attach.

This is done regardless:

* Shift the arge MAC and MDIO bus reset code into separate functions
and call it early during MDIO bus attach. It's required for
correct MDIO bus IO to occur on AR71xx/AR91xx devices.

* Remove the AR71xx/AR91xx centric assumption that there's only one
MDIO bus. The initial code mapped miibus0(arge0) and miibus1(arge1)
MII register operations to the MII0 (arge0) register space. The
AR724x (and later, upcoming chipsets) have two MDIO busses and
the second is very much in use.

TODO:

* since the multiphy behaviour has changed (where now a phymask of >1
PHY will still be enumerated), multiphy setups may be quite wrong.
I'll go and fix these so they still have a chance of working, at least.
until the switch PHY support appears in -HEAD.

Submitted by: Stefan Bethke <stb@lassitu.de>

Migrate ARGE_DEBUG to opt_arge.h.

Submitted by: Stefan Bethke <stb@lassitu.de>

Allow for a default GPIO pin "high", which is required for some boards
which tie the USB device enable to a GPIO line.

Submitted by: Stefan Bethke <stb@lassitu.de>

Introduce the matching PCI ath(4) fixup code from ar71xx_pci into
ar724x_pci.c.

* Move out the code which populates the firmware into ar71xx_fixup.c
* Shuffle around the ar724x fixup code to match what the ar71xx fixup
code does.

I've validated this on an AR7240 with AR9285 on-board NIC. It doesn't
yet load, as the AR9285 EEPROM code needs to be made "flash aware."

TODO:

* Validate that I haven't broken AR71xx
* Test AR9285/AR9287 onboard NICs, complete with EEPROM code changes
* Port over the needed BAR hacks for AR7240, AR7241 and AR7242 from
Linux OpenWRT. The current WAR has only been tested on the AR7240
and I'm not sure the way the BAR register is treated is "right".
The "fixup" method here is right when setting the BAR for local access -
ie, the BAR address is either 0xffff (AR7240) or 0x1000ffff (AR7241/AR7242),
but the ath9k-fixup.c code (Linux OpenWRT) does this when setting the
initial "fixup" BAR. It then restores the original BAR.
I'll have to read the ar724x PCI bus glue to see what other special cases
await.

Style(9) and white space fixes.

Protect the PCI space registers behind a mutex.

Obtained from: Linux/OpenWRT, Atheros

The AR913x MII speed configuration matches the AR71xx MII configuration.
So share the code.

Don't do it for the AR724x - that has a completely different set of PLL
and MII configuration parameters.

Fix the mask logic when reading PCI configuration space registers.

(ab)Use the firmware API to store away EEPROM calibration data for
future use by the ath(4) driver.

These embedded devices put the calibration/PCI bootstrap data on the
on board SPI flash rather than on an EEPROM connected to the NIC.
For some boards, there's two NICs and two sets of EEPROM data in the
main SPI flash.

The particulars:

* Introduce ath_fixup_size, which is the size of the EEPROM area in
bytes.
* Create a firmware image with a name based on the PCI device identifier
(bus/slot/device/function).
* Hide some verbose debugging behind 'bootverbose'.

ath(4) can then use this to load in the EEPROM data.

This requires AR71XX_ATH_EEPROM to be defined.

Remove an unused variable. Grr.

Sync this code against what's in OpenWRT trunk.

* the openwrt code doesn't treat 0/0/0 any differently
from other bus/slot/func combinations.
* A "local write" function writes to the LCONF area, and
so I've added it.
* The PCI workaround at attach time uses this LCONF code,
which it already did ..
* .. but it is a 4 byte write, not a 2 byte write.
Even though it's PCIR_COMMAND which is a two byte PCI register.

Tested on: AR7161
TODO: The other two AR71xx derivatives
TODO: More thoroughly stare at the datasheets I do have
and if it indeed is incorrect, push fixes to both
FreeBSD and Linux/OpenWRT.

Obtained from: Linux OpenWRT

Assume a big-endian default on MIPS and drop the "eb" suffix from MACHINE_ARCH.
This makes our naming scheme more closely match other systems and the
expectations of much third-party software. MIPS builds which are little-endian
should require and exhibit no changes. Big-endian TARGET_ARCHes must be
changed:
From: To:
mipseb mips
mipsn32eb mipsn32
mips64eb mips64

An entry has been added to UPDATING and some foot-shooting protection (complete
with warnings which should become errors in the near future) to the top-level
base system Makefile.

Rework MIPS PMC code:

- Replace MIPS24K-specific code with more generic framework that will
make adding new CPU support easier
- Add MIPS24K support for new framework
- Limit backtrace depth to 1 for stability reasons and add option
HWPMC_MIPS_BACKTRACE to override this limitation

Move PMC hook invocation to cpu_intr. The idea is the same as with ast()
call but there is no reason to implement it in assembler.

- Fix logic for detection if further processing of PMC should be performed.
pmc_intr returns one if one of the counters actually triggered the IRQ
- style(9) fixed

style(9) changes.

Begin fleshing out MII clock rate configuration changes.

These are needed for some particular port configurations where the default
speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit
PLL rate requires a similar MII clock rate, rather than a fixed MII rate.)

This is:

* only currently implemented for the ar71xx;
* isn't used anywhere (yet), as the final interface for this hasn't yet
been determined.

Remove a now unneeded ARGE_UNLOCK().

Whilst I'm here, remove a couple blank lines.

Fix link status handling on if_arge upon system boot to allow bootp/NFS to
function.

From the submitter:

This patch fixes an issue I encountered using an NFS root with an
ar71xx-based MikroTik RouterBoard 450G on -current where the kernel fails
to contact a DHCP/BOOTP server via if_arge when it otherwise should be able
to. This may be the same issue that Monthadar Al Jaberi reported against
an RSPRO on 6 March, as the signature is the same:

%%%

DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
.
.
.
DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
arge0: initialization failed: no memory for rx buffers
DHCP/BOOTP timeout for server 255.255.255.255
arge0: initialization failed: no memory for rx buffers

%%%

The primary issue that I found is that the DHCP/BOOTP message that
bootpc_call() is sending never makes it onto the wire, which I believe is
due to the following:

- Last December, a change was made to the ifioctl that bootpc_call() uses
to adjust the netmask around the sosend().

- The new ioctl (SIOCAIFADDR) performs an if_init when invoked, whereas the
old one (SIOCSIFNETMASK) did not.

- if_arge maintains its own sense of link state in sc->arge_link_status.

- On a single-phy interface, sc->arge_link_status is initialized to 0 in
arge_init_locked().

- sc->arge_link_status remains 0 until a phy state change notification
causes arge_link_task to run, notice the link is up, and set it to 1.

- The inits caused by the ifioctls in bootpc_call are reinitializing the
interface, but not the phy, so sc->arge_link_status goes to 0 and remains
there.

- arge_start_locked() always sees sc->arge_link_status == 0 and returns
without queuing anything.

The attached patch changes arge_init_locked() such that in the single-phy
case, instead of initializing sc->arge_link_status to 0, it runs
arge_link_task() to set it according to the current phy state. This change
has allowed my setup to mount an NFS root successfully.

Submitted by: Patrick Kelsey <kelsey@ieee.org>
Reviewed by: juli

Correctly (I hope) deallocate the if_arge RX buffer ring on arge_stop().

I had some interesting hangs until I realised I should try flushing the
DDR FIFO register and lo and behold, hangs stopped occuring.

I've put in a few DDR flushes here and there in case people decide to
reuse some of these functions. It's very very likely they're almost
all superflous.

To test:

* Connect to a network with a _lot_ of broadcast traffic
* Do this:
# while true; do ifconfig arge0 down; ifconfig arge0 up; done

This fixes the mbuf exhaustion that has been reported when the interface
state flaps up/down.

o) Use ABI, not ISA_* options, to determine whether to compile bits if libkern
required for the ABI the kernel is being built for.
XXX This is implemented in a kind-of nasty way that involves including source
files, but it's still an improvement.
o) Retire ISA_* options since they're unused and were always wrong.

Remove platform APIs which are not used by any code and which had only stub
implementations or no implementation on all platforms.

Some of these functions might be good ideas, but their semantics were unclear
given the lack of implementation, and an unlucky porter could be fooled into
trying to implement them or, worse, being baffled when something like
platform_trap_enter() failed to be called.

- Rename apb_intr to apb_filter since it's a filter handler
- Pass interrupt trapframe for handlers dow the chain
- Add PMC interrupt handler
PMC interrupt is a special case, so we want handle it as soon as possible
with minimum overhead. So we handle it apb filter routine.

Break long lines.

Approved by: adri (mentor)

Remove EoL whitespaces.

Approved by: adri (mentor)

Stop overloading opt_global.h.

Some of the atheros based embedded devices use one or more PCI NICs
on-board, glued to the AR71xx CPU. These may forgo separate WMAC EEPROMs
(which store configuration and calibration data) and instead store
it in the main board SPI flash.

Normally the NIC reads the EEPROM attached to it to setup various PCI
configuration registers. If this isn't done, the device will probe as
something different (eg 0x168c:abcd, or 0x168c:ff??.) Other setup registers
are also written to which may control important functions.

This introduces a new compile option, AR71XX_ATH_EEPROM, which enables the
use of this particular code. The ART offset in the SPI flash can be
specified as a hint against the relevant slot/device number, for example:

hint.pcib.0.bus.0.17.0.ath_fixup_addr=0x1fff1000
hint.pcib.0.bus.0.18.0.ath_fixup_addr=0x1fff5000

TODO:

* Think of a better name;
* Make the PCIe version of this fixup code also use this option;
* Maybe also check slot 19;
* This has to happen _before_ the SPI flash is set from memory-mapped
to SPI-IO - so document that somewhere.

Fix the ar724x shift calculation when writing to the PCI config space.

This was preventing the ath driver from being loaded at runtime.
It worked fine when compiled statically into the kernel but not when
kldload'ed after the system booted.

The root cause was that PCIR_INTLINE (register 60) was being
overwritten by zeros when register 62 was being written to.
A subsequent read of this register would return 0, and thus
the rest of the PCI glue assumed an IRQ resource had already
been allocated. This caused the device to fail to attach at
runtime as the device itself didn't contain any IRQ resources.

TODO: go back over the ar71xx and ar724x PCI config read/write
code and ensure it's correct.

Remove these locks - they aren't strictly needed and cause measurable
performance issues.

* Access to the GPIO bus is already locked by requesting
and releasing the bus - thus the lock isn't really needed
for each GPIO pin change.
* Don't lock and unlock the GPIO bus for -each- i2c access -
the i2c bus code is already doing this by calling the upper
layer callback to request/release the bus. This thus locks
the bus for the entirety of the transaction.

TODO:

* Further verify that everything is correctly requesting/
releasing the GPIO bus.
* Look at how to lock the GPIO pin configuration stuff,
potentially by locking/unlocking the bus at the gpiobus
layer.

Re-jiggle the GPIO code a little to remove the hard-coded AR71xx GPIO
config and function mask setup.

* "gpiomask" now specifies which GPIO pins to enable, for devices to bind to.
* "function_set" allows bits in the function register to be set at GPIO setup.
* "function_clear" allows bits in the function register to be cleared at
GPIO setup.

The function_set/function_clear bits allow for individual GPIO pins to either
drive a GPIO line or an alternate function - eg USB, JTAG, etc. This allows
for things like CS1/CS2 be enabled for those boards w/ >1 SPI device connected,
or disabling JTAG for the AR7240 (which is apparently needed ..)

I've verified this on the AR71xx.

Implement better support for USB controller suspend and resume.

This patch should remove the need for kldunload of USB
controller drivers at suspend and kldload of USB controller
drivers at resume.

This patch also fixes some build issues in avr32dci.c

MFC after: 2 weeks

Style(9) changes.

Simplify arge_flush_ddr to use updated ar71xx_device_flush_ddr_ge(unit).

Approved by: adrian (mentor)

Fix build, fininshing r228018.

Join chip depended methods for arge0 and arge1 into single call with unit.

Approved by: adrian (mentor)

Introduce a new (global, sorry!) option which controls whether
the ar71xx platform code should assume a uboot or redboot environment.

The current code gets very confused (and just crashes) on a uboot
environment, where each attribute=value pair is in a single entry.
Redboot on the other hand stores it as "attribute", "value", "attribute",
"value", ...

This allows the kernel to boot on a TP-LINK TL-WR1043ND from flash,
where the uboot environment gets setup. This didn't show up during a netboot
as "tftpboot" and "go" don't setup the uboot environment variables.

Rename device_delete_all_children() into device_delete_children().

Suggested by: jhb @ and marius @
MFC after: 1 week

- There's no need to overwrite the default device method with the default
one. Interestingly, these are actually the default for quite some time
(bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9)
since r52045) but even recently added device drivers do this unnecessarily.
Discussed with: jhb, marcel
- While at it, use DEVMETHOD_END.
Discussed with: jhb
- Also while at it, use __FBSDID.

Close a race where SIOCGIFMEDIA ioctl get inconsistent link status.
Because driver is accessing a common MII structure in
mii_pollstat(), updating user supplied structure should be done
before dropping a driver lock.

Reported by: Karim (fodillemlinkarimi <> gmail dot com)

Remove duplicate header includes

Fix GPIO_MAXPINS calculation for the AR71xx, AR724x, AR913x SoC.

Submitted by: Luiz Otavio O Souza <loos.br@gmail.com>

- Remove attempts to implement setting of BMCR_LOOP/MIIF_NOLOOP
(reporting IFM_LOOP based on BMCR_LOOP is left in place though as
it might provide useful for debugging). For most mii(4) drivers it
was unclear whether the PHYs driven by them actually support
loopback or not. Moreover, typically loopback mode also needs to
be activated on the MAC, which none of the Ethernet drivers using
mii(4) implements. Given that loopback media has no real use (and
obviously hardly had a chance to actually work) besides for driver
development (which just loopback mode should be sufficient for
though, i.e one doesn't necessary need support for loopback media)
support for it is just dropped as both NetBSD and OpenBSD already
did quite some time ago.
- Let mii_phy_add_media() also announce the support of IFM_NONE.
- Restructure the PHY entry points to use a structure of entry points
instead of discrete function pointers, and extend this to include
a "reset" entry point. Make sure any PHY-specific reset routine is
always used, and provide one for lxtphy(4) which disables MII
interrupts (as is done for a few other PHYs we have drivers for).
This includes changing NIC drivers which previously just called the
generic mii_phy_reset() to now actually call the PHY-specific reset
routine, which might be crucial in some cases. While at it, the
redundant checks in these NIC drivers for mii->mii_instance not being
zero before calling the reset routines were removed because as soon
as one PHY driver attaches mii->mii_instance is incremented and we
hardly can end up in their media change callbacks etc if no PHY driver
has attached as mii_attach() would have failed in that case and not
attach a miibus(4) instance.
Consequently, NIC drivers now no longer should call mii_phy_reset()
directly, so it was removed from EXPORT_SYMS.
- Add a mii_phy_dev_attach() as a companion helper to mii_phy_dev_probe().
The purpose of that function is to perform the common steps to attach
a PHY driver instance and to hook it up to the miibus(4) instance and to
optionally also handle the probing, addition and initialization of the
supported media. So all a PHY driver without any special requirements
has to do in its bus attach method is to call mii_phy_dev_attach()
along with PHY-specific MIIF_* flags, a pointer to its PHY functions
and the add_media set to one. All PHY drivers were updated to take
advantage of mii_phy_dev_attach() as appropriate. Along with these
changes the capability mask was added to the mii_softc structure so
PHY drivers taking advantage of mii_phy_dev_attach() but still
handling media on their own do not need to fiddle with the MII attach
arguments anyway.
- Keep track of the PHY offset in the mii_softc structure. This is done
for compatibility with NetBSD/OpenBSD.
- Keep track of the PHY's OUI, model and revision in the mii_softc
structure. Several PHY drivers require this information also after
attaching and previously had to wrap their own softc around mii_softc.
NetBSD/OpenBSD also keep track of the model and revision on their
mii_softc structure. All PHY drivers were updated to take advantage
as appropriate.
- Convert the mebers of the MII data structure to unsigned where
appropriate. This is partly inspired by NetBSD/OpenBSD.
- According to IEEE 802.3-2002 the bits actually have to be reversed
when mapping an OUI to the MII ID registers. All PHY drivers and
miidevs where changed as necessary. Actually this now again allows to
largely share miidevs with NetBSD, which fixed this problem already
9 years ago. Consequently miidevs was synced as far as possible.
- Add MIIF_NOMANPAUSE and mii_phy_flowstatus() calls to drivers that
weren't explicitly converted to support flow control before. It's
unclear whether flow control actually works with these but typically
it should and their net behavior should be more correct with these
changes in place than without if the MAC driver sets MIIF_DOPAUSE.

Obtained from: NetBSD (partially)
Reviewed by: yongari (earlier version), silence on arch@ and net@

Some AR724x PCIe fixes, which should wrap up the first round
of endian-ness issues with the AR724x.

From Luiz:

* Fix the bus space tag used so endian-ness is correctly handled;
* Only do the workaround for the AR7240; AR7241/AR7242 (PB92)
don't require this

From me:

* Add a read flush from openwrt

Submitted by: Luiz Otavio O Souza

The AR724x SoC's require the irq status line to be acked/cleared.

This allows console IO to occur correctly once the kernel is in multi-user
mode.

Submitted by: Luiz Otavio O Souza

Call the DDR FIFO flush method when IP2 interrupts occur.

Flip off debugging for now.

Add some initial PCIe bridge support for the AR724x chipsets.

This is reported to work on the AR7240 based Ubiquiti Rocket M5
but I haven't tested it on that hardware. I also don't yet have
it fully working on the AR7242 based development board here;
probe/attach functions but the register space resource looks like
the endian-ness is wrong (0x10000000 instead of 0x00001000).o

Further digging will be required.

Submitted by: Luiz Otavio O Souza

In preparation for the AR724x PCIe bus code, make the AR71xx PCI bus
glue require 'device ar71xx_pci' .

Users of the AR71xx board configs will now require this for functioning
PCI:

device pci
device ar71xx_pci

Add a missing DDR FIFO method for the ar71xx.

Tidy up the naming of the ip2 DDR flush routine, and add an inline
accessor method (which is currently unused) in there.

Add the IP2 DDR flush handlers.

These aren't yet used in the interrupt handler path but should be.

We don't need to call EOWRITE4(sc, EHCI_USBINTR, 0) directly from each EHCI
bus driver at detach, hence ehci_detach() does exactly this since r199718.

Submitted by: Luiz Otavio O Souza
MFC after: 7 days
Approved by: thompsa (mentor)

if_arge has had a strange bug that only appears during high traffic
levels. TX would hang, RX wouldn't. A bit of digging showed the interface
send queue was full, but IFF_DRV_OACTIVE was clear and the hardware TX
queue was empty.

It turns out that there wasn't a check to drain the interface send
queue once hardware TX had completed, so if the interface send queue
had filled up in the meantime, subsequent packets would be dropped
by the higher layers and if_start (and thus arge_start()) would never
be called.

The fix is simple - call arge_start_locked() in the software interrupt
handler after the hardware TX queue has been handled or a TX underrun
occured. This way the interface send queue gets drained.

* Add some more debugging to if_arge
* Make doubly sure that IFF_DRV_OACTIVE is set if the hardware TX queue is full

Put the ARGE_DEBUG behind a kernel config option.

Begin fleshing out a functioning debugging setup for if_arge.

I'm seeing TX hangs when doing large amounts of TX traffic;
an interface reset fixes it. This will hopefully help me identify
why.

- Correct EHCI interrupt disabling at detach.

Submitted by: Luiz Otavio O Souza
MFC after: 7 days
Approved by: thompsa (mentor)

Add in some missing flags in the EHCI initialisation code,
needed to get USB working on the AR913x/AR724x.

A handful of the openwrt devices use a MAC address that's at a hard-coded
offset in the flash.

Some devices (eg the TPLink WR-1043ND) don't have a flash environment
partition which can be queried for the current board settings.

This particular workaround allows for image creators to use a hint
to set the base MAC address. For example:

hint.arge.0.eeprommac=0x1f01fc00

Implement AR724x USB initialisation code.

This (again) still requires an offset for the AR913x/AR724x before USB will
function.

Submitted by: Luiz Otavio O Souzau <loos.br@gmail.com>

The previous commit didn't completely rename this to what it should be.

Refactor out the ar71xx mac address code into something that's
just for Redboot.

At some point we're going to need to build options for different
boot environments - for example, the UBoot setups I've seen simply
have the MAC address hard-coded at a fixed location in flash.
The OpenWRT support simply yanks the if_arge MAC directly from that
in code, rather than trying to find a uboot environment to pull it
from.

Add an option - AR71XX_REALMEM - which overrides the amount of
memory detected from Redboot, or overrides the "otherwise" case
if no Redboot information was found.

Some AR71XX platforms don't use Redboot (eg TP-LINK devices using
UBoot; some later Ubiquiti devices which apparently also use
UBoot) and at least one plain out lies - the Ubiquiti LS-SR71A
Redboot says there's 16mb of RAM when in fact there's 32mb.

A more "clean" solution will be needed at a later date.

Add some missing flags needed for AR913x/AR724x USB to correctly operate.

The AR913x/AR724x USB lives at a different offset to the AR71xx
USB, so this needs to be either adjusted for in a subsequent
commit, or updated in hints for kernels compiled for those
platforms.

Submitted by: Luiz Otavio O Souzau <loos.br@gmail.com>

* Add wireless MAC reset, in prep for bringing over AR9130 support.
* Whilst I'm here, reformat to fit inside 80 characters.

Add the missing AR724x DDR flush routines for if_arge0.

Submitted by: Luiz Otavio O Souza

Fix the TX underrun status reset; remove a now unused variable.

Submitted by: Luiz Otavio O Souza

Commit FIFO configuration fixes from OpenWRT. This fixes performance
issues with if_arge on the AR913x and AR724x.

Reference: https://dev.openwrt.org/ticket/6754
Submitted by: Luiz Otavio O Souza

Add missing ar91xx definition for the WMAC reset control.

- Populate dump_avail with proper values from phys_avail

Remove the 'machine mips' from DEFAULTS. Put the proper 'machine mips
mipsel' or 'machine mips mipseb' into the config file (with a few 64's
tossed in for good measure). This will let us build the proper
kernels with different worlds as part of make universe.

Converted the remainder of the NIC drivers to use the mii_attach()
introduced in r213878 instead of mii_phy_probe(). Unlike r213893 these
are only straight forward conversions though.

Reviewed by: yongari

- Fix values of CS1_EN and CS2_EN flags
- Unbreak kernel build by fixing naming convention of
GPIO_FUNC flags

Spotted by: Luiz Otavio O Souza, Andrew Thompson

AR71XX_GPIO_* defines were introduced by adrian@ a while ago,
remove duplicated.

Add AR71XX GPIO bus driver.

Make a note of which platforms the mac strings come from.

Suggested by: adrian

Use getenv to find the mac address since it could be in the bootloader
environment or command line and under different names.

bus_add_child: change type of order parameter to u_int

This reflects actual type used to store and compare child device orders.
Change is mostly done via a Coccinelle (soon to be devel/coccinelle)
semantic patch.
Verified by LINT+modules kernel builds.

Followup to: r212213
MFC after: 10 days

Migrate if_arge to use the PLL cpuops.

This has been lightly tested on the AR7161 and AR9132.

Implement PLL generalisation in preparation for use in if_arge.

* Add a function to write to the relevant PLL register
* Break out the PLL configuration for the AR71XX into the CPU ops,
lifted from if_arge.c.
* Add the AR91XX PLL configuration ops, using the AR91XX register
definitions.

add the PLL set functions to cpuops

Fix mistaken indenting.

Add some initial AR724X chipset support.

This is untested but should at least allow an AR724X to boot.

The current code is lacking the detail needed to expose the PCIe bus.
It is also lacking any NIC, PLL or flush/WB code.

Add initial Atheros AR91XX support.

This works well enough to bring a system up to single-user mode
using an MDROOT.

Known Issues:

* The EHCI USB doesn't currently work and will panic the kernel during
attach.
* The onboard ethernet won't work until the PLL routines have been
fleshed out and shoe-horned into if_arge.
* The WMAC device glue (and quite likely the if_ath support)
hasn't yet been implemented.

Add missing licence.

style(9) pick from imp@ .

Remove now unused 'reg'.

Initialise the USB system using cpuops rather than the AR71XX specific method.

Migrate the CPU reset path to use the new cpuops.

Remove the now-unused DDR flush register value.

Make the PCI initialisation path use the new cpuops rather than directly
programming the reset register.

Make if_arge use the new cpuops rather than hard coding the DDR flush registers.

Preparation work for supporting the AR91xx and AR724x.

* Implement a SoC probe function, from Linux, which determines the
SoC family, type and revision. This only probes the AR71xx series
SoC and (currently) panics on others.

* Migrate some of the AR71XX specific hardware init (USB device, determining
system frequencies) into using the cpuops introduced in an earlier commit.
Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring,
Ethernet PLL setup, other things I've likely missed) will be introduced in
subsequent commits.

Reviewed by: imp@
Obtained from: (partially) Linux

Add a DDR flush function, inspired by both Linux and if_arge.c.

Add a further register definition for USB device initialisation.

Obtained from: Linux

Bring over the first cut of the Atheros-specific SoC operations.

Each of these SoCs have different devices, different hardware initialisation
methods and, quite likely, different quirks. These functions will abstract
out the SoC differences and keep these differences out of the drivers (eg
USB init, if_arge, etc.)

Import initial AR91XX and AR724X CPU register definitions.

Obtained from: Linux

- Add interrupts counter for PCI devices

Add TX-path aligned/unaligned stats for if_arge.

Address PR kern/148307 - fix if_ath TX mbuf alignment/size constraint checks

The existing code only checked the alignment of the first mbuf and
didn't enforce the size constraints.

This commit introduces a simple function to check the alignment and
size of all mbufs in the list. This fixes the initial issue in the
PR.

PR: kern/148307
Reviewed by: gonzo@

Introduce a sysctl block for if_arge and, for now, a blank debug sysctl
placeholder for later.

Add in a missing FreeBSD ID string.

Fix the CS line definitions. These bits are for the CS2/CS1 lines
rather than CS1/CS0.

This has been tested on the Ubiqiti Routerstation Pro board.

Comment about the shared pins I know about.

AR71XX GPIO register definitions.

Reviewed by: gonzo@

Extend the AR71XX watchdog debugging and data.

* Add some per-device sysctl entries which record the watchdog state -
whether it is armed; whether the last reboot was due to the watchdog.
* Add a per-device sysctl debug flag to enable logging watchdog arming/
disarming.

Reviewed by: gonzo@

Add new tunable 'net.link.ifqmaxlen' to set default send interface
queue length. The default value for this parameter is 50, which is
quite low for many of today's uses and the only way to modify this
parameter right now is to edit if_var.h file. Also add read-only
sysctl with the same name, so that it's possible to retrieve the
current value.

MFC after: 1 month

- Fix mutex type for miibus_mtx: it's not spinlock, it's def lock

Define DMA_RX_STATUS_OVERFLOW with correct value.

The RX overflow is reported in bit 2 on real hardware and Linux driver
for the same device already has this defined correctly.
This fixes frequent interrupt storms seen on RouterStation Pro boards.

Discussed with: gonzo

- Increase timeouts to 100 milliseconds, 1 millisecond is definitely not
enough for PCI controller to get into shape

Thanks to: adrian@

- Call post-boot fixup function in order to get proper static
symbols resolving in DDB
- When zeroing .bss/.sbss do not round end address to page boundary,
it's not neccessary and might destroy data pased by trampoline or
boot loader

Update from old DDB convetion to initialize debugger to new KDB way.
Always call kdb_init(). If we have KDB enabled, then provide a handy
place to break to the debugger.

- Add driver for PCF2123, SPI real time clock/calendar

- Remove unnecessary register writes in activate_device
and deactivate_device
- Save state before attaching driver and restore it when
detaching
- Clear CLK bit after last bit of byte has been sent over
the bus providing falling edge for last byte in transfer
- Fix several places where CS0 was always assumed
- Add $FreeBSD$ to ar71xxreg.h

Set the svn:eol-style = native and svn:mime-type = text/plain
properties on all files in this tree.

Submitted by: rpaulo@

Place proper svn:keywords tag on all these files. They were created
somehow without them on projects/mips, and that mistake was propigated
over to head.

Submitted by: rpaulo@

Using svn cp rather than cp to copy these files over had the benefit
of preserving their history. It had the problem that it also copied
over mergeinfo data. Since we're retiring the projects/mips branch,
I'm removing the svn:mergeinfo property from them all.

Submitted by: jhb

Merge from projects/mips to head by hand:

Merge support files for the Atheros AR71xx (and soon AR9xxx)
processors, except files from sys/conf and sys/mips/conf. This work
was done primarily by Olecksandr Tymoshenko and works on the
RouterStation and RouterStation PRO. Other AR71xx-based boards have
been reported as working as well (RouterBoard, for example).

Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the
BSP. Provide a missing prototype.

Centralize initialization of pcpu, and set curthread early...

- Add intr counters for APB interrupts

- Handle multiphy MAC case: create interface with
fixed-state media with parameters set via hints
and configure MAC accordingly to these parameters.
All the underlying PHY magic is done by boot manager
on startup. At the moment there is no proper way
to make active and control all PHYs simultaneously
from one MII bus and there is no way to associate
incoming/outgoing packet with specific PHY.

- include register definitions for respective controllers

- Access to all 5 PHYs goes through registers in MAC0 memory
space, rewrite miibus accessors respectively

- Fix: Wrong register is used for initial value reading

- Fix initialization of PLL registers (different shifts for
arge0/arge1)
- Use base MAC address to generate MACs for arge1 and above

- Replace dumb cut'n'paste call with not to self (XXX)

- style(9): replace whitespaces with tabs

- Remove noisy "Implement me" stubs
- Handle SIOCSIFFLAGS ioctl

With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
making it run ;-)

- Fix build with DEVICE_POLLING enabled

Parse and save the command line passed in from RedBoot (exec -c "xxx") and also
the board specific environment variables.

This is not ar71xx specific and should be shared better.

Does 4 things:
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c
(which we will need for RMI) in the machine specific directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
may need to look at finding a better place to put this. But first I want to
get this thing compiling.

- Fix CPU divisor mask

Repored by: Luiz Otavio O Souza

- Remove flags accidently brought by dumb cut'n'paste coding

- Fix phy address calculation

- Make USB part of AR71XX kernel buildable again

- Add AR71XX watchdog timer driver

- Move CPU/AHB frequency calculations to functions to
prevent code duplication

- Fix PCI routing code

- Fix off-by-one bug in arge_fixup_rx. If mbuf is located
by the end of the page and even number of bytes long,
that may cause TLBMiss exception for unallocated address.
- Fix mess with DMA sync opeartions

- Flush PCI register write before delay

Spotted by: Pyun YongHyeon

- Take into account only unmasked bits in interrupt status register

- Fix functions prototypes to make compiler happy

- Revert fix by dwhite that has been accidentally lost in r192783
commit.

- style(9) fixes
- Get rid of obsolete mask_fn

- arge_poll should be decalred only if DEVICE_POLLING is enabled
- Revert Rx buffer nsegments from BUS_SPACE_UNRESTRICTED to
ARGE_MAXFRAGS

- Add polling support
- Get rid of arge_fix_chain, use m_defrag like if_vr
- Rework interrupt handling routine to avoid race that lead
to disabling RX interrupts
- Enable full duplex if requested
- Properly set station MAC address
- Slightly optimize RX loop
- Initialize FILTERMATCH and FILTERMASK registers as linux driver does

- Calculate clock frequency using PLL registers

- Wrong logical operator was used for flag check

Remove unused variable.

Add some missing bits to arge:
* In arge_attach(), hard reset the MAC blocks before configuring the MAC.
* In arge_reset_dma(), clear pending packet interrupts based off
the hardware counter instead of acking every packet in the ring,
as the hardware counter can exceed the ring size. If the reset
was successful the counters will be zero anyway.
* In arge_encap(), remove an unused variable.
* In arge_tx_locked(), remove redundant setting of the EMPTY flag as
the TX DMA engine sets it for us.
* In arge_intr(), remember to clear the interrupt status bits
relayed from arge_intr_filter().
* Handle RX overflow and TX underflow.
* In arge_tx_intr(), remember to unmask the TX interrupt bits
after processing them.

- ar71xx increases Count value every two cycles

- Add SPI bus driver for ar71xx SoC

- Set MAC Address obtained from RedBoot or generate random one

- Get memory size and base MAC address from RedBoot (if available)

- Add pci bus space that translates byte order to little endian,
may be it will be merged with bus_space_reversed later
- Handle memory resources close to bus in order to control
bus_space_tag

- Calculate clock frequency using PLL registers
- Remove stale comments

- Calculate CPU frequency using dividers from PLL registers

- Add definitions for PLL CPU Config register fields

- Add SPI-related registers

- Remove garbage debug output

- Add interrupt handling for AR71XX PCI bridge

- Rollback to the hack with 3-bytes offset in base address.
uart_bus_XXXXX resources are handled in uart(4) code
and we need more sophysticated way to define which space
should be used for device based on hints

- Add APB base and size for memory rman in apb

- Handle memory requests on apb level, do not pass them up to
nexus
- Unmask IRQ in bus_intr_setup
- Do not count timer IRQ (IRQ0) as stray

- accummulate interrupt causes in filter instead of rewriting old. The only
place where status should be overrided - interrupt handler

- Remove garbage debug output
- ar71xx_bus_space_reversed is bus_space_tag_t, use it this way

- Add EHCI controller driver for AR71XX-based boards.

- Handle byte-order issue for non-word accesses to memory mapped
registers with ar71xx_bus_space_reversed. Note, that byte order
of values is handled by drivers. bus_spaces fixes only position
of register in word.
- Replace .hints hack for AR71XX UART with ar71xx_bus_space_reversed.

Fix USB2 quick'n'dirty porting, now system successfully detects OHCI

- Port AR71XX OHCI controller to new USB stack

- Revert changes accidentally killed by merge operation

- Remove some garbage output

- Add integrated OHCI controller driver, just a
wrapper around generic ohci driver

- Add some debug output
- Do not manage memory, it's not neccessary. Just pass
request up to nexus to map it to KSEG1

- Reset USB chip and init control registers

- Add USB-related registers

- Add if_arge to build

- Driver for on-board AR71XX ethernet

- Add PLL, reset, ethernet and DMA registers/values

- Add ar71xx PCI bridge implementation and link it to the build

- Rename RESET-related registers
- Add PCI registers

- Forgot to add this file to r187515

- Add apb device. apb is bridge that connects UART, GPIO,
I2S and PCM to main bus
- Connect apb and uart_bus to build

- Use new register naming convention
- Properly initialize bus_space tags for uart

- Change register/bitnumber/masks naming convention (again)
o For register names use AR71XX_REGISTER_NAME (prefix varies depending
on platform AR71XX/AR91XX/... Yes, let's hope other families are
on their way to tree, they call it positive thinking)
o For bit number use REGISTER_NAME_FIELD_NAME
o For field mask use REGISTER_NAME_FIELD_NAME_MASK

- Add newbus uart driver implementation

- Use ATH_READ_REG/ATH_WRITE_REG instead of direct memory access

- Fix platform_reset function

- Use more generic prefix for register names (ATH instead of AR71XX

- Use more generic name for atheros-based devices subdirectory. Keep old
naming scheme for files until we'll figure out common parts.

Suggested by: imp@

- style(9) fix: replace spaces with tabs

- First bits of Atheros' AR71XX port. Only UART supported ATM.