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machdep.c (1.52) machdep.c (1.53)
1/* $NetBSD: machdep.c,v 1.52 1996/05/29 06:25:04 mhitch Exp $ */
1/* $NetBSD: machdep.c,v 1.53 1996/06/15 08:57:52 jonathan Exp $ */
2
3/*
4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer

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177
178#ifdef DS5100 /* mipsmate */
179# include <pmax/pmax/kn230var.h> /* kn230_establish_intr(), kn230_intr() */
180#endif
181
182#ifdef DS5000_240
183int kn03_intr();
184#endif
2
3/*
4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer

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177
178#ifdef DS5100 /* mipsmate */
179# include <pmax/pmax/kn230var.h> /* kn230_establish_intr(), kn230_intr() */
180#endif
181
182#ifdef DS5000_240
183int kn03_intr();
184#endif
185
185extern int Mach_spl0(), Mach_spl1(), Mach_spl2(), Mach_spl3(), splhigh();
186int (*Mach_splbio)() = splhigh;
187int (*Mach_splnet)() = splhigh;
188int (*Mach_spltty)() = splhigh;
189int (*Mach_splimp)() = splhigh;
190int (*Mach_splclock)() = splhigh;
191int (*Mach_splstatclock)() = splhigh;
192extern volatile struct chiptime *Mach_clock_addr;
193u_long kmin_tc3_imask, xine_tc3_imask;
186extern int Mach_spl0(), Mach_spl1(), Mach_spl2(), Mach_spl3(), splhigh();
187int (*Mach_splbio)() = splhigh;
188int (*Mach_splnet)() = splhigh;
189int (*Mach_spltty)() = splhigh;
190int (*Mach_splimp)() = splhigh;
191int (*Mach_splclock)() = splhigh;
192int (*Mach_splstatclock)() = splhigh;
193extern volatile struct chiptime *Mach_clock_addr;
194u_long kmin_tc3_imask, xine_tc3_imask;
195
194#ifdef DS5000_240
195u_long kn03_tc3_imask;
196extern u_long latched_cycle_cnt;
197#endif
196#ifdef DS5000_240
197u_long kn03_tc3_imask;
198extern u_long latched_cycle_cnt;
199#endif
200
198tc_option_t tc_slot_info[TC_MAX_LOGICAL_SLOTS];
199static void asic_init();
200extern void RemconsInit();
201
201tc_option_t tc_slot_info[TC_MAX_LOGICAL_SLOTS];
202static void asic_init();
203extern void RemconsInit();
204
202#ifdef DS5000
203
204#if 1 /*def DS5000_200*/
205#ifdef DS5000_200
205void kn02_enable_intr __P ((u_int slotno,
206 int (*handler) __P((intr_arg_t sc)),
207 intr_arg_t sc, int onoff));
206void kn02_enable_intr __P ((u_int slotno,
207 int (*handler) __P((intr_arg_t sc)),
208 intr_arg_t sc, int onoff));
208#endif /*def DS5000_200*/
209#endif /*DS5000_200*/
209
210#ifdef DS5000_100
211void kmin_enable_intr __P ((u_int slotno, int (*handler) (intr_arg_t sc),
212 intr_arg_t sc, int onoff));
213#endif /*DS5000_100*/
214
215#ifdef DS5000_25
216void xine_enable_intr __P ((u_int slotno, int (*handler) (intr_arg_t sc),
217 intr_arg_t sc, int onoff));
218#endif /*DS5000_25*/
219
220#ifdef DS5000_240
221void kn03_enable_intr __P ((u_int slotno, int (*handler) (intr_arg_t sc),
222 intr_arg_t sc, int onoff));
223#endif /*DS5000_240*/
224
210
211#ifdef DS5000_100
212void kmin_enable_intr __P ((u_int slotno, int (*handler) (intr_arg_t sc),
213 intr_arg_t sc, int onoff));
214#endif /*DS5000_100*/
215
216#ifdef DS5000_25
217void xine_enable_intr __P ((u_int slotno, int (*handler) (intr_arg_t sc),
218 intr_arg_t sc, int onoff));
219#endif /*DS5000_25*/
220
221#ifdef DS5000_240
222void kn03_enable_intr __P ((u_int slotno, int (*handler) (intr_arg_t sc),
223 intr_arg_t sc, int onoff));
224#endif /*DS5000_240*/
225
226#if defined(DS5000_200) || defined(DS5000_25) || defined(DS5000_100) || \
227 defined(DS5000_240)
225volatile u_int *Mach_reset_addr;
228volatile u_int *Mach_reset_addr;
226#endif /* DS5000 */
229#endif /* DS5000_200 || DS5000_25 || DS5000_100 || DS5000_240 */
227
228
229/*
230 * safepri is a safe priority for sleep to set for a spin-wait
231 * during autoconfiguration or after a panic.
232 */
233int safepri = PSL_LOWIPL;
234

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445 Mach_splclock = Mach_spl3;
446 Mach_splstatclock = Mach_spl3;
447 Mach_clock_addr = (volatile struct chiptime *)
448 MACH_PHYS_TO_UNCACHED(KN01_SYS_CLOCK);
449 strcpy(cpu_model, "5100");
450 break;
451#endif /* DS5100 */
452
230
231
232/*
233 * safepri is a safe priority for sleep to set for a spin-wait
234 * during autoconfiguration or after a panic.
235 */
236int safepri = PSL_LOWIPL;
237

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448 Mach_splclock = Mach_spl3;
449 Mach_splstatclock = Mach_spl3;
450 Mach_clock_addr = (volatile struct chiptime *)
451 MACH_PHYS_TO_UNCACHED(KN01_SYS_CLOCK);
452 strcpy(cpu_model, "5100");
453 break;
454#endif /* DS5100 */
455
453#ifdef DS5000
456#ifdef DS5000_200
454 case DS_3MAX: /* DS5000/200 3max */
455 {
456 volatile int *csr_addr =
457 (volatile int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR);
458
459 Mach_reset_addr =
460 (unsigned *)MACH_PHYS_TO_UNCACHED(KN02_SYS_ERRADR);
461 /* clear any memory errors from new-config probes */

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477 Mach_splclock = Mach_spl1;
478 Mach_splstatclock = Mach_spl1;
479 Mach_clock_addr = (volatile struct chiptime *)
480 MACH_PHYS_TO_UNCACHED(KN02_SYS_CLOCK);
481
482 }
483 strcpy(cpu_model, "5000/200");
484 break;
457 case DS_3MAX: /* DS5000/200 3max */
458 {
459 volatile int *csr_addr =
460 (volatile int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR);
461
462 Mach_reset_addr =
463 (unsigned *)MACH_PHYS_TO_UNCACHED(KN02_SYS_ERRADR);
464 /* clear any memory errors from new-config probes */

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480 Mach_splclock = Mach_spl1;
481 Mach_splstatclock = Mach_spl1;
482 Mach_clock_addr = (volatile struct chiptime *)
483 MACH_PHYS_TO_UNCACHED(KN02_SYS_CLOCK);
484
485 }
486 strcpy(cpu_model, "5000/200");
487 break;
488#endif /* DS5000_200 */
485
486#ifdef DS5000_100
487 case DS_3MIN: /* DS5000/1xx 3min */
488 tc_max_slot = KMIN_TC_MAX;
489 tc_min_slot = KMIN_TC_MIN;
490 tc_slot_phys_base[0] = KMIN_PHYS_TC_0_START;
491 tc_slot_phys_base[1] = KMIN_PHYS_TC_1_START;
492 tc_slot_phys_base[2] = KMIN_PHYS_TC_2_START;

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520
521 /* clear any memory errors from probes */
522 Mach_reset_addr =
523 (u_int*)MACH_PHYS_TO_UNCACHED(KMIN_REG_TIMEOUT);
524 (*Mach_reset_addr) = 0;
525
526 strcpy(cpu_model, "5000/1xx");
527 break;
489
490#ifdef DS5000_100
491 case DS_3MIN: /* DS5000/1xx 3min */
492 tc_max_slot = KMIN_TC_MAX;
493 tc_min_slot = KMIN_TC_MIN;
494 tc_slot_phys_base[0] = KMIN_PHYS_TC_0_START;
495 tc_slot_phys_base[1] = KMIN_PHYS_TC_1_START;
496 tc_slot_phys_base[2] = KMIN_PHYS_TC_2_START;

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524
525 /* clear any memory errors from probes */
526 Mach_reset_addr =
527 (u_int*)MACH_PHYS_TO_UNCACHED(KMIN_REG_TIMEOUT);
528 (*Mach_reset_addr) = 0;
529
530 strcpy(cpu_model, "5000/1xx");
531 break;
528
529#endif /* ds5000_100 */
530
531#ifdef DS5000_25
532 case DS_MAXINE: /* DS5000/xx maxine */
533 tc_max_slot = XINE_TC_MAX;
534 tc_min_slot = XINE_TC_MIN;
535 tc_slot_phys_base[0] = XINE_PHYS_TC_0_START;
536 tc_slot_phys_base[1] = XINE_PHYS_TC_1_START;

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598 /* XXX hard-reset LANCE */
599 *(u_int *)IOASIC_REG_CSR(ioasic_base) |= 0x100;
600
601 /* clear any memory errors from probes */
602 *Mach_reset_addr = 0;
603 strcpy(cpu_model, "5000/240");
604 break;
605#endif /* DS5000_240 */
532#endif /* ds5000_100 */
533
534#ifdef DS5000_25
535 case DS_MAXINE: /* DS5000/xx maxine */
536 tc_max_slot = XINE_TC_MAX;
537 tc_min_slot = XINE_TC_MIN;
538 tc_slot_phys_base[0] = XINE_PHYS_TC_0_START;
539 tc_slot_phys_base[1] = XINE_PHYS_TC_1_START;

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601 /* XXX hard-reset LANCE */
602 *(u_int *)IOASIC_REG_CSR(ioasic_base) |= 0x100;
603
604 /* clear any memory errors from probes */
605 *Mach_reset_addr = 0;
606 strcpy(cpu_model, "5000/240");
607 break;
608#endif /* DS5000_240 */
606#endif /* DS5000 */
607
608 default:
609 printf("kernel not configured for systype 0x%x\n", i);
610 boot(RB_HALT | RB_NOSYNC);
611 }
612
613 /*
614 * Find out how much memory is available.

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1323}
1324
1325int
1326initcpu()
1327{
1328 register volatile struct chiptime *c;
1329 int i;
1330
609
610 default:
611 printf("kernel not configured for systype 0x%x\n", i);
612 boot(RB_HALT | RB_NOSYNC);
613 }
614
615 /*
616 * Find out how much memory is available.

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1325}
1326
1327int
1328initcpu()
1329{
1330 register volatile struct chiptime *c;
1331 int i;
1332
1331#if defined(DS_5000) || defined(DS5000_25) || defined(DS5000_100) || \
1332 defined(DS_5000_240)
1333#if defined(DS5000_200) || defined(DS5000_25) || defined(DS5000_100) || \
1334 defined(DS5000_240)
1333 /* Reset after bus errors during probe */
1334 if (Mach_reset_addr) {
1335 *Mach_reset_addr = 0;
1336 wbflush();
1337 }
1338#endif
1339
1340 /* clear any pending interrupts */

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1456 } else {
1457 tc_slot_info[slotno].intr = 0;
1458 tc_slot_info[slotno].sc = 0;
1459 }
1460}
1461#endif /* DS3100 */
1462
1463
1335 /* Reset after bus errors during probe */
1336 if (Mach_reset_addr) {
1337 *Mach_reset_addr = 0;
1338 wbflush();
1339 }
1340#endif
1341
1342 /* clear any pending interrupts */

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1458 } else {
1459 tc_slot_info[slotno].intr = 0;
1460 tc_slot_info[slotno].sc = 0;
1461 }
1462}
1463#endif /* DS3100 */
1464
1465
1464#ifdef DS5000
1466#ifdef DS5000_200
1465
1466/*
1467 * Enable/Disable interrupts for a TURBOchannel slot on the 3MAX.
1468 */
1469void
1470kn02_enable_intr(slotno, handler, sc, on)
1471 register u_int slotno;
1472 int (*handler) __P((void* softc));

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1499 s = Mach_spl0();
1500 csr = *p_csr & ~(KN02_CSR_WRESERVED | 0xFF);
1501 if (on)
1502 *p_csr = csr | slotno;
1503 else
1504 *p_csr = csr & ~slotno;
1505 splx(s);
1506}
1467
1468/*
1469 * Enable/Disable interrupts for a TURBOchannel slot on the 3MAX.
1470 */
1471void
1472kn02_enable_intr(slotno, handler, sc, on)
1473 register u_int slotno;
1474 int (*handler) __P((void* softc));

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1501 s = Mach_spl0();
1502 csr = *p_csr & ~(KN02_CSR_WRESERVED | 0xFF);
1503 if (on)
1504 *p_csr = csr | slotno;
1505 else
1506 *p_csr = csr & ~slotno;
1507 splx(s);
1508}
1509#endif /*DS5000_200*/
1507
1510
1511#ifdef DS5000_100
1508/*
1509 * Object:
1510 * kmin_enable_intr EXPORTED function
1511 *
1512 * Enable/Disable interrupts from a TURBOchannel slot.
1513 *
1514 * We pretend we actually have 8 slots even if we really have
1515 * only 4: TCslots 0-2 maps to slots 0-2, TCslot3 maps to

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1603 /* it's a baseboard device going via the ASIC */
1604 kmin_tc3_imask &= ~mask;
1605 }
1606 /* ... and clear the handler */
1607 tc_slot_info[slotno].intr = 0;
1608 tc_slot_info[slotno].sc = 0;
1609 }
1610}
1512/*
1513 * Object:
1514 * kmin_enable_intr EXPORTED function
1515 *
1516 * Enable/Disable interrupts from a TURBOchannel slot.
1517 *
1518 * We pretend we actually have 8 slots even if we really have
1519 * only 4: TCslots 0-2 maps to slots 0-2, TCslot3 maps to

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1607 /* it's a baseboard device going via the ASIC */
1608 kmin_tc3_imask &= ~mask;
1609 }
1610 /* ... and clear the handler */
1611 tc_slot_info[slotno].intr = 0;
1612 tc_slot_info[slotno].sc = 0;
1613 }
1614}
1615#endif /*DS5000_100*/
1611
1616
1617
1618#ifdef DS5000_25
1612/*
1613 * Object:
1614 * xine_enable_intr EXPORTED function
1615 *
1616 * Enable/Disable interrupts from a TURBOchannel slot.
1617 *
1618 * We pretend we actually have 11 slots even if we really have
1619 * only 3: TCslots 0-1 maps to slots 0-1, TCslot 2 is used for

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1669 tc_slot_info[slotno].sc = sc;
1670 } else {
1671 xine_tc3_imask &= ~mask;
1672 tc_slot_info[slotno].intr = 0;
1673 tc_slot_info[slotno].sc = 0;
1674 }
1675 *(u_int *)IOASIC_REG_IMSK(ioasic_base) = xine_tc3_imask;
1676}
1619/*
1620 * Object:
1621 * xine_enable_intr EXPORTED function
1622 *
1623 * Enable/Disable interrupts from a TURBOchannel slot.
1624 *
1625 * We pretend we actually have 11 slots even if we really have
1626 * only 3: TCslots 0-1 maps to slots 0-1, TCslot 2 is used for

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1676 tc_slot_info[slotno].sc = sc;
1677 } else {
1678 xine_tc3_imask &= ~mask;
1679 tc_slot_info[slotno].intr = 0;
1680 tc_slot_info[slotno].sc = 0;
1681 }
1682 *(u_int *)IOASIC_REG_IMSK(ioasic_base) = xine_tc3_imask;
1683}
1684#endif /*DS5000_25*/
1677
1678#ifdef DS5000_240
1679void
1680kn03_tc_reset()
1681{
1682/*
1683 * Reset interrupts, clear any errors from newconf probes
1684 */

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1773 /* These are common between 3min and maxine */
1774 decoder = (volatile u_int *)IOASIC_REG_LANCE_DECODE(ioasic_base);
1775 *decoder = KMIN_LANCE_CONFIG;
1776
1777 /* set the SCSI DMA configuration map */
1778 decoder = (volatile u_int *) IOASIC_REG_SCSI_DECODE(ioasic_base);
1779 (*decoder) = 0x00000000e;
1780}
1685
1686#ifdef DS5000_240
1687void
1688kn03_tc_reset()
1689{
1690/*
1691 * Reset interrupts, clear any errors from newconf probes
1692 */

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1781 /* These are common between 3min and maxine */
1782 decoder = (volatile u_int *)IOASIC_REG_LANCE_DECODE(ioasic_base);
1783 *decoder = KMIN_LANCE_CONFIG;
1784
1785 /* set the SCSI DMA configuration map */
1786 decoder = (volatile u_int *) IOASIC_REG_SCSI_DECODE(ioasic_base);
1787 (*decoder) = 0x00000000e;
1788}
1781#endif /* DS5000 */