| tegra_var.h (1.14) | tegra_var.h (1.15) |
|---|---|
| 1/* $NetBSD: tegra_var.h,v 1.14 2015/05/10 23:50:21 jmcneill Exp $ */ | 1/* $NetBSD: tegra_var.h,v 1.15 2015/05/13 11:06:13 jmcneill Exp $ */ |
| 2 3/*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: --- 57 unchanged lines hidden (view full) --- 67#define CHIP_ID_TEGRA114 0x35 68#define CHIP_ID_TEGRA124 0x40 69#define CHIP_ID_TEGRA132 0x13 70 71u_int tegra_chip_id(void); 72const char *tegra_chip_name(void); 73void tegra_bootstrap(void); 74void tegra_dma_bootstrap(psize_t); | 2 3/*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: --- 57 unchanged lines hidden (view full) --- 67#define CHIP_ID_TEGRA114 0x35 68#define CHIP_ID_TEGRA124 0x40 69#define CHIP_ID_TEGRA132 0x13 70 71u_int tegra_chip_id(void); 72const char *tegra_chip_name(void); 73void tegra_bootstrap(void); 74void tegra_dma_bootstrap(psize_t); |
| 75void tegra_cpuinit(void); |
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| 75 76u_int tegra_car_osc_rate(void); 77u_int tegra_car_pllc_rate(void); 78u_int tegra_car_plle_rate(void); 79u_int tegra_car_pllx_rate(void); | 76 77u_int tegra_car_osc_rate(void); 78u_int tegra_car_pllc_rate(void); 79u_int tegra_car_plle_rate(void); 80u_int tegra_car_pllx_rate(void); |
| 81void tegra_car_pllx_set_rate(u_int, u_int, u_int); |
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| 80u_int tegra_car_pllu_rate(void); 81u_int tegra_car_pllp0_rate(void); 82u_int tegra_car_uart_rate(u_int); 83u_int tegra_car_periph_sdmmc_rate(u_int); 84int tegra_car_periph_sdmmc_set_div(u_int, u_int); 85int tegra_car_periph_usb_enable(u_int); 86void tegra_car_periph_hda_enable(void); 87void tegra_car_periph_sata_enable(void); --- 28 unchanged lines hidden (view full) --- 116bool tegra_mpio_pinmux_get_io_reset(u_int); 117bool tegra_mpio_pinmux_get_rcv_sel(u_int); 118 119void tegra_pmc_reset(void); 120void tegra_pmc_power(u_int, bool); 121 122psize_t tegra_mc_memsize(void); 123 | 82u_int tegra_car_pllu_rate(void); 83u_int tegra_car_pllp0_rate(void); 84u_int tegra_car_uart_rate(u_int); 85u_int tegra_car_periph_sdmmc_rate(u_int); 86int tegra_car_periph_sdmmc_set_div(u_int, u_int); 87int tegra_car_periph_usb_enable(u_int); 88void tegra_car_periph_hda_enable(void); 89void tegra_car_periph_sata_enable(void); --- 28 unchanged lines hidden (view full) --- 118bool tegra_mpio_pinmux_get_io_reset(u_int); 119bool tegra_mpio_pinmux_get_rcv_sel(u_int); 120 121void tegra_pmc_reset(void); 122void tegra_pmc_power(u_int, bool); 123 124psize_t tegra_mc_memsize(void); 125 |
| 126#define TEGRA_CPUFREQ_MAX 16 127struct tegra_cpufreq_func { 128 u_int (*set_rate)(u_int); 129 u_int (*get_rate)(void); 130 size_t (*get_available)(u_int *, size_t); 131}; 132void tegra_cpufreq_register(const struct tegra_cpufreq_func *); 133void tegra_cpufreq_init(void); 134 |
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| 124#if defined(SOC_TEGRA124) | 135#if defined(SOC_TEGRA124) |
| 136void tegra124_cpuinit(void); |
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| 125void tegra124_mpinit(void); 126#endif 127 128static void inline 129tegra_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh, 130 bus_size_t o, uint32_t set_mask, uint32_t clr_mask) 131{ 132 const uint32_t old = bus_space_read_4(bst, bsh, o); 133 const uint32_t new = set_mask | (old & ~clr_mask); 134 if (old != new) { 135 bus_space_write_4(bst, bsh, o, new); 136 } 137} 138 139#endif /* _ARM_TEGRA_VAR_H */ | 137void tegra124_mpinit(void); 138#endif 139 140static void inline 141tegra_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh, 142 bus_size_t o, uint32_t set_mask, uint32_t clr_mask) 143{ 144 const uint32_t old = bus_space_read_4(bst, bsh, o); 145 const uint32_t new = set_mask | (old & ~clr_mask); 146 if (old != new) { 147 bus_space_write_4(bst, bsh, o, new); 148 } 149} 150 151#endif /* _ARM_TEGRA_VAR_H */ |