1/* $NetBSD: tegra_var.h,v 1.14 2015/05/10 23:50:21 jmcneill Exp $ */
| 1/* $NetBSD: tegra_var.h,v 1.15 2015/05/13 11:06:13 jmcneill Exp $ */
|
2
3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef _ARM_TEGRA_VAR_H
30#define _ARM_TEGRA_VAR_H
31
32#include <sys/types.h>
33#include <sys/bus.h>
34#include <sys/gpio.h>
35
36#include "opt_tegra.h"
37
38struct tegra_locators {
39 const char *loc_name;
40 bus_addr_t loc_offset;
41 bus_size_t loc_size;
42 int loc_port;
43 int loc_intr;
44#define TEGRAIO_INTR_DEFAULT 0
45};
46
47struct tegraio_attach_args {
48 struct tegra_locators tio_loc;
49 bus_space_tag_t tio_bst;
50 bus_space_tag_t tio_a4x_bst;
51 bus_space_handle_t tio_bsh;
52 bus_dma_tag_t tio_dmat;
53 bus_dma_tag_t tio_coherent_dmat;
54};
55
56extern struct bus_space armv7_generic_bs_tag;
57extern struct bus_space armv7_generic_a4x_bs_tag;
58extern bus_space_handle_t tegra_host1x_bsh;
59extern bus_space_handle_t tegra_ppsb_bsh;
60extern bus_space_handle_t tegra_apb_bsh;
61extern bus_space_handle_t tegra_ahb_a2_bsh;
62extern struct arm32_bus_dma_tag tegra_dma_tag;
63extern struct arm32_bus_dma_tag tegra_coherent_dma_tag;
64
65#define CHIP_ID_TEGRA20 0x20
66#define CHIP_ID_TEGRA30 0x30
67#define CHIP_ID_TEGRA114 0x35
68#define CHIP_ID_TEGRA124 0x40
69#define CHIP_ID_TEGRA132 0x13
70
71u_int tegra_chip_id(void);
72const char *tegra_chip_name(void);
73void tegra_bootstrap(void);
74void tegra_dma_bootstrap(psize_t);
| 2
3/*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef _ARM_TEGRA_VAR_H
30#define _ARM_TEGRA_VAR_H
31
32#include <sys/types.h>
33#include <sys/bus.h>
34#include <sys/gpio.h>
35
36#include "opt_tegra.h"
37
38struct tegra_locators {
39 const char *loc_name;
40 bus_addr_t loc_offset;
41 bus_size_t loc_size;
42 int loc_port;
43 int loc_intr;
44#define TEGRAIO_INTR_DEFAULT 0
45};
46
47struct tegraio_attach_args {
48 struct tegra_locators tio_loc;
49 bus_space_tag_t tio_bst;
50 bus_space_tag_t tio_a4x_bst;
51 bus_space_handle_t tio_bsh;
52 bus_dma_tag_t tio_dmat;
53 bus_dma_tag_t tio_coherent_dmat;
54};
55
56extern struct bus_space armv7_generic_bs_tag;
57extern struct bus_space armv7_generic_a4x_bs_tag;
58extern bus_space_handle_t tegra_host1x_bsh;
59extern bus_space_handle_t tegra_ppsb_bsh;
60extern bus_space_handle_t tegra_apb_bsh;
61extern bus_space_handle_t tegra_ahb_a2_bsh;
62extern struct arm32_bus_dma_tag tegra_dma_tag;
63extern struct arm32_bus_dma_tag tegra_coherent_dma_tag;
64
65#define CHIP_ID_TEGRA20 0x20
66#define CHIP_ID_TEGRA30 0x30
67#define CHIP_ID_TEGRA114 0x35
68#define CHIP_ID_TEGRA124 0x40
69#define CHIP_ID_TEGRA132 0x13
70
71u_int tegra_chip_id(void);
72const char *tegra_chip_name(void);
73void tegra_bootstrap(void);
74void tegra_dma_bootstrap(psize_t);
|
| 75void tegra_cpuinit(void);
|
75
76u_int tegra_car_osc_rate(void);
77u_int tegra_car_pllc_rate(void);
78u_int tegra_car_plle_rate(void);
79u_int tegra_car_pllx_rate(void);
| 76
77u_int tegra_car_osc_rate(void);
78u_int tegra_car_pllc_rate(void);
79u_int tegra_car_plle_rate(void);
80u_int tegra_car_pllx_rate(void);
|
| 81void tegra_car_pllx_set_rate(u_int, u_int, u_int);
|
80u_int tegra_car_pllu_rate(void);
81u_int tegra_car_pllp0_rate(void);
82u_int tegra_car_uart_rate(u_int);
83u_int tegra_car_periph_sdmmc_rate(u_int);
84int tegra_car_periph_sdmmc_set_div(u_int, u_int);
85int tegra_car_periph_usb_enable(u_int);
86void tegra_car_periph_hda_enable(void);
87void tegra_car_periph_sata_enable(void);
88int tegra_car_periph_i2c_enable(u_int, u_int);
89void tegra_car_utmip_init(void);
90void tegra_car_utmip_enable(u_int);
91
92struct tegra_gpio_pin;
93struct tegra_gpio_pin *tegra_gpio_acquire(const char *, u_int);
94void tegra_gpio_release(struct tegra_gpio_pin *);
95int tegra_gpio_read(struct tegra_gpio_pin *);
96void tegra_gpio_write(struct tegra_gpio_pin *, int);
97
98struct tegra_mpio_padctlgrp {
99 int preemp;
100 int hsm;
101 int schmt;
102 int drv_type;
103 int drvdn;
104 int drvup;
105 int slwr;
106 int slwf;
107};
108void tegra_mpio_padctlgrp_read(u_int, struct tegra_mpio_padctlgrp *);
109void tegra_mpio_padctlgrp_write(u_int, const struct tegra_mpio_padctlgrp *);
110
111void tegra_mpio_pinmux_set_config(u_int, int, const char *);
112void tegra_mpio_pinmux_set_io_reset(u_int, bool);
113void tegra_mpio_pinmux_set_rcv_sel(u_int, bool);
114void tegra_mpio_pinmux_get_config(u_int, int *, const char **);
115const char *tegra_mpio_pinmux_get_pm(u_int);
116bool tegra_mpio_pinmux_get_io_reset(u_int);
117bool tegra_mpio_pinmux_get_rcv_sel(u_int);
118
119void tegra_pmc_reset(void);
120void tegra_pmc_power(u_int, bool);
121
122psize_t tegra_mc_memsize(void);
123
| 82u_int tegra_car_pllu_rate(void);
83u_int tegra_car_pllp0_rate(void);
84u_int tegra_car_uart_rate(u_int);
85u_int tegra_car_periph_sdmmc_rate(u_int);
86int tegra_car_periph_sdmmc_set_div(u_int, u_int);
87int tegra_car_periph_usb_enable(u_int);
88void tegra_car_periph_hda_enable(void);
89void tegra_car_periph_sata_enable(void);
90int tegra_car_periph_i2c_enable(u_int, u_int);
91void tegra_car_utmip_init(void);
92void tegra_car_utmip_enable(u_int);
93
94struct tegra_gpio_pin;
95struct tegra_gpio_pin *tegra_gpio_acquire(const char *, u_int);
96void tegra_gpio_release(struct tegra_gpio_pin *);
97int tegra_gpio_read(struct tegra_gpio_pin *);
98void tegra_gpio_write(struct tegra_gpio_pin *, int);
99
100struct tegra_mpio_padctlgrp {
101 int preemp;
102 int hsm;
103 int schmt;
104 int drv_type;
105 int drvdn;
106 int drvup;
107 int slwr;
108 int slwf;
109};
110void tegra_mpio_padctlgrp_read(u_int, struct tegra_mpio_padctlgrp *);
111void tegra_mpio_padctlgrp_write(u_int, const struct tegra_mpio_padctlgrp *);
112
113void tegra_mpio_pinmux_set_config(u_int, int, const char *);
114void tegra_mpio_pinmux_set_io_reset(u_int, bool);
115void tegra_mpio_pinmux_set_rcv_sel(u_int, bool);
116void tegra_mpio_pinmux_get_config(u_int, int *, const char **);
117const char *tegra_mpio_pinmux_get_pm(u_int);
118bool tegra_mpio_pinmux_get_io_reset(u_int);
119bool tegra_mpio_pinmux_get_rcv_sel(u_int);
120
121void tegra_pmc_reset(void);
122void tegra_pmc_power(u_int, bool);
123
124psize_t tegra_mc_memsize(void);
125
|
| 126#define TEGRA_CPUFREQ_MAX 16
127struct tegra_cpufreq_func {
128 u_int (*set_rate)(u_int);
129 u_int (*get_rate)(void);
130 size_t (*get_available)(u_int *, size_t);
131};
132void tegra_cpufreq_register(const struct tegra_cpufreq_func *);
133void tegra_cpufreq_init(void);
134
|
124#if defined(SOC_TEGRA124)
| 135#if defined(SOC_TEGRA124)
|
| 136void tegra124_cpuinit(void);
|
125void tegra124_mpinit(void);
126#endif
127
128static void inline
129tegra_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh,
130 bus_size_t o, uint32_t set_mask, uint32_t clr_mask)
131{
132 const uint32_t old = bus_space_read_4(bst, bsh, o);
133 const uint32_t new = set_mask | (old & ~clr_mask);
134 if (old != new) {
135 bus_space_write_4(bst, bsh, o, new);
136 }
137}
138
139#endif /* _ARM_TEGRA_VAR_H */
| 137void tegra124_mpinit(void);
138#endif
139
140static void inline
141tegra_reg_set_clear(bus_space_tag_t bst, bus_space_handle_t bsh,
142 bus_size_t o, uint32_t set_mask, uint32_t clr_mask)
143{
144 const uint32_t old = bus_space_read_4(bst, bsh, o);
145 const uint32_t new = set_mask | (old & ~clr_mask);
146 if (old != new) {
147 bus_space_write_4(bst, bsh, o, new);
148 }
149}
150
151#endif /* _ARM_TEGRA_VAR_H */
|