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ncrreg.h (6132) ncrreg.h (7232)
1/**************************************************************************
2**
1/**************************************************************************
2**
3** $Id: ncrreg.h,v 1.1 1994/10/12 02:21:56 se Exp $
3** $Id: ncrreg.h,v 1.2 1995/02/02 13:12:16 davidg Exp $
4**
5** Device driver for the NCR 53C810 PCI-SCSI-Controller.
6**
7** 386bsd / FreeBSD / NetBSD
8**
9**-------------------------------------------------------------------------
10**
11** Written for 386bsd and FreeBSD by
4**
5** Device driver for the NCR 53C810 PCI-SCSI-Controller.
6**
7** 386bsd / FreeBSD / NetBSD
8**
9**-------------------------------------------------------------------------
10**
11** Written for 386bsd and FreeBSD by
12** wolf@dentaro.gun.de Wolfgang Stanglmeier
12** wolf@cologne.de Wolfgang Stanglmeier
13** se@mi.Uni-Koeln.de Stefan Esser
14**
15** Ported to NetBSD by
16** mycroft@gnu.ai.mit.edu
17**
18**-------------------------------------------------------------------------
19**
20** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved.

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42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43**
44***************************************************************************
45*/
46
47#ifndef __NCR_REG_H__
48#define __NCR_REG_H__
49
13** se@mi.Uni-Koeln.de Stefan Esser
14**
15** Ported to NetBSD by
16** mycroft@gnu.ai.mit.edu
17**
18**-------------------------------------------------------------------------
19**
20** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved.

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42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43**
44***************************************************************************
45*/
46
47#ifndef __NCR_REG_H__
48#define __NCR_REG_H__
49
50
51/*-----------------------------------------------------------------
52**
53** The ncr 53c810 register structure.
54**
55**-----------------------------------------------------------------
56*/
57
58struct ncr_reg {

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91 #define CATN 0x08 /* r/w: SCSI-ATN */
92 #define CMSG 0x04 /* r/w: SCSI-MSG */
93 #define CC_D 0x02 /* r/w: SCSI-C_D */
94 #define CI_O 0x01 /* r/w: SCSI-I_O */
95
96/*0a*/ u_char nc_ssid;
97
98/*0b*/ u_char nc_sbcl;
50/*-----------------------------------------------------------------
51**
52** The ncr 53c810 register structure.
53**
54**-----------------------------------------------------------------
55*/
56
57struct ncr_reg {

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90 #define CATN 0x08 /* r/w: SCSI-ATN */
91 #define CMSG 0x04 /* r/w: SCSI-MSG */
92 #define CC_D 0x02 /* r/w: SCSI-C_D */
93 #define CI_O 0x01 /* r/w: SCSI-I_O */
94
95/*0a*/ u_char nc_ssid;
96
97/*0b*/ u_char nc_sbcl;
99
98
100/*0c*/ u_char nc_dstat;
101 #define DFE 0x80 /* sta: dma fifo empty */
102 #define MDPE 0x40 /* int: master data parity error */
103 #define BF 0x20 /* int: script: bus fault */
104 #define ABRT 0x10 /* int: script: command aborted */
105 #define SSI 0x08 /* int: script: single step */
106 #define SIR 0x04 /* int: script: interrupt instruct. */
107 #define IID 0x01 /* int: script: illegal instruct. */

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146
147/*1a*/ u_char nc_ctest2;
148 #define CSIGP 0x40
149
150/*1b*/ u_char nc_ctest3;
151 #define CLF 0x04 /* clear scsi fifo */
152
153/*1c*/ u_long nc_temp; /* ### Temporary stack */
99/*0c*/ u_char nc_dstat;
100 #define DFE 0x80 /* sta: dma fifo empty */
101 #define MDPE 0x40 /* int: master data parity error */
102 #define BF 0x20 /* int: script: bus fault */
103 #define ABRT 0x10 /* int: script: command aborted */
104 #define SSI 0x08 /* int: script: single step */
105 #define SIR 0x04 /* int: script: interrupt instruct. */
106 #define IID 0x01 /* int: script: illegal instruct. */

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145
146/*1a*/ u_char nc_ctest2;
147 #define CSIGP 0x40
148
149/*1b*/ u_char nc_ctest3;
150 #define CLF 0x04 /* clear scsi fifo */
151
152/*1c*/ u_long nc_temp; /* ### Temporary stack */
154
153
155/*20*/ u_char nc_dfifo;
156/*21*/ u_char nc_ctest4;
157/*22*/ u_char nc_ctest5;
158/*23*/ u_char nc_ctest6;
159
160/*24*/ u_long nc_dbc; /* ### Byte count and command */
161/*28*/ u_long nc_dnad; /* ### Next command register */
162/*2c*/ u_long nc_dsp; /* --> Script Pointer */

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202
203/*4e*/ u_char nc_stest2;
204 #define ROF 0x40 /* reset scsi offset (after gross error!) */
205 #define EXT 0x02 /* extended filtering */
206
207/*4f*/ u_char nc_stest3;
208 #define TE 0x80 /* c: tolerAnt enable */
209 #define CSF 0x02 /* c: clear scsi fifo */
154/*20*/ u_char nc_dfifo;
155/*21*/ u_char nc_ctest4;
156/*22*/ u_char nc_ctest5;
157/*23*/ u_char nc_ctest6;
158
159/*24*/ u_long nc_dbc; /* ### Byte count and command */
160/*28*/ u_long nc_dnad; /* ### Next command register */
161/*2c*/ u_long nc_dsp; /* --> Script Pointer */

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201
202/*4e*/ u_char nc_stest2;
203 #define ROF 0x40 /* reset scsi offset (after gross error!) */
204 #define EXT 0x02 /* extended filtering */
205
206/*4f*/ u_char nc_stest3;
207 #define TE 0x80 /* c: tolerAnt enable */
208 #define CSF 0x02 /* c: clear scsi fifo */
210
209
211/*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */
212/*52*/ u_short nc_52_;
213/*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */
214/*56*/ u_short nc_56_;
215/*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */
216/*5a*/ u_short nc_5a_;
217/*5c*/ u_char nc_scr0; /* Working register B */
218/*5d*/ u_char nc_scr1; /* */
219/*5e*/ u_char nc_scr2; /* */
220/*5f*/ u_char nc_scr3; /* */
221/*60*/
222};
210/*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */
211/*52*/ u_short nc_52_;
212/*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */
213/*56*/ u_short nc_56_;
214/*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */
215/*5a*/ u_short nc_5a_;
216/*5c*/ u_char nc_scr0; /* Working register B */
217/*5d*/ u_char nc_scr1; /* */
218/*5e*/ u_char nc_scr2; /* */
219/*5f*/ u_char nc_scr3; /* */
220/*60*/
221};
223
222
224/*-----------------------------------------------------------
225**
226** Utility macros for the script.
227**
228**-----------------------------------------------------------
229*/
230
231#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))

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274#define SCR_MOVE_ABS(l) ((0x08000000 ^ (TARGET_MODE << 1ul)) | (l))
275#define SCR_MOVE_IND(l) ((0x28000000 ^ (TARGET_MODE << 1ul)) | (l))
276#define SCR_MOVE_TBL (0x18000000 ^ (TARGET_MODE << 1ul))
277
278struct scr_tblmove {
279 u_long size;
280 u_long addr;
281};
223/*-----------------------------------------------------------
224**
225** Utility macros for the script.
226**
227**-----------------------------------------------------------
228*/
229
230#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))

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273#define SCR_MOVE_ABS(l) ((0x08000000 ^ (TARGET_MODE << 1ul)) | (l))
274#define SCR_MOVE_IND(l) ((0x28000000 ^ (TARGET_MODE << 1ul)) | (l))
275#define SCR_MOVE_TBL (0x18000000 ^ (TARGET_MODE << 1ul))
276
277struct scr_tblmove {
278 u_long size;
279 u_long addr;
280};
282
281
283/*-----------------------------------------------------------
284**
285** Selection
286**
287**-----------------------------------------------------------
288**
289** SEL_ABS | SCR_ID (0..7) [ | REL_JMP]
290** <<alternate_address>>

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322** WAIT_RESEL
323** <<alternate_address>>
324**
325**-----------------------------------------------------------
326*/
327
328#define SCR_WAIT_DISC 0x48000000
329#define SCR_WAIT_RESEL 0x50000000
282/*-----------------------------------------------------------
283**
284** Selection
285**
286**-----------------------------------------------------------
287**
288** SEL_ABS | SCR_ID (0..7) [ | REL_JMP]
289** <<alternate_address>>

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321** WAIT_RESEL
322** <<alternate_address>>
323**
324**-----------------------------------------------------------
325*/
326
327#define SCR_WAIT_DISC 0x48000000
328#define SCR_WAIT_RESEL 0x50000000
330
329
331/*-----------------------------------------------------------
332**
333** Bit Set / Reset
334**
335**-----------------------------------------------------------
336**
337** SET (flags {|.. })
338**

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361** COPY (bytecount)
362** << source_address >>
363** << destination_address >>
364**
365**-----------------------------------------------------------
366*/
367
368#define SCR_COPY(n) (0xc0000000 | (n))
330/*-----------------------------------------------------------
331**
332** Bit Set / Reset
333**
334**-----------------------------------------------------------
335**
336** SET (flags {|.. })
337**

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360** COPY (bytecount)
361** << source_address >>
362** << destination_address >>
363**
364**-----------------------------------------------------------
365*/
366
367#define SCR_COPY(n) (0xc0000000 | (n))
369
368
370/*-----------------------------------------------------------
371**
372** Register move and binary operations
373**
374**-----------------------------------------------------------
375**
376** SFBR_REG (reg, op, data) reg = SFBR op data
377** << 0 >>

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400#define SCR_LOAD 0x00000000
401#define SCR_SHL 0x01000000
402#define SCR_OR 0x02000000
403#define SCR_XOR 0x03000000
404#define SCR_AND 0x04000000
405#define SCR_SHR 0x05000000
406#define SCR_ADD 0x06000000
407#define SCR_ADDC 0x07000000
369/*-----------------------------------------------------------
370**
371** Register move and binary operations
372**
373**-----------------------------------------------------------
374**
375** SFBR_REG (reg, op, data) reg = SFBR op data
376** << 0 >>

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399#define SCR_LOAD 0x00000000
400#define SCR_SHL 0x01000000
401#define SCR_OR 0x02000000
402#define SCR_XOR 0x03000000
403#define SCR_AND 0x04000000
404#define SCR_SHR 0x05000000
405#define SCR_ADD 0x06000000
406#define SCR_ADDC 0x07000000
408
407
409/*-----------------------------------------------------------
410**
411** FROM_REG (reg) reg = SFBR
412** << 0 >>
413**
414** TO_REG (reg) SFBR = reg
415** << 0 >>
416**

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429#define SCR_TO_REG(reg) \
430 SCR_SFBR_REG(reg,SCR_OR,0)
431
432#define SCR_LOAD_REG(reg,data) \
433 SCR_REG_REG(reg,SCR_LOAD,data)
434
435#define SCR_LOAD_SFBR(data) \
436 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
408/*-----------------------------------------------------------
409**
410** FROM_REG (reg) reg = SFBR
411** << 0 >>
412**
413** TO_REG (reg) SFBR = reg
414** << 0 >>
415**

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428#define SCR_TO_REG(reg) \
429 SCR_SFBR_REG(reg,SCR_OR,0)
430
431#define SCR_LOAD_REG(reg,data) \
432 SCR_REG_REG(reg,SCR_LOAD,data)
433
434#define SCR_LOAD_SFBR(data) \
435 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
437
436
438/*-----------------------------------------------------------
439**
440** Waiting for Disconnect or Reselect
441**
442**-----------------------------------------------------------
443**
444** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
445** <<address>>

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484
485#define WHEN(phase) (0x00030000 | (phase))
486#define IF(phase) (0x00020000 | (phase))
487
488#define DATA(D) (0x00040000 | ((D) & 0xff))
489#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
490
491#define CARRYSET (0x00200000)
437/*-----------------------------------------------------------
438**
439** Waiting for Disconnect or Reselect
440**
441**-----------------------------------------------------------
442**
443** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
444** <<address>>

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483
484#define WHEN(phase) (0x00030000 | (phase))
485#define IF(phase) (0x00020000 | (phase))
486
487#define DATA(D) (0x00040000 | ((D) & 0xff))
488#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
489
490#define CARRYSET (0x00200000)
492
491
493/*-----------------------------------------------------------
494**
495** SCSI constants.
496**
497**-----------------------------------------------------------
498*/
499
500/*

--- 48 unchanged lines hidden --- 		492/*-----------------------------------------------------------
493**
494** SCSI constants.
495**
496**-----------------------------------------------------------
497*/
498
499/*

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