1/**************************************************************************
2**
| 1/**************************************************************************
2**
|
3** $Id: ncrreg.h,v 1.1 1994/10/12 02:21:56 se Exp $
| 3** $Id: ncrreg.h,v 1.2 1995/02/02 13:12:16 davidg Exp $
|
4**
5** Device driver for the NCR 53C810 PCI-SCSI-Controller.
6**
7** 386bsd / FreeBSD / NetBSD
8**
9**-------------------------------------------------------------------------
10**
11** Written for 386bsd and FreeBSD by
| 4**
5** Device driver for the NCR 53C810 PCI-SCSI-Controller.
6**
7** 386bsd / FreeBSD / NetBSD
8**
9**-------------------------------------------------------------------------
10**
11** Written for 386bsd and FreeBSD by
|
12** wolf@dentaro.gun.de Wolfgang Stanglmeier
| 12** wolf@cologne.de Wolfgang Stanglmeier
|
13** se@mi.Uni-Koeln.de Stefan Esser
14**
15** Ported to NetBSD by
16** mycroft@gnu.ai.mit.edu
17**
18**-------------------------------------------------------------------------
19**
20** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved.
21**
22** Redistribution and use in source and binary forms, with or without
23** modification, are permitted provided that the following conditions
24** are met:
25** 1. Redistributions of source code must retain the above copyright
26** notice, this list of conditions and the following disclaimer.
27** 2. Redistributions in binary form must reproduce the above copyright
28** notice, this list of conditions and the following disclaimer in the
29** documentation and/or other materials provided with the distribution.
30** 3. The name of the author may not be used to endorse or promote products
31** derived from this software without specific prior written permission.
32**
33** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
34** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
35** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
36** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
37** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
38** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
40** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43**
44***************************************************************************
45*/
46
47#ifndef __NCR_REG_H__
48#define __NCR_REG_H__
49
| 13** se@mi.Uni-Koeln.de Stefan Esser
14**
15** Ported to NetBSD by
16** mycroft@gnu.ai.mit.edu
17**
18**-------------------------------------------------------------------------
19**
20** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved.
21**
22** Redistribution and use in source and binary forms, with or without
23** modification, are permitted provided that the following conditions
24** are met:
25** 1. Redistributions of source code must retain the above copyright
26** notice, this list of conditions and the following disclaimer.
27** 2. Redistributions in binary form must reproduce the above copyright
28** notice, this list of conditions and the following disclaimer in the
29** documentation and/or other materials provided with the distribution.
30** 3. The name of the author may not be used to endorse or promote products
31** derived from this software without specific prior written permission.
32**
33** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
34** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
35** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
36** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
37** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
38** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
40** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43**
44***************************************************************************
45*/
46
47#ifndef __NCR_REG_H__
48#define __NCR_REG_H__
49
|
50
| |
51/*-----------------------------------------------------------------
52**
53** The ncr 53c810 register structure.
54**
55**-----------------------------------------------------------------
56*/
57
58struct ncr_reg {
59/*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */
60
61/*01*/ u_char nc_scntl1; /* no reset */
62 #define ISCON 0x10 /* connected to scsi */
63 #define CRST 0x08 /* force reset */
64
65/*02*/ u_char nc_scntl2; /* no disconnect expected */
66 #define SDU 0x80 /* cmd: disconnect will raise error */
67 #define CHM 0x40 /* sta: chained mode */
68 #define WSS 0x08 /* sta: wide scsi send [W]*/
69 #define WSR 0x01 /* sta: wide scsi received [W]*/
70
71/*03*/ u_char nc_scntl3; /* cnf system clock dependent */
72 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
73
74/*04*/ u_char nc_scid; /* cnf host adapter scsi address */
75 #define RRE 0x40 /* r/w:e enable response to resel. */
76 #define SRE 0x20 /* r/w:e enable response to select */
77
78/*05*/ u_char nc_sxfer; /* ### Sync speed and count */
79
80/*06*/ u_char nc_sdid; /* ### Destination-ID */
81
82/*07*/ u_char nc_gpreg; /* ??? IO-Pins */
83
84/*08*/ u_char nc_sfbr; /* ### First byte in phase */
85
86/*09*/ u_char nc_socl;
87 #define CREQ 0x80 /* r/w: SCSI-REQ */
88 #define CACK 0x40 /* r/w: SCSI-ACK */
89 #define CBSY 0x20 /* r/w: SCSI-BSY */
90 #define CSEL 0x10 /* r/w: SCSI-SEL */
91 #define CATN 0x08 /* r/w: SCSI-ATN */
92 #define CMSG 0x04 /* r/w: SCSI-MSG */
93 #define CC_D 0x02 /* r/w: SCSI-C_D */
94 #define CI_O 0x01 /* r/w: SCSI-I_O */
95
96/*0a*/ u_char nc_ssid;
97
98/*0b*/ u_char nc_sbcl;
| 50/*-----------------------------------------------------------------
51**
52** The ncr 53c810 register structure.
53**
54**-----------------------------------------------------------------
55*/
56
57struct ncr_reg {
58/*00*/ u_char nc_scntl0; /* full arb., ena parity, par->ATN */
59
60/*01*/ u_char nc_scntl1; /* no reset */
61 #define ISCON 0x10 /* connected to scsi */
62 #define CRST 0x08 /* force reset */
63
64/*02*/ u_char nc_scntl2; /* no disconnect expected */
65 #define SDU 0x80 /* cmd: disconnect will raise error */
66 #define CHM 0x40 /* sta: chained mode */
67 #define WSS 0x08 /* sta: wide scsi send [W]*/
68 #define WSR 0x01 /* sta: wide scsi received [W]*/
69
70/*03*/ u_char nc_scntl3; /* cnf system clock dependent */
71 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
72
73/*04*/ u_char nc_scid; /* cnf host adapter scsi address */
74 #define RRE 0x40 /* r/w:e enable response to resel. */
75 #define SRE 0x20 /* r/w:e enable response to select */
76
77/*05*/ u_char nc_sxfer; /* ### Sync speed and count */
78
79/*06*/ u_char nc_sdid; /* ### Destination-ID */
80
81/*07*/ u_char nc_gpreg; /* ??? IO-Pins */
82
83/*08*/ u_char nc_sfbr; /* ### First byte in phase */
84
85/*09*/ u_char nc_socl;
86 #define CREQ 0x80 /* r/w: SCSI-REQ */
87 #define CACK 0x40 /* r/w: SCSI-ACK */
88 #define CBSY 0x20 /* r/w: SCSI-BSY */
89 #define CSEL 0x10 /* r/w: SCSI-SEL */
90 #define CATN 0x08 /* r/w: SCSI-ATN */
91 #define CMSG 0x04 /* r/w: SCSI-MSG */
92 #define CC_D 0x02 /* r/w: SCSI-C_D */
93 #define CI_O 0x01 /* r/w: SCSI-I_O */
94
95/*0a*/ u_char nc_ssid;
96
97/*0b*/ u_char nc_sbcl;
|
99
| 98
|
100/*0c*/ u_char nc_dstat;
101 #define DFE 0x80 /* sta: dma fifo empty */
102 #define MDPE 0x40 /* int: master data parity error */
103 #define BF 0x20 /* int: script: bus fault */
104 #define ABRT 0x10 /* int: script: command aborted */
105 #define SSI 0x08 /* int: script: single step */
106 #define SIR 0x04 /* int: script: interrupt instruct. */
107 #define IID 0x01 /* int: script: illegal instruct. */
108
109/*0d*/ u_char nc_sstat0;
110 #define ILF 0x80 /* sta: data in SIDL register lsb */
111 #define ORF 0x40 /* sta: data in SODR register lsb */
112 #define OLF 0x20 /* sta: data in SODL register lsb */
113 #define AIP 0x10 /* sta: arbitration in progress */
114 #define LOA 0x08 /* sta: arbitration lost */
115 #define WOA 0x04 /* sta: arbitration won */
116 #define IRST 0x02 /* sta: scsi reset signal */
117 #define SDP 0x01 /* sta: scsi parity signal */
118
119/*0e*/ u_char nc_sstat1;
120 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
121
122/*0f*/ u_char nc_sstat2;
123 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
124 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
125 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
126 #define LDSC 0x02 /* sta: disconnect & reconnect */
127
128/*10*/ u_long nc_dsa; /* --> Base page */
129
130/*14*/ u_char nc_istat; /* --> Main Command and status */
131 #define CABRT 0x80 /* cmd: abort current operation */
132 #define SRST 0x40 /* mod: reset chip */
133 #define SIGP 0x20 /* r/w: message from host to ncr */
134 #define SEM 0x10 /* r/w: message between host + ncr */
135 #define CON 0x08 /* sta: connected to scsi */
136 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
137 #define SIP 0x02 /* sta: scsi-interrupt */
138 #define DIP 0x01 /* sta: host/script interrupt */
139
140/*15*/ u_char nc_15_;
141/*16*/ u_char nc_16_;
142/*17*/ u_char nc_17_;
143
144/*18*/ u_char nc_ctest0;
145/*19*/ u_char nc_ctest1;
146
147/*1a*/ u_char nc_ctest2;
148 #define CSIGP 0x40
149
150/*1b*/ u_char nc_ctest3;
151 #define CLF 0x04 /* clear scsi fifo */
152
153/*1c*/ u_long nc_temp; /* ### Temporary stack */
| 99/*0c*/ u_char nc_dstat;
100 #define DFE 0x80 /* sta: dma fifo empty */
101 #define MDPE 0x40 /* int: master data parity error */
102 #define BF 0x20 /* int: script: bus fault */
103 #define ABRT 0x10 /* int: script: command aborted */
104 #define SSI 0x08 /* int: script: single step */
105 #define SIR 0x04 /* int: script: interrupt instruct. */
106 #define IID 0x01 /* int: script: illegal instruct. */
107
108/*0d*/ u_char nc_sstat0;
109 #define ILF 0x80 /* sta: data in SIDL register lsb */
110 #define ORF 0x40 /* sta: data in SODR register lsb */
111 #define OLF 0x20 /* sta: data in SODL register lsb */
112 #define AIP 0x10 /* sta: arbitration in progress */
113 #define LOA 0x08 /* sta: arbitration lost */
114 #define WOA 0x04 /* sta: arbitration won */
115 #define IRST 0x02 /* sta: scsi reset signal */
116 #define SDP 0x01 /* sta: scsi parity signal */
117
118/*0e*/ u_char nc_sstat1;
119 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
120
121/*0f*/ u_char nc_sstat2;
122 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
123 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
124 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
125 #define LDSC 0x02 /* sta: disconnect & reconnect */
126
127/*10*/ u_long nc_dsa; /* --> Base page */
128
129/*14*/ u_char nc_istat; /* --> Main Command and status */
130 #define CABRT 0x80 /* cmd: abort current operation */
131 #define SRST 0x40 /* mod: reset chip */
132 #define SIGP 0x20 /* r/w: message from host to ncr */
133 #define SEM 0x10 /* r/w: message between host + ncr */
134 #define CON 0x08 /* sta: connected to scsi */
135 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
136 #define SIP 0x02 /* sta: scsi-interrupt */
137 #define DIP 0x01 /* sta: host/script interrupt */
138
139/*15*/ u_char nc_15_;
140/*16*/ u_char nc_16_;
141/*17*/ u_char nc_17_;
142
143/*18*/ u_char nc_ctest0;
144/*19*/ u_char nc_ctest1;
145
146/*1a*/ u_char nc_ctest2;
147 #define CSIGP 0x40
148
149/*1b*/ u_char nc_ctest3;
150 #define CLF 0x04 /* clear scsi fifo */
151
152/*1c*/ u_long nc_temp; /* ### Temporary stack */
|
154
| 153
|
155/*20*/ u_char nc_dfifo;
156/*21*/ u_char nc_ctest4;
157/*22*/ u_char nc_ctest5;
158/*23*/ u_char nc_ctest6;
159
160/*24*/ u_long nc_dbc; /* ### Byte count and command */
161/*28*/ u_long nc_dnad; /* ### Next command register */
162/*2c*/ u_long nc_dsp; /* --> Script Pointer */
163/*30*/ u_long nc_dsps; /* --> Script pointer save/opcode#2 */
164/*34*/ u_long nc_scratcha; /* ??? Temporary register a */
165
166/*38*/ u_char nc_dmode;
167/*39*/ u_char nc_dien;
168/*3a*/ u_char nc_dwt;
169
170/*3b*/ u_char nc_dcntl; /* --> Script execution control */
171 #define SSM 0x10 /* mod: single step mode */
172 #define STD 0x04 /* cmd: start dma mode */
173 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
174
175/*3c*/ u_long nc_adder;
176
177/*40*/ u_short nc_sien; /* -->: interrupt enable */
178/*42*/ u_short nc_sist; /* <--: interrupt status */
179 #define STO 0x0400/* sta: timeout (select) */
180 #define GEN 0x0200/* sta: timeout (general) */
181 #define HTH 0x0100/* sta: timeout (handshake) */
182 #define MA 0x80 /* sta: phase mismatch */
183 #define CMP 0x40 /* sta: arbitration complete */
184 #define SEL 0x20 /* sta: selected by another device */
185 #define RSL 0x10 /* sta: reselected by another device*/
186 #define SGE 0x08 /* sta: gross error (over/underflow)*/
187 #define UDC 0x04 /* sta: unexpected disconnect */
188 #define RST 0x02 /* sta: scsi bus reset detected */
189 #define PAR 0x01 /* sta: scsi parity error */
190
191/*44*/ u_char nc_slpar;
192/*45*/ u_char nc_swide;
193/*46*/ u_char nc_macntl;
194/*47*/ u_char nc_gpcntl;
195/*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/
196/*49*/ u_char nc_stime1; /* cmd: timeout user defined */
197/*4a*/ u_short nc_respid; /* sta: Reselect-IDs */
198
199/*4c*/ u_char nc_stest0;
200
201/*4d*/ u_char nc_stest1;
202
203/*4e*/ u_char nc_stest2;
204 #define ROF 0x40 /* reset scsi offset (after gross error!) */
205 #define EXT 0x02 /* extended filtering */
206
207/*4f*/ u_char nc_stest3;
208 #define TE 0x80 /* c: tolerAnt enable */
209 #define CSF 0x02 /* c: clear scsi fifo */
| 154/*20*/ u_char nc_dfifo;
155/*21*/ u_char nc_ctest4;
156/*22*/ u_char nc_ctest5;
157/*23*/ u_char nc_ctest6;
158
159/*24*/ u_long nc_dbc; /* ### Byte count and command */
160/*28*/ u_long nc_dnad; /* ### Next command register */
161/*2c*/ u_long nc_dsp; /* --> Script Pointer */
162/*30*/ u_long nc_dsps; /* --> Script pointer save/opcode#2 */
163/*34*/ u_long nc_scratcha; /* ??? Temporary register a */
164
165/*38*/ u_char nc_dmode;
166/*39*/ u_char nc_dien;
167/*3a*/ u_char nc_dwt;
168
169/*3b*/ u_char nc_dcntl; /* --> Script execution control */
170 #define SSM 0x10 /* mod: single step mode */
171 #define STD 0x04 /* cmd: start dma mode */
172 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
173
174/*3c*/ u_long nc_adder;
175
176/*40*/ u_short nc_sien; /* -->: interrupt enable */
177/*42*/ u_short nc_sist; /* <--: interrupt status */
178 #define STO 0x0400/* sta: timeout (select) */
179 #define GEN 0x0200/* sta: timeout (general) */
180 #define HTH 0x0100/* sta: timeout (handshake) */
181 #define MA 0x80 /* sta: phase mismatch */
182 #define CMP 0x40 /* sta: arbitration complete */
183 #define SEL 0x20 /* sta: selected by another device */
184 #define RSL 0x10 /* sta: reselected by another device*/
185 #define SGE 0x08 /* sta: gross error (over/underflow)*/
186 #define UDC 0x04 /* sta: unexpected disconnect */
187 #define RST 0x02 /* sta: scsi bus reset detected */
188 #define PAR 0x01 /* sta: scsi parity error */
189
190/*44*/ u_char nc_slpar;
191/*45*/ u_char nc_swide;
192/*46*/ u_char nc_macntl;
193/*47*/ u_char nc_gpcntl;
194/*48*/ u_char nc_stime0; /* cmd: timeout for select&handshake*/
195/*49*/ u_char nc_stime1; /* cmd: timeout user defined */
196/*4a*/ u_short nc_respid; /* sta: Reselect-IDs */
197
198/*4c*/ u_char nc_stest0;
199
200/*4d*/ u_char nc_stest1;
201
202/*4e*/ u_char nc_stest2;
203 #define ROF 0x40 /* reset scsi offset (after gross error!) */
204 #define EXT 0x02 /* extended filtering */
205
206/*4f*/ u_char nc_stest3;
207 #define TE 0x80 /* c: tolerAnt enable */
208 #define CSF 0x02 /* c: clear scsi fifo */
|
210
| 209
|
211/*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */
212/*52*/ u_short nc_52_;
213/*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */
214/*56*/ u_short nc_56_;
215/*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */
216/*5a*/ u_short nc_5a_;
217/*5c*/ u_char nc_scr0; /* Working register B */
218/*5d*/ u_char nc_scr1; /* */
219/*5e*/ u_char nc_scr2; /* */
220/*5f*/ u_char nc_scr3; /* */
221/*60*/
222};
| 210/*50*/ u_short nc_sidl; /* Lowlevel: latched from scsi data */
211/*52*/ u_short nc_52_;
212/*54*/ u_short nc_sodl; /* Lowlevel: data out to scsi data */
213/*56*/ u_short nc_56_;
214/*58*/ u_short nc_sbdl; /* Lowlevel: data from scsi data */
215/*5a*/ u_short nc_5a_;
216/*5c*/ u_char nc_scr0; /* Working register B */
217/*5d*/ u_char nc_scr1; /* */
218/*5e*/ u_char nc_scr2; /* */
219/*5f*/ u_char nc_scr3; /* */
220/*60*/
221};
|
223
| 222
|
224/*-----------------------------------------------------------
225**
226** Utility macros for the script.
227**
228**-----------------------------------------------------------
229*/
230
231#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
232#define REG(r) REGJ (nc_, r)
233
234#ifndef TARGET_MODE
235#define TARGET_MODE 0
236#endif
237
238typedef unsigned long ncrcmd;
239
240/*-----------------------------------------------------------
241**
242** SCSI phases
243**
244**-----------------------------------------------------------
245*/
246
247#define SCR_DATA_OUT 0x00000000
248#define SCR_DATA_IN 0x01000000
249#define SCR_COMMAND 0x02000000
250#define SCR_STATUS 0x03000000
251#define SCR_ILG_OUT 0x04000000
252#define SCR_ILG_IN 0x05000000
253#define SCR_MSG_OUT 0x06000000
254#define SCR_MSG_IN 0x07000000
255
256/*-----------------------------------------------------------
257**
258** Data transfer via SCSI.
259**
260**-----------------------------------------------------------
261**
262** MOVE_ABS (LEN)
263** <<start address>>
264**
265** MOVE_IND (LEN)
266** <<dnad_offset>>
267**
268** MOVE_TBL
269** <<dnad_offset>>
270**
271**-----------------------------------------------------------
272*/
273
274#define SCR_MOVE_ABS(l) ((0x08000000 ^ (TARGET_MODE << 1ul)) | (l))
275#define SCR_MOVE_IND(l) ((0x28000000 ^ (TARGET_MODE << 1ul)) | (l))
276#define SCR_MOVE_TBL (0x18000000 ^ (TARGET_MODE << 1ul))
277
278struct scr_tblmove {
279 u_long size;
280 u_long addr;
281};
| 223/*-----------------------------------------------------------
224**
225** Utility macros for the script.
226**
227**-----------------------------------------------------------
228*/
229
230#define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
231#define REG(r) REGJ (nc_, r)
232
233#ifndef TARGET_MODE
234#define TARGET_MODE 0
235#endif
236
237typedef unsigned long ncrcmd;
238
239/*-----------------------------------------------------------
240**
241** SCSI phases
242**
243**-----------------------------------------------------------
244*/
245
246#define SCR_DATA_OUT 0x00000000
247#define SCR_DATA_IN 0x01000000
248#define SCR_COMMAND 0x02000000
249#define SCR_STATUS 0x03000000
250#define SCR_ILG_OUT 0x04000000
251#define SCR_ILG_IN 0x05000000
252#define SCR_MSG_OUT 0x06000000
253#define SCR_MSG_IN 0x07000000
254
255/*-----------------------------------------------------------
256**
257** Data transfer via SCSI.
258**
259**-----------------------------------------------------------
260**
261** MOVE_ABS (LEN)
262** <<start address>>
263**
264** MOVE_IND (LEN)
265** <<dnad_offset>>
266**
267** MOVE_TBL
268** <<dnad_offset>>
269**
270**-----------------------------------------------------------
271*/
272
273#define SCR_MOVE_ABS(l) ((0x08000000 ^ (TARGET_MODE << 1ul)) | (l))
274#define SCR_MOVE_IND(l) ((0x28000000 ^ (TARGET_MODE << 1ul)) | (l))
275#define SCR_MOVE_TBL (0x18000000 ^ (TARGET_MODE << 1ul))
276
277struct scr_tblmove {
278 u_long size;
279 u_long addr;
280};
|
282
| 281
|
283/*-----------------------------------------------------------
284**
285** Selection
286**
287**-----------------------------------------------------------
288**
289** SEL_ABS | SCR_ID (0..7) [ | REL_JMP]
290** <<alternate_address>>
291**
292** SEL_TBL | << dnad_offset>> [ | REL_JMP]
293** <<alternate_address>>
294**
295**-----------------------------------------------------------
296*/
297
298#define SCR_SEL_ABS 0x40000000
299#define SCR_SEL_ABS_ATN 0x41000000
300#define SCR_SEL_TBL 0x42000000
301#define SCR_SEL_TBL_ATN 0x43000000
302
303struct scr_tblsel {
304 u_char sel_0;
305 u_char sel_sxfer;
306 u_char sel_id;
307 u_char sel_scntl3;
308};
309
310#define SCR_JMP_REL 0x04000000
311#define SCR_ID(id) (((u_long)(id)) << 16)
312
313/*-----------------------------------------------------------
314**
315** Waiting for Disconnect or Reselect
316**
317**-----------------------------------------------------------
318**
319** WAIT_DISC
320** dummy: <<alternate_address>>
321**
322** WAIT_RESEL
323** <<alternate_address>>
324**
325**-----------------------------------------------------------
326*/
327
328#define SCR_WAIT_DISC 0x48000000
329#define SCR_WAIT_RESEL 0x50000000
| 282/*-----------------------------------------------------------
283**
284** Selection
285**
286**-----------------------------------------------------------
287**
288** SEL_ABS | SCR_ID (0..7) [ | REL_JMP]
289** <<alternate_address>>
290**
291** SEL_TBL | << dnad_offset>> [ | REL_JMP]
292** <<alternate_address>>
293**
294**-----------------------------------------------------------
295*/
296
297#define SCR_SEL_ABS 0x40000000
298#define SCR_SEL_ABS_ATN 0x41000000
299#define SCR_SEL_TBL 0x42000000
300#define SCR_SEL_TBL_ATN 0x43000000
301
302struct scr_tblsel {
303 u_char sel_0;
304 u_char sel_sxfer;
305 u_char sel_id;
306 u_char sel_scntl3;
307};
308
309#define SCR_JMP_REL 0x04000000
310#define SCR_ID(id) (((u_long)(id)) << 16)
311
312/*-----------------------------------------------------------
313**
314** Waiting for Disconnect or Reselect
315**
316**-----------------------------------------------------------
317**
318** WAIT_DISC
319** dummy: <<alternate_address>>
320**
321** WAIT_RESEL
322** <<alternate_address>>
323**
324**-----------------------------------------------------------
325*/
326
327#define SCR_WAIT_DISC 0x48000000
328#define SCR_WAIT_RESEL 0x50000000
|
330
| 329
|
331/*-----------------------------------------------------------
332**
333** Bit Set / Reset
334**
335**-----------------------------------------------------------
336**
337** SET (flags {|.. })
338**
339** CLR (flags {|.. })
340**
341**-----------------------------------------------------------
342*/
343
344#define SCR_SET(f) (0x58000000 | (f))
345#define SCR_CLR(f) (0x60000000 | (f))
346
347#define SCR_CARRY 0x00000400
348#define SCR_TRG 0x00000200
349#define SCR_ACK 0x00000040
350#define SCR_ATN 0x00000008
351
352
353
354
355/*-----------------------------------------------------------
356**
357** Memory to memory move
358**
359**-----------------------------------------------------------
360**
361** COPY (bytecount)
362** << source_address >>
363** << destination_address >>
364**
365**-----------------------------------------------------------
366*/
367
368#define SCR_COPY(n) (0xc0000000 | (n))
| 330/*-----------------------------------------------------------
331**
332** Bit Set / Reset
333**
334**-----------------------------------------------------------
335**
336** SET (flags {|.. })
337**
338** CLR (flags {|.. })
339**
340**-----------------------------------------------------------
341*/
342
343#define SCR_SET(f) (0x58000000 | (f))
344#define SCR_CLR(f) (0x60000000 | (f))
345
346#define SCR_CARRY 0x00000400
347#define SCR_TRG 0x00000200
348#define SCR_ACK 0x00000040
349#define SCR_ATN 0x00000008
350
351
352
353
354/*-----------------------------------------------------------
355**
356** Memory to memory move
357**
358**-----------------------------------------------------------
359**
360** COPY (bytecount)
361** << source_address >>
362** << destination_address >>
363**
364**-----------------------------------------------------------
365*/
366
367#define SCR_COPY(n) (0xc0000000 | (n))
|
369
| 368
|
370/*-----------------------------------------------------------
371**
372** Register move and binary operations
373**
374**-----------------------------------------------------------
375**
376** SFBR_REG (reg, op, data) reg = SFBR op data
377** << 0 >>
378**
379** REG_SFBR (reg, op, data) SFBR = reg op data
380** << 0 >>
381**
382** REG_REG (reg, op, data) reg = reg op data
383** << 0 >>
384**
385**-----------------------------------------------------------
386*/
387
388#define SCR_REG_OFS(ofs) ((ofs) << 16ul)
389
390#define SCR_SFBR_REG(reg,op,data) \
391 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))
392
393#define SCR_REG_SFBR(reg,op,data) \
394 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))
395
396#define SCR_REG_REG(reg,op,data) \
397 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))
398
399
400#define SCR_LOAD 0x00000000
401#define SCR_SHL 0x01000000
402#define SCR_OR 0x02000000
403#define SCR_XOR 0x03000000
404#define SCR_AND 0x04000000
405#define SCR_SHR 0x05000000
406#define SCR_ADD 0x06000000
407#define SCR_ADDC 0x07000000
| 369/*-----------------------------------------------------------
370**
371** Register move and binary operations
372**
373**-----------------------------------------------------------
374**
375** SFBR_REG (reg, op, data) reg = SFBR op data
376** << 0 >>
377**
378** REG_SFBR (reg, op, data) SFBR = reg op data
379** << 0 >>
380**
381** REG_REG (reg, op, data) reg = reg op data
382** << 0 >>
383**
384**-----------------------------------------------------------
385*/
386
387#define SCR_REG_OFS(ofs) ((ofs) << 16ul)
388
389#define SCR_SFBR_REG(reg,op,data) \
390 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))
391
392#define SCR_REG_SFBR(reg,op,data) \
393 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))
394
395#define SCR_REG_REG(reg,op,data) \
396 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | ((data)<<8ul))
397
398
399#define SCR_LOAD 0x00000000
400#define SCR_SHL 0x01000000
401#define SCR_OR 0x02000000
402#define SCR_XOR 0x03000000
403#define SCR_AND 0x04000000
404#define SCR_SHR 0x05000000
405#define SCR_ADD 0x06000000
406#define SCR_ADDC 0x07000000
|
408
| 407
|
409/*-----------------------------------------------------------
410**
411** FROM_REG (reg) reg = SFBR
412** << 0 >>
413**
414** TO_REG (reg) SFBR = reg
415** << 0 >>
416**
417** LOAD_REG (reg, data) reg = <data>
418** << 0 >>
419**
420** LOAD_SFBR(data) SFBR = <data>
421** << 0 >>
422**
423**-----------------------------------------------------------
424*/
425
426#define SCR_FROM_REG(reg) \
427 SCR_REG_SFBR(reg,SCR_OR,0)
428
429#define SCR_TO_REG(reg) \
430 SCR_SFBR_REG(reg,SCR_OR,0)
431
432#define SCR_LOAD_REG(reg,data) \
433 SCR_REG_REG(reg,SCR_LOAD,data)
434
435#define SCR_LOAD_SFBR(data) \
436 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
| 408/*-----------------------------------------------------------
409**
410** FROM_REG (reg) reg = SFBR
411** << 0 >>
412**
413** TO_REG (reg) SFBR = reg
414** << 0 >>
415**
416** LOAD_REG (reg, data) reg = <data>
417** << 0 >>
418**
419** LOAD_SFBR(data) SFBR = <data>
420** << 0 >>
421**
422**-----------------------------------------------------------
423*/
424
425#define SCR_FROM_REG(reg) \
426 SCR_REG_SFBR(reg,SCR_OR,0)
427
428#define SCR_TO_REG(reg) \
429 SCR_SFBR_REG(reg,SCR_OR,0)
430
431#define SCR_LOAD_REG(reg,data) \
432 SCR_REG_REG(reg,SCR_LOAD,data)
433
434#define SCR_LOAD_SFBR(data) \
435 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
|
437
| 436
|
438/*-----------------------------------------------------------
439**
440** Waiting for Disconnect or Reselect
441**
442**-----------------------------------------------------------
443**
444** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
445** <<address>>
446**
447** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
448** <<distance>>
449**
450** CALL [ | IFTRUE/IFFALSE ( ... ) ]
451** <<address>>
452**
453** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
454** <<distance>>
455**
456** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
457** <<dummy>>
458**
459** INT [ | IFTRUE/IFFALSE ( ... ) ]
460** <<ident>>
461**
462** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
463** <<ident>>
464**
465** Conditions:
466** WHEN (phase)
467** IF (phase)
468** CARRY
469** DATA (data, mask)
470**
471**-----------------------------------------------------------
472*/
473
474#define SCR_JUMP 0x80080000
475#define SCR_JUMPR 0x80880000
476#define SCR_CALL 0x88080000
477#define SCR_CALLR 0x88880000
478#define SCR_RETURN 0x90080000
479#define SCR_INT 0x98080000
480#define SCR_INT_FLY 0x98180000
481
482#define IFFALSE(arg) (0x00080000 | (arg))
483#define IFTRUE(arg) (0x00000000 | (arg))
484
485#define WHEN(phase) (0x00030000 | (phase))
486#define IF(phase) (0x00020000 | (phase))
487
488#define DATA(D) (0x00040000 | ((D) & 0xff))
489#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
490
491#define CARRYSET (0x00200000)
| 437/*-----------------------------------------------------------
438**
439** Waiting for Disconnect or Reselect
440**
441**-----------------------------------------------------------
442**
443** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
444** <<address>>
445**
446** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
447** <<distance>>
448**
449** CALL [ | IFTRUE/IFFALSE ( ... ) ]
450** <<address>>
451**
452** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
453** <<distance>>
454**
455** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
456** <<dummy>>
457**
458** INT [ | IFTRUE/IFFALSE ( ... ) ]
459** <<ident>>
460**
461** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
462** <<ident>>
463**
464** Conditions:
465** WHEN (phase)
466** IF (phase)
467** CARRY
468** DATA (data, mask)
469**
470**-----------------------------------------------------------
471*/
472
473#define SCR_JUMP 0x80080000
474#define SCR_JUMPR 0x80880000
475#define SCR_CALL 0x88080000
476#define SCR_CALLR 0x88880000
477#define SCR_RETURN 0x90080000
478#define SCR_INT 0x98080000
479#define SCR_INT_FLY 0x98180000
480
481#define IFFALSE(arg) (0x00080000 | (arg))
482#define IFTRUE(arg) (0x00000000 | (arg))
483
484#define WHEN(phase) (0x00030000 | (phase))
485#define IF(phase) (0x00020000 | (phase))
486
487#define DATA(D) (0x00040000 | ((D) & 0xff))
488#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
489
490#define CARRYSET (0x00200000)
|
492
| 491
|
493/*-----------------------------------------------------------
494**
495** SCSI constants.
496**
497**-----------------------------------------------------------
498*/
499
500/*
501** Messages
502*/
503
504#define M_COMPLETE (0x00)
505#define M_EXTENDED (0x01)
506#define M_SAVE_DP (0x02)
507#define M_RESTORE_DP (0x03)
508#define M_DISCONNECT (0x04)
509#define M_ID_ERROR (0x05)
510#define M_ABORT (0x06)
511#define M_REJECT (0x07)
512#define M_NOOP (0x08)
513#define M_PARITY (0x09)
514#define M_LCOMPLETE (0x0a)
515#define M_FCOMPLETE (0x0b)
516#define M_RESET (0x0c)
517#define M_ABORT_TAG (0x0d)
518#define M_CLEAR_QUEUE (0x0e)
519#define M_INIT_REC (0x0f)
520#define M_REL_REC (0x10)
521#define M_TERMINATE (0x11)
522#define M_SIMPLE_TAG (0x20)
523#define M_HEAD_TAG (0x21)
524#define M_ORDERED_TAG (0x22)
525#define M_IGN_RESIDUE (0x23)
526#define M_IDENTIFY (0x80)
527
528#define M_X_MODIFY_DP (0x00)
529#define M_X_SYNC_REQ (0x01)
530#define M_X_WIDE_REQ (0x03)
531
532/*
533** Status
534*/
535
536#define S_GOOD (0x00)
537#define S_CHECK_COND (0x02)
538#define S_COND_MET (0x04)
539#define S_BUSY (0x08)
540#define S_INT (0x10)
541#define S_INT_COND_MET (0x14)
542#define S_CONFLICT (0x18)
543#define S_TERMINATED (0x20)
544#define S_QUEUE_FULL (0x28)
545#define S_ILLEGAL (0xff)
546#define S_SENSE (0x80)
547
548#endif /*__NCR_REG_H__*/
| 492/*-----------------------------------------------------------
493**
494** SCSI constants.
495**
496**-----------------------------------------------------------
497*/
498
499/*
500** Messages
501*/
502
503#define M_COMPLETE (0x00)
504#define M_EXTENDED (0x01)
505#define M_SAVE_DP (0x02)
506#define M_RESTORE_DP (0x03)
507#define M_DISCONNECT (0x04)
508#define M_ID_ERROR (0x05)
509#define M_ABORT (0x06)
510#define M_REJECT (0x07)
511#define M_NOOP (0x08)
512#define M_PARITY (0x09)
513#define M_LCOMPLETE (0x0a)
514#define M_FCOMPLETE (0x0b)
515#define M_RESET (0x0c)
516#define M_ABORT_TAG (0x0d)
517#define M_CLEAR_QUEUE (0x0e)
518#define M_INIT_REC (0x0f)
519#define M_REL_REC (0x10)
520#define M_TERMINATE (0x11)
521#define M_SIMPLE_TAG (0x20)
522#define M_HEAD_TAG (0x21)
523#define M_ORDERED_TAG (0x22)
524#define M_IGN_RESIDUE (0x23)
525#define M_IDENTIFY (0x80)
526
527#define M_X_MODIFY_DP (0x00)
528#define M_X_SYNC_REQ (0x01)
529#define M_X_WIDE_REQ (0x03)
530
531/*
532** Status
533*/
534
535#define S_GOOD (0x00)
536#define S_CHECK_COND (0x02)
537#define S_COND_MET (0x04)
538#define S_BUSY (0x08)
539#define S_INT (0x10)
540#define S_INT_COND_MET (0x14)
541#define S_CONFLICT (0x18)
542#define S_TERMINATED (0x20)
543#define S_QUEUE_FULL (0x28)
544#define S_ILLEGAL (0xff)
545#define S_SENSE (0x80)
546
547#endif /*__NCR_REG_H__*/
|