86#include <sys/param.h>
87#include <sys/endian.h>
88#include <sys/systm.h>
89#include <sys/sockio.h>
90#include <sys/mbuf.h>
91#include <sys/malloc.h>
92#include <sys/kernel.h>
93#include <sys/socket.h>
94
95#include <net/if.h>
96#include <net/if_arp.h>
97#include <net/ethernet.h>
98#include <net/if_dl.h>
99#include <net/if_media.h>
100
101#include <net/bpf.h>
102
103#include <machine/bus_pio.h>
104#include <machine/bus_memio.h>
105#include <machine/bus.h>
106#include <machine/resource.h>
107#include <sys/bus.h>
108#include <sys/rman.h>
109
110#include <dev/mii/mii.h>
111#include <dev/mii/miivar.h>
112
113#include <dev/pci/pcireg.h>
114#include <dev/pci/pcivar.h>
115
116MODULE_DEPEND(rl, pci, 1, 1, 1);
117MODULE_DEPEND(rl, ether, 1, 1, 1);
118MODULE_DEPEND(rl, miibus, 1, 1, 1);
119
120/* "controller miibus0" required. See GENERIC if you get errors here. */
121#include "miibus_if.h"
122
123/*
124 * Default to using PIO access for this driver. On SMP systems,
125 * there appear to be problems with memory mapped mode: it looks like
126 * doing too many memory mapped access back to back in rapid succession
127 * can hang the bus. I'm inclined to blame this on crummy design/construction
128 * on the part of RealTek. Memory mapped mode does appear to work on
129 * uniprocessor systems though.
130 */
131#define RL_USEIOSPACE
132
133#include <pci/if_rlreg.h>
134
135/*
136 * Various supported device vendors/types and their names.
137 */
138static struct rl_type rl_devs[] = {
139 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
140 "RealTek 8129 10/100BaseTX" },
141 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
142 "RealTek 8139 10/100BaseTX" },
143 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
144 "RealTek 8139 10/100BaseTX CardBus" },
145 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
146 "RealTek 8100 10/100BaseTX" },
147 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
148 "Accton MPX 5030/5038 10/100BaseTX" },
149 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
150 "Delta Electronics 8139 10/100BaseTX" },
151 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
152 "Addtron Technolgy 8139 10/100BaseTX" },
153 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
154 "D-Link DFE-530TX+ 10/100BaseTX" },
155 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
156 "D-Link DFE-690TXD 10/100BaseTX" },
157 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
158 "Nortel Networks 10/100BaseTX" },
159 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
160 "Corega FEther CB-TXD" },
161 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
162 "Corega FEtherII CB-TXD" },
163 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
164 "Peppercon AG ROL-F" },
165 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
166 "Planex FNW-3800-TX" },
167 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
168 "Compaq HNE-300" },
169 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
170 "LevelOne FPC-0106TX" },
171 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
172 "Edimax EP-4103DL CardBus" },
173 { 0, 0, NULL }
174};
175
176static int rl_probe (device_t);
177static int rl_attach (device_t);
178static int rl_detach (device_t);
179
180static int rl_encap (struct rl_softc *, struct mbuf * );
181
182static void rl_rxeof (struct rl_softc *);
183static void rl_txeof (struct rl_softc *);
184static void rl_intr (void *);
185static void rl_tick (void *);
186static void rl_start (struct ifnet *);
187static int rl_ioctl (struct ifnet *, u_long, caddr_t);
188static void rl_init (void *);
189static void rl_stop (struct rl_softc *);
190static void rl_watchdog (struct ifnet *);
191static int rl_suspend (device_t);
192static int rl_resume (device_t);
193static void rl_shutdown (device_t);
194static int rl_ifmedia_upd (struct ifnet *);
195static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
196
197static void rl_eeprom_putbyte (struct rl_softc *, int);
198static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *);
199static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
200static void rl_mii_sync (struct rl_softc *);
201static void rl_mii_send (struct rl_softc *, u_int32_t, int);
202static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *);
203static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *);
204
205static int rl_miibus_readreg (device_t, int, int);
206static int rl_miibus_writereg (device_t, int, int, int);
207static void rl_miibus_statchg (device_t);
208
209static u_int32_t rl_mchash (caddr_t);
210static void rl_setmulti (struct rl_softc *);
211static void rl_reset (struct rl_softc *);
212static int rl_list_tx_init (struct rl_softc *);
213
214static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int);
215static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int);
216
217#ifdef RL_USEIOSPACE
218#define RL_RES SYS_RES_IOPORT
219#define RL_RID RL_PCI_LOIO
220#else
221#define RL_RES SYS_RES_MEMORY
222#define RL_RID RL_PCI_LOMEM
223#endif
224
225static device_method_t rl_methods[] = {
226 /* Device interface */
227 DEVMETHOD(device_probe, rl_probe),
228 DEVMETHOD(device_attach, rl_attach),
229 DEVMETHOD(device_detach, rl_detach),
230 DEVMETHOD(device_suspend, rl_suspend),
231 DEVMETHOD(device_resume, rl_resume),
232 DEVMETHOD(device_shutdown, rl_shutdown),
233
234 /* bus interface */
235 DEVMETHOD(bus_print_child, bus_generic_print_child),
236 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
237
238 /* MII interface */
239 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
240 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
241 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
242
243 { 0, 0 }
244};
245
246static driver_t rl_driver = {
247 "rl",
248 rl_methods,
249 sizeof(struct rl_softc)
250};
251
252static devclass_t rl_devclass;
253
254DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
255DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
256
257#define EE_SET(x) \
258 CSR_WRITE_1(sc, RL_EECMD, \
259 CSR_READ_1(sc, RL_EECMD) | x)
260
261#define EE_CLR(x) \
262 CSR_WRITE_1(sc, RL_EECMD, \
263 CSR_READ_1(sc, RL_EECMD) & ~x)
264
265static void
266rl_dma_map_rxbuf(arg, segs, nseg, error)
267 void *arg;
268 bus_dma_segment_t *segs;
269 int nseg, error;
270{
271 struct rl_softc *sc;
272
273 sc = arg;
274 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
275
276 return;
277}
278
279static void
280rl_dma_map_txbuf(arg, segs, nseg, error)
281 void *arg;
282 bus_dma_segment_t *segs;
283 int nseg, error;
284{
285 struct rl_softc *sc;
286
287 sc = arg;
288 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
289
290 return;
291}
292
293/*
294 * Send a read command and address to the EEPROM, check for ACK.
295 */
296static void
297rl_eeprom_putbyte(sc, addr)
298 struct rl_softc *sc;
299 int addr;
300{
301 register int d, i;
302
303 d = addr | sc->rl_eecmd_read;
304
305 /*
306 * Feed in each bit and strobe the clock.
307 */
308 for (i = 0x400; i; i >>= 1) {
309 if (d & i) {
310 EE_SET(RL_EE_DATAIN);
311 } else {
312 EE_CLR(RL_EE_DATAIN);
313 }
314 DELAY(100);
315 EE_SET(RL_EE_CLK);
316 DELAY(150);
317 EE_CLR(RL_EE_CLK);
318 DELAY(100);
319 }
320
321 return;
322}
323
324/*
325 * Read a word of data stored in the EEPROM at address 'addr.'
326 */
327static void
328rl_eeprom_getword(sc, addr, dest)
329 struct rl_softc *sc;
330 int addr;
331 u_int16_t *dest;
332{
333 register int i;
334 u_int16_t word = 0;
335
336 /* Enter EEPROM access mode. */
337 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
338
339 /*
340 * Send address of word we want to read.
341 */
342 rl_eeprom_putbyte(sc, addr);
343
344 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
345
346 /*
347 * Start reading bits from EEPROM.
348 */
349 for (i = 0x8000; i; i >>= 1) {
350 EE_SET(RL_EE_CLK);
351 DELAY(100);
352 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
353 word |= i;
354 EE_CLR(RL_EE_CLK);
355 DELAY(100);
356 }
357
358 /* Turn off EEPROM access mode. */
359 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
360
361 *dest = word;
362
363 return;
364}
365
366/*
367 * Read a sequence of words from the EEPROM.
368 */
369static void
370rl_read_eeprom(sc, dest, off, cnt, swap)
371 struct rl_softc *sc;
372 caddr_t dest;
373 int off;
374 int cnt;
375 int swap;
376{
377 int i;
378 u_int16_t word = 0, *ptr;
379
380 for (i = 0; i < cnt; i++) {
381 rl_eeprom_getword(sc, off + i, &word);
382 ptr = (u_int16_t *)(dest + (i * 2));
383 if (swap)
384 *ptr = ntohs(word);
385 else
386 *ptr = word;
387 }
388
389 return;
390}
391
392
393/*
394 * MII access routines are provided for the 8129, which
395 * doesn't have a built-in PHY. For the 8139, we fake things
396 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
397 * direct access PHY registers.
398 */
399#define MII_SET(x) \
400 CSR_WRITE_1(sc, RL_MII, \
401 CSR_READ_1(sc, RL_MII) | (x))
402
403#define MII_CLR(x) \
404 CSR_WRITE_1(sc, RL_MII, \
405 CSR_READ_1(sc, RL_MII) & ~(x))
406
407/*
408 * Sync the PHYs by setting data bit and strobing the clock 32 times.
409 */
410static void
411rl_mii_sync(sc)
412 struct rl_softc *sc;
413{
414 register int i;
415
416 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
417
418 for (i = 0; i < 32; i++) {
419 MII_SET(RL_MII_CLK);
420 DELAY(1);
421 MII_CLR(RL_MII_CLK);
422 DELAY(1);
423 }
424
425 return;
426}
427
428/*
429 * Clock a series of bits through the MII.
430 */
431static void
432rl_mii_send(sc, bits, cnt)
433 struct rl_softc *sc;
434 u_int32_t bits;
435 int cnt;
436{
437 int i;
438
439 MII_CLR(RL_MII_CLK);
440
441 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
442 if (bits & i) {
443 MII_SET(RL_MII_DATAOUT);
444 } else {
445 MII_CLR(RL_MII_DATAOUT);
446 }
447 DELAY(1);
448 MII_CLR(RL_MII_CLK);
449 DELAY(1);
450 MII_SET(RL_MII_CLK);
451 }
452}
453
454/*
455 * Read an PHY register through the MII.
456 */
457static int
458rl_mii_readreg(sc, frame)
459 struct rl_softc *sc;
460 struct rl_mii_frame *frame;
461
462{
463 int i, ack;
464
465 RL_LOCK(sc);
466
467 /*
468 * Set up frame for RX.
469 */
470 frame->mii_stdelim = RL_MII_STARTDELIM;
471 frame->mii_opcode = RL_MII_READOP;
472 frame->mii_turnaround = 0;
473 frame->mii_data = 0;
474
475 CSR_WRITE_2(sc, RL_MII, 0);
476
477 /*
478 * Turn on data xmit.
479 */
480 MII_SET(RL_MII_DIR);
481
482 rl_mii_sync(sc);
483
484 /*
485 * Send command/address info.
486 */
487 rl_mii_send(sc, frame->mii_stdelim, 2);
488 rl_mii_send(sc, frame->mii_opcode, 2);
489 rl_mii_send(sc, frame->mii_phyaddr, 5);
490 rl_mii_send(sc, frame->mii_regaddr, 5);
491
492 /* Idle bit */
493 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
494 DELAY(1);
495 MII_SET(RL_MII_CLK);
496 DELAY(1);
497
498 /* Turn off xmit. */
499 MII_CLR(RL_MII_DIR);
500
501 /* Check for ack */
502 MII_CLR(RL_MII_CLK);
503 DELAY(1);
504 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
505 MII_SET(RL_MII_CLK);
506 DELAY(1);
507
508 /*
509 * Now try reading data bits. If the ack failed, we still
510 * need to clock through 16 cycles to keep the PHY(s) in sync.
511 */
512 if (ack) {
513 for(i = 0; i < 16; i++) {
514 MII_CLR(RL_MII_CLK);
515 DELAY(1);
516 MII_SET(RL_MII_CLK);
517 DELAY(1);
518 }
519 goto fail;
520 }
521
522 for (i = 0x8000; i; i >>= 1) {
523 MII_CLR(RL_MII_CLK);
524 DELAY(1);
525 if (!ack) {
526 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
527 frame->mii_data |= i;
528 DELAY(1);
529 }
530 MII_SET(RL_MII_CLK);
531 DELAY(1);
532 }
533
534fail:
535
536 MII_CLR(RL_MII_CLK);
537 DELAY(1);
538 MII_SET(RL_MII_CLK);
539 DELAY(1);
540
541 RL_UNLOCK(sc);
542
543 if (ack)
544 return(1);
545 return(0);
546}
547
548/*
549 * Write to a PHY register through the MII.
550 */
551static int
552rl_mii_writereg(sc, frame)
553 struct rl_softc *sc;
554 struct rl_mii_frame *frame;
555
556{
557 RL_LOCK(sc);
558
559 /*
560 * Set up frame for TX.
561 */
562
563 frame->mii_stdelim = RL_MII_STARTDELIM;
564 frame->mii_opcode = RL_MII_WRITEOP;
565 frame->mii_turnaround = RL_MII_TURNAROUND;
566
567 /*
568 * Turn on data output.
569 */
570 MII_SET(RL_MII_DIR);
571
572 rl_mii_sync(sc);
573
574 rl_mii_send(sc, frame->mii_stdelim, 2);
575 rl_mii_send(sc, frame->mii_opcode, 2);
576 rl_mii_send(sc, frame->mii_phyaddr, 5);
577 rl_mii_send(sc, frame->mii_regaddr, 5);
578 rl_mii_send(sc, frame->mii_turnaround, 2);
579 rl_mii_send(sc, frame->mii_data, 16);
580
581 /* Idle bit. */
582 MII_SET(RL_MII_CLK);
583 DELAY(1);
584 MII_CLR(RL_MII_CLK);
585 DELAY(1);
586
587 /*
588 * Turn off xmit.
589 */
590 MII_CLR(RL_MII_DIR);
591
592 RL_UNLOCK(sc);
593
594 return(0);
595}
596
597static int
598rl_miibus_readreg(dev, phy, reg)
599 device_t dev;
600 int phy, reg;
601{
602 struct rl_softc *sc;
603 struct rl_mii_frame frame;
604 u_int16_t rval = 0;
605 u_int16_t rl8139_reg = 0;
606
607 sc = device_get_softc(dev);
608 RL_LOCK(sc);
609
610 if (sc->rl_type == RL_8139) {
611 /* Pretend the internal PHY is only at address 0 */
612 if (phy) {
613 RL_UNLOCK(sc);
614 return(0);
615 }
616 switch(reg) {
617 case MII_BMCR:
618 rl8139_reg = RL_BMCR;
619 break;
620 case MII_BMSR:
621 rl8139_reg = RL_BMSR;
622 break;
623 case MII_ANAR:
624 rl8139_reg = RL_ANAR;
625 break;
626 case MII_ANER:
627 rl8139_reg = RL_ANER;
628 break;
629 case MII_ANLPAR:
630 rl8139_reg = RL_LPAR;
631 break;
632 case MII_PHYIDR1:
633 case MII_PHYIDR2:
634 RL_UNLOCK(sc);
635 return(0);
636 /*
637 * Allow the rlphy driver to read the media status
638 * register. If we have a link partner which does not
639 * support NWAY, this is the register which will tell
640 * us the results of parallel detection.
641 */
642 case RL_MEDIASTAT:
643 rval = CSR_READ_1(sc, RL_MEDIASTAT);
644 RL_UNLOCK(sc);
645 return(rval);
646 default:
647 printf("rl%d: bad phy register\n", sc->rl_unit);
648 RL_UNLOCK(sc);
649 return(0);
650 }
651 rval = CSR_READ_2(sc, rl8139_reg);
652 RL_UNLOCK(sc);
653 return(rval);
654 }
655
656 bzero((char *)&frame, sizeof(frame));
657
658 frame.mii_phyaddr = phy;
659 frame.mii_regaddr = reg;
660 rl_mii_readreg(sc, &frame);
661 RL_UNLOCK(sc);
662
663 return(frame.mii_data);
664}
665
666static int
667rl_miibus_writereg(dev, phy, reg, data)
668 device_t dev;
669 int phy, reg, data;
670{
671 struct rl_softc *sc;
672 struct rl_mii_frame frame;
673 u_int16_t rl8139_reg = 0;
674
675 sc = device_get_softc(dev);
676 RL_LOCK(sc);
677
678 if (sc->rl_type == RL_8139) {
679 /* Pretend the internal PHY is only at address 0 */
680 if (phy) {
681 RL_UNLOCK(sc);
682 return(0);
683 }
684 switch(reg) {
685 case MII_BMCR:
686 rl8139_reg = RL_BMCR;
687 break;
688 case MII_BMSR:
689 rl8139_reg = RL_BMSR;
690 break;
691 case MII_ANAR:
692 rl8139_reg = RL_ANAR;
693 break;
694 case MII_ANER:
695 rl8139_reg = RL_ANER;
696 break;
697 case MII_ANLPAR:
698 rl8139_reg = RL_LPAR;
699 break;
700 case MII_PHYIDR1:
701 case MII_PHYIDR2:
702 RL_UNLOCK(sc);
703 return(0);
704 break;
705 default:
706 printf("rl%d: bad phy register\n", sc->rl_unit);
707 RL_UNLOCK(sc);
708 return(0);
709 }
710 CSR_WRITE_2(sc, rl8139_reg, data);
711 RL_UNLOCK(sc);
712 return(0);
713 }
714
715 bzero((char *)&frame, sizeof(frame));
716
717 frame.mii_phyaddr = phy;
718 frame.mii_regaddr = reg;
719 frame.mii_data = data;
720
721 rl_mii_writereg(sc, &frame);
722
723 RL_UNLOCK(sc);
724 return(0);
725}
726
727static void
728rl_miibus_statchg(dev)
729 device_t dev;
730{
731 return;
732}
733
734/*
735 * Calculate CRC of a multicast group address, return the upper 6 bits.
736 */
737static u_int32_t
738rl_mchash(addr)
739 caddr_t addr;
740{
741 u_int32_t crc, carry;
742 int idx, bit;
743 u_int8_t data;
744
745 /* Compute CRC for the address value. */
746 crc = 0xFFFFFFFF; /* initial value */
747
748 for (idx = 0; idx < 6; idx++) {
749 for (data = *addr++, bit = 0; bit < 8; bit++, data >>=1 ) {
750 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
751 crc <<= 1;
752 if (carry)
753 crc = (crc ^ 0x04c11db6) | carry;
754 }
755 }
756
757 /* return the filter bit position */
758 return(crc >> 26);
759}
760
761/*
762 * Program the 64-bit multicast hash filter.
763 */
764static void
765rl_setmulti(sc)
766 struct rl_softc *sc;
767{
768 struct ifnet *ifp;
769 int h = 0;
770 u_int32_t hashes[2] = { 0, 0 };
771 struct ifmultiaddr *ifma;
772 u_int32_t rxfilt;
773 int mcnt = 0;
774
775 ifp = &sc->arpcom.ac_if;
776
777 rxfilt = CSR_READ_4(sc, RL_RXCFG);
778
779 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
780 rxfilt |= RL_RXCFG_RX_MULTI;
781 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
782 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
783 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
784 return;
785 }
786
787 /* first, zot all the existing hash bits */
788 CSR_WRITE_4(sc, RL_MAR0, 0);
789 CSR_WRITE_4(sc, RL_MAR4, 0);
790
791 /* now program new ones */
792 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
793 if (ifma->ifma_addr->sa_family != AF_LINK)
794 continue;
795 h = rl_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
796 if (h < 32)
797 hashes[0] |= (1 << h);
798 else
799 hashes[1] |= (1 << (h - 32));
800 mcnt++;
801 }
802
803 if (mcnt)
804 rxfilt |= RL_RXCFG_RX_MULTI;
805 else
806 rxfilt &= ~RL_RXCFG_RX_MULTI;
807
808 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
809 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
810 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
811
812 return;
813}
814
815static void
816rl_reset(sc)
817 struct rl_softc *sc;
818{
819 register int i;
820
821 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
822
823 for (i = 0; i < RL_TIMEOUT; i++) {
824 DELAY(10);
825 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
826 break;
827 }
828 if (i == RL_TIMEOUT)
829 printf("rl%d: reset never completed!\n", sc->rl_unit);
830
831 return;
832}
833
834/*
835 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
836 * IDs against our list and return a device name if we find a match.
837 */
838static int
839rl_probe(dev)
840 device_t dev;
841{
842 struct rl_type *t;
843 struct rl_softc *sc;
844 int rid;
845 u_int32_t hwrev;
846
847 t = rl_devs;
848 sc = device_get_softc(dev);
849
850 while(t->rl_name != NULL) {
851 if ((pci_get_vendor(dev) == t->rl_vid) &&
852 (pci_get_device(dev) == t->rl_did)) {
853
854 /*
855 * Temporarily map the I/O space
856 * so we can read the chip ID register.
857 */
858 rid = RL_RID;
859 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
860 0, ~0, 1, RF_ACTIVE);
861 if (sc->rl_res == NULL) {
862 device_printf(dev,
863 "couldn't map ports/memory\n");
864 return(ENXIO);
865 }
866 sc->rl_btag = rman_get_bustag(sc->rl_res);
867 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
868 mtx_init(&sc->rl_mtx,
869 device_get_nameunit(dev),
870 MTX_NETWORK_LOCK, MTX_DEF);
871 RL_LOCK(sc);
872 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
873 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
874 RL_UNLOCK(sc);
875 mtx_destroy(&sc->rl_mtx);
876
877 /* Don't attach to 8139C+ or 8169/8110 chips. */
878 if (hwrev == RL_HWREV_8139CPLUS ||
879 hwrev == RL_HWREV_8169 ||
880 hwrev == RL_HWREV_8169S ||
881 hwrev == RL_HWREV_8110S) {
882 t++;
883 continue;
884 }
885
886 device_set_desc(dev, t->rl_name);
887 return(0);
888 }
889 t++;
890 }
891
892 return(ENXIO);
893}
894
895/*
896 * Attach the interface. Allocate softc structures, do ifmedia
897 * setup and ethernet/BPF attach.
898 */
899static int
900rl_attach(dev)
901 device_t dev;
902{
903 u_char eaddr[ETHER_ADDR_LEN];
904 u_int16_t as[3];
905 struct rl_softc *sc;
906 struct ifnet *ifp;
907 u_int16_t rl_did = 0;
908 struct rl_type *t;
909 int unit, error = 0, rid, i;
910
911 sc = device_get_softc(dev);
912 unit = device_get_unit(dev);
913
914 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
915 MTX_DEF | MTX_RECURSE);
916#ifndef BURN_BRIDGES
917 /*
918 * Handle power management nonsense.
919 */
920
921 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
922 u_int32_t iobase, membase, irq;
923
924 /* Save important PCI config data. */
925 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
926 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
927 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
928
929 /* Reset the power state. */
930 printf("rl%d: chip is is in D%d power mode "
931 "-- setting to D0\n", unit,
932 pci_get_powerstate(dev));
933
934 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
935
936 /* Restore PCI config data. */
937 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
938 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
939 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
940 }
941#endif
942 /*
943 * Map control/status registers.
944 */
945 pci_enable_busmaster(dev);
946
947 rid = RL_RID;
948 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
949 0, ~0, 1, RF_ACTIVE);
950
951 if (sc->rl_res == NULL) {
952 printf ("rl%d: couldn't map ports/memory\n", unit);
953 error = ENXIO;
954 goto fail;
955 }
956
957#ifdef notdef
958 /* Detect the Realtek 8139B. For some reason, this chip is very
959 * unstable when left to autoselect the media
960 * The best workaround is to set the device to the required
961 * media type or to set it to the 10 Meg speed.
962 */
963
964 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) {
965 printf("rl%d: Realtek 8139B detected. Warning, "
966 "this may be unstable in autoselect mode\n", unit);
967 }
968#endif
969
970 sc->rl_btag = rman_get_bustag(sc->rl_res);
971 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
972
973 /* Allocate interrupt */
974 rid = 0;
975 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
976 RF_SHAREABLE | RF_ACTIVE);
977
978 if (sc->rl_irq == NULL) {
979 printf("rl%d: couldn't map interrupt\n", unit);
980 error = ENXIO;
981 goto fail;
982 }
983
984 /* Reset the adapter. */
985 rl_reset(sc);
986 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
987 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0);
988 if (rl_did != 0x8129)
989 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
990
991 /*
992 * Get station address from the EEPROM.
993 */
994 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
995 for (i = 0; i < 3; i++) {
996 eaddr[(i * 2) + 0] = as[i] & 0xff;
997 eaddr[(i * 2) + 1] = as[i] >> 8;
998 }
999
1000 /*
1001 * A RealTek chip was detected. Inform the world.
1002 */
1003 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
1004
1005 sc->rl_unit = unit;
1006 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
1007
1008 /*
1009 * Now read the exact device type from the EEPROM to find
1010 * out if it's an 8129 or 8139.
1011 */
1012 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
1013
1014 t = rl_devs;
1015 sc->rl_type = 0;
1016 while(t->rl_name != NULL) {
1017 if (rl_did == t->rl_did) {
1018 sc->rl_type = t->rl_basetype;
1019 break;
1020 }
1021 t++;
1022 }
1023
1024 if (sc->rl_type == 0) {
1025 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
1026 error = ENXIO;
1027 goto fail;
1028 }
1029
1030 /*
1031 * Allocate the parent bus DMA tag appropriate for PCI.
1032 */
1033#define RL_NSEG_NEW 32
1034 error = bus_dma_tag_create(NULL, /* parent */
1035 1, 0, /* alignment, boundary */
1036 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1037 BUS_SPACE_MAXADDR, /* highaddr */
1038 NULL, NULL, /* filter, filterarg */
1039 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
1040 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1041 BUS_DMA_ALLOCNOW, /* flags */
1042 NULL, NULL, /* lockfunc, lockarg */
1043 &sc->rl_parent_tag);
1044 if (error)
1045 goto fail;
1046
1047 /*
1048 * Now allocate a tag for the DMA descriptor lists.
1049 * All of our lists are allocated as a contiguous block
1050 * of memory.
1051 */
1052 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
1053 1, 0, /* alignment, boundary */
1054 BUS_SPACE_MAXADDR, /* lowaddr */
1055 BUS_SPACE_MAXADDR, /* highaddr */
1056 NULL, NULL, /* filter, filterarg */
1057 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
1058 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1059 BUS_DMA_ALLOCNOW, /* flags */
1060 NULL, NULL, /* lockfunc, lockarg */
1061 &sc->rl_tag);
1062 if (error)
1063 goto fail;
1064
1065 /*
1066 * Now allocate a chunk of DMA-able memory based on the
1067 * tag we just created.
1068 */
1069 error = bus_dmamem_alloc(sc->rl_tag,
1070 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1071 &sc->rl_cdata.rl_rx_dmamap);
1072
1073 if (error) {
1074 printf("rl%d: no memory for list buffers!\n", unit);
1075 bus_dma_tag_destroy(sc->rl_tag);
1076 sc->rl_tag = NULL;
1077 goto fail;
1078 }
1079
1080 /* Leave a few bytes before the start of the RX ring buffer. */
1081 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1082 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
1083
1084 /* Do MII setup */
1085 if (mii_phy_probe(dev, &sc->rl_miibus,
1086 rl_ifmedia_upd, rl_ifmedia_sts)) {
1087 printf("rl%d: MII without any phy!\n", sc->rl_unit);
1088 error = ENXIO;
1089 goto fail;
1090 }
1091
1092 ifp = &sc->arpcom.ac_if;
1093 ifp->if_softc = sc;
1094 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1095 ifp->if_mtu = ETHERMTU;
1096 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1097 ifp->if_ioctl = rl_ioctl;
1098 ifp->if_output = ether_output;
1099 ifp->if_start = rl_start;
1100 ifp->if_watchdog = rl_watchdog;
1101 ifp->if_init = rl_init;
1102 ifp->if_baudrate = 10000000;
1103 ifp->if_capabilities = IFCAP_VLAN_MTU;
1104 ifp->if_capenable = ifp->if_capabilities;
1105 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1106
1107 callout_handle_init(&sc->rl_stat_ch);
1108
1109 /*
1110 * Call MI attach routine.
1111 */
1112 ether_ifattach(ifp, eaddr);
1113
1114 /* Hook interrupt last to avoid having to lock softc */
1115 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
1116 rl_intr, sc, &sc->rl_intrhand);
1117
1118 if (error) {
1119 printf("rl%d: couldn't set up irq\n", unit);
1120 ether_ifdetach(ifp);
1121 goto fail;
1122 }
1123
1124fail:
1125 if (error)
1126 rl_detach(dev);
1127
1128 return (error);
1129}
1130
1131/*
1132 * Shutdown hardware and free up resources. This can be called any
1133 * time after the mutex has been initialized. It is called in both
1134 * the error case in attach and the normal detach case so it needs
1135 * to be careful about only freeing resources that have actually been
1136 * allocated.
1137 */
1138static int
1139rl_detach(dev)
1140 device_t dev;
1141{
1142 struct rl_softc *sc;
1143 struct ifnet *ifp;
1144
1145 sc = device_get_softc(dev);
1146 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1147 RL_LOCK(sc);
1148 ifp = &sc->arpcom.ac_if;
1149
1150 /* These should only be active if attach succeeded */
1151 if (device_is_attached(dev)) {
1152 rl_stop(sc);
1153 ether_ifdetach(ifp);
1154 }
1155 if (sc->rl_miibus)
1156 device_delete_child(dev, sc->rl_miibus);
1157 bus_generic_detach(dev);
1158
1159 if (sc->rl_intrhand)
1160 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1161 if (sc->rl_irq)
1162 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1163 if (sc->rl_res)
1164 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1165
1166 if (sc->rl_tag) {
1167 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1168 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1169 sc->rl_cdata.rl_rx_dmamap);
1170 bus_dma_tag_destroy(sc->rl_tag);
1171 }
1172 if (sc->rl_parent_tag)
1173 bus_dma_tag_destroy(sc->rl_parent_tag);
1174
1175 RL_UNLOCK(sc);
1176 mtx_destroy(&sc->rl_mtx);
1177
1178 return(0);
1179}
1180
1181/*
1182 * Initialize the transmit descriptors.
1183 */
1184static int
1185rl_list_tx_init(sc)
1186 struct rl_softc *sc;
1187{
1188 struct rl_chain_data *cd;
1189 int i;
1190
1191 cd = &sc->rl_cdata;
1192 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1193 cd->rl_tx_chain[i] = NULL;
1194 CSR_WRITE_4(sc,
1195 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
1196 }
1197
1198 sc->rl_cdata.cur_tx = 0;
1199 sc->rl_cdata.last_tx = 0;
1200
1201 return(0);
1202}
1203
1204/*
1205 * A frame has been uploaded: pass the resulting mbuf chain up to
1206 * the higher level protocols.
1207 *
1208 * You know there's something wrong with a PCI bus-master chip design
1209 * when you have to use m_devget().
1210 *
1211 * The receive operation is badly documented in the datasheet, so I'll
1212 * attempt to document it here. The driver provides a buffer area and
1213 * places its base address in the RX buffer start address register.
1214 * The chip then begins copying frames into the RX buffer. Each frame
1215 * is preceded by a 32-bit RX status word which specifies the length
1216 * of the frame and certain other status bits. Each frame (starting with
1217 * the status word) is also 32-bit aligned. The frame length is in the
1218 * first 16 bits of the status word; the lower 15 bits correspond with
1219 * the 'rx status register' mentioned in the datasheet.
1220 *
1221 * Note: to make the Alpha happy, the frame payload needs to be aligned
1222 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1223 * as the offset argument to m_devget().
1224 */
1225static void
1226rl_rxeof(sc)
1227 struct rl_softc *sc;
1228{
1229 struct mbuf *m;
1230 struct ifnet *ifp;
1231 int total_len = 0;
1232 u_int32_t rxstat;
1233 caddr_t rxbufpos;
1234 int wrap = 0;
1235 u_int16_t cur_rx;
1236 u_int16_t limit;
1237 u_int16_t rx_bytes = 0, max_bytes;
1238
1239 ifp = &sc->arpcom.ac_if;
1240
1241 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1242 BUS_DMASYNC_POSTREAD);
1243
1244 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1245
1246 /* Do not try to read past this point. */
1247 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1248
1249 if (limit < cur_rx)
1250 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1251 else
1252 max_bytes = limit - cur_rx;
1253
1254 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1255#ifdef DEVICE_POLLING
1256 if (ifp->if_flags & IFF_POLLING) {
1257 if (sc->rxcycles <= 0)
1258 break;
1259 sc->rxcycles--;
1260 }
1261#endif /* DEVICE_POLLING */
1262 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1263 rxstat = le32toh(*(u_int32_t *)rxbufpos);
1264
1265 /*
1266 * Here's a totally undocumented fact for you. When the
1267 * RealTek chip is in the process of copying a packet into
1268 * RAM for you, the length will be 0xfff0. If you spot a
1269 * packet header with this value, you need to stop. The
1270 * datasheet makes absolutely no mention of this and
1271 * RealTek should be shot for this.
1272 */
1273 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1274 break;
1275
1276 if (!(rxstat & RL_RXSTAT_RXOK)) {
1277 ifp->if_ierrors++;
1278 rl_init(sc);
1279 return;
1280 }
1281
1282 /* No errors; receive the packet. */
1283 total_len = rxstat >> 16;
1284 rx_bytes += total_len + 4;
1285
1286 /*
1287 * XXX The RealTek chip includes the CRC with every
1288 * received frame, and there's no way to turn this
1289 * behavior off (at least, I can't find anything in
1290 * the manual that explains how to do it) so we have
1291 * to trim off the CRC manually.
1292 */
1293 total_len -= ETHER_CRC_LEN;
1294
1295 /*
1296 * Avoid trying to read more bytes than we know
1297 * the chip has prepared for us.
1298 */
1299 if (rx_bytes > max_bytes)
1300 break;
1301
1302 rxbufpos = sc->rl_cdata.rl_rx_buf +
1303 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1304
1305 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1306 rxbufpos = sc->rl_cdata.rl_rx_buf;
1307
1308 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1309
1310 if (total_len > wrap) {
1311 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1312 NULL);
1313 if (m == NULL) {
1314 ifp->if_ierrors++;
1315 } else {
1316 m_copyback(m, wrap, total_len - wrap,
1317 sc->rl_cdata.rl_rx_buf);
1318 }
1319 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1320 } else {
1321 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1322 NULL);
1323 if (m == NULL) {
1324 ifp->if_ierrors++;
1325 }
1326 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1327 }
1328
1329 /*
1330 * Round up to 32-bit boundary.
1331 */
1332 cur_rx = (cur_rx + 3) & ~3;
1333 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1334
1335 if (m == NULL)
1336 continue;
1337
1338 ifp->if_ipackets++;
1339 (*ifp->if_input)(ifp, m);
1340 }
1341
1342 return;
1343}
1344
1345/*
1346 * A frame was downloaded to the chip. It's safe for us to clean up
1347 * the list buffers.
1348 */
1349static void
1350rl_txeof(sc)
1351 struct rl_softc *sc;
1352{
1353 struct ifnet *ifp;
1354 u_int32_t txstat;
1355
1356 ifp = &sc->arpcom.ac_if;
1357
1358 /*
1359 * Go through our tx list and free mbufs for those
1360 * frames that have been uploaded.
1361 */
1362 do {
1363 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1364 if (!(txstat & (RL_TXSTAT_TX_OK|
1365 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1366 break;
1367
1368 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1369
1370 if (RL_LAST_TXMBUF(sc) != NULL) {
1371 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1372 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1373 m_freem(RL_LAST_TXMBUF(sc));
1374 RL_LAST_TXMBUF(sc) = NULL;
1375 }
1376 if (txstat & RL_TXSTAT_TX_OK)
1377 ifp->if_opackets++;
1378 else {
1379 int oldthresh;
1380 ifp->if_oerrors++;
1381 if ((txstat & RL_TXSTAT_TXABRT) ||
1382 (txstat & RL_TXSTAT_OUTOFWIN))
1383 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1384 oldthresh = sc->rl_txthresh;
1385 /* error recovery */
1386 rl_reset(sc);
1387 rl_init(sc);
1388 /*
1389 * If there was a transmit underrun,
1390 * bump the TX threshold.
1391 */
1392 if (txstat & RL_TXSTAT_TX_UNDERRUN)
1393 sc->rl_txthresh = oldthresh + 32;
1394 return;
1395 }
1396 RL_INC(sc->rl_cdata.last_tx);
1397 ifp->if_flags &= ~IFF_OACTIVE;
1398 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1399
1400 ifp->if_timer =
1401 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5;
1402
1403 return;
1404}
1405
1406static void
1407rl_tick(xsc)
1408 void *xsc;
1409{
1410 struct rl_softc *sc;
1411 struct mii_data *mii;
1412
1413 sc = xsc;
1414 RL_LOCK(sc);
1415 mii = device_get_softc(sc->rl_miibus);
1416
1417 mii_tick(mii);
1418
1419 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1420 RL_UNLOCK(sc);
1421
1422 return;
1423}
1424
1425#ifdef DEVICE_POLLING
1426static void
1427rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1428{
1429 struct rl_softc *sc = ifp->if_softc;
1430
1431 RL_LOCK(sc);
1432 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1433 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1434 goto done;
1435 }
1436
1437 sc->rxcycles = count;
1438 rl_rxeof(sc);
1439 rl_txeof(sc);
1440 if (ifp->if_snd.ifq_head != NULL)
1441 rl_start(ifp);
1442
1443 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1444 u_int16_t status;
1445
1446 status = CSR_READ_2(sc, RL_ISR);
1447 if (status == 0xffff)
1448 goto done;
1449 if (status)
1450 CSR_WRITE_2(sc, RL_ISR, status);
1451
1452 /*
1453 * XXX check behaviour on receiver stalls.
1454 */
1455
1456 if (status & RL_ISR_SYSTEM_ERR) {
1457 rl_reset(sc);
1458 rl_init(sc);
1459 }
1460 }
1461done:
1462 RL_UNLOCK(sc);
1463}
1464#endif /* DEVICE_POLLING */
1465
1466static void
1467rl_intr(arg)
1468 void *arg;
1469{
1470 struct rl_softc *sc;
1471 struct ifnet *ifp;
1472 u_int16_t status;
1473
1474 sc = arg;
1475
1476 if (sc->suspended) {
1477 return;
1478 }
1479
1480 RL_LOCK(sc);
1481 ifp = &sc->arpcom.ac_if;
1482
1483#ifdef DEVICE_POLLING
1484 if (ifp->if_flags & IFF_POLLING)
1485 goto done;
1486 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
1487 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1488 rl_poll(ifp, 0, 1);
1489 goto done;
1490 }
1491#endif /* DEVICE_POLLING */
1492
1493 for (;;) {
1494
1495 status = CSR_READ_2(sc, RL_ISR);
1496 /* If the card has gone away the read returns 0xffff. */
1497 if (status == 0xffff)
1498 break;
1499 if (status)
1500 CSR_WRITE_2(sc, RL_ISR, status);
1501
1502 if ((status & RL_INTRS) == 0)
1503 break;
1504
1505 if (status & RL_ISR_RX_OK)
1506 rl_rxeof(sc);
1507
1508 if (status & RL_ISR_RX_ERR)
1509 rl_rxeof(sc);
1510
1511 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1512 rl_txeof(sc);
1513
1514 if (status & RL_ISR_SYSTEM_ERR) {
1515 rl_reset(sc);
1516 rl_init(sc);
1517 }
1518
1519 }
1520
1521 if (ifp->if_snd.ifq_head != NULL)
1522 rl_start(ifp);
1523
1524#ifdef DEVICE_POLLING
1525done:
1526#endif
1527 RL_UNLOCK(sc);
1528
1529 return;
1530}
1531
1532/*
1533 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1534 * pointers to the fragment pointers.
1535 */
1536static int
1537rl_encap(sc, m_head)
1538 struct rl_softc *sc;
1539 struct mbuf *m_head;
1540{
1541 struct mbuf *m_new = NULL;
1542
1543 /*
1544 * The RealTek is brain damaged and wants longword-aligned
1545 * TX buffers, plus we can only have one fragment buffer
1546 * per packet. We have to copy pretty much all the time.
1547 */
1548 m_new = m_defrag(m_head, M_DONTWAIT);
1549
1550 if (m_new == NULL) {
1551 m_freem(m_head);
1552 return(1);
1553 }
1554 m_head = m_new;
1555
1556 /* Pad frames to at least 60 bytes. */
1557 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1558 /*
1559 * Make security concious people happy: zero out the
1560 * bytes in the pad area, since we don't know what
1561 * this mbuf cluster buffer's previous user might
1562 * have left in it.
1563 */
1564 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1565 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1566 m_head->m_pkthdr.len +=
1567 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1568 m_head->m_len = m_head->m_pkthdr.len;
1569 }
1570
1571 RL_CUR_TXMBUF(sc) = m_head;
1572
1573 return(0);
1574}
1575
1576/*
1577 * Main transmit routine.
1578 */
1579
1580static void
1581rl_start(ifp)
1582 struct ifnet *ifp;
1583{
1584 struct rl_softc *sc;
1585 struct mbuf *m_head = NULL;
1586
1587 sc = ifp->if_softc;
1588 RL_LOCK(sc);
1589
1590 while(RL_CUR_TXMBUF(sc) == NULL) {
1591 IF_DEQUEUE(&ifp->if_snd, m_head);
1592 if (m_head == NULL)
1593 break;
1594
1595 if (rl_encap(sc, m_head)) {
1596 break;
1597 }
1598
1599 /*
1600 * If there's a BPF listener, bounce a copy of this frame
1601 * to him.
1602 */
1603 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1604
1605 /*
1606 * Transmit the frame.
1607 */
1608 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1609 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1610 mtod(RL_CUR_TXMBUF(sc), void *),
1611 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1612 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1613 BUS_DMASYNC_PREREAD);
1614 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1615 RL_TXTHRESH(sc->rl_txthresh) |
1616 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1617
1618 RL_INC(sc->rl_cdata.cur_tx);
1619
1620 /*
1621 * Set a timeout in case the chip goes out to lunch.
1622 */
1623 ifp->if_timer = 5;
1624 }
1625
1626 /*
1627 * We broke out of the loop because all our TX slots are
1628 * full. Mark the NIC as busy until it drains some of the
1629 * packets from the queue.
1630 */
1631 if (RL_CUR_TXMBUF(sc) != NULL)
1632 ifp->if_flags |= IFF_OACTIVE;
1633
1634 RL_UNLOCK(sc);
1635
1636 return;
1637}
1638
1639static void
1640rl_init(xsc)
1641 void *xsc;
1642{
1643 struct rl_softc *sc = xsc;
1644 struct ifnet *ifp = &sc->arpcom.ac_if;
1645 struct mii_data *mii;
1646 u_int32_t rxcfg = 0;
1647
1648 RL_LOCK(sc);
1649 mii = device_get_softc(sc->rl_miibus);
1650
1651 /*
1652 * Cancel pending I/O and free all RX/TX buffers.
1653 */
1654 rl_stop(sc);
1655
1656 /*
1657 * Init our MAC address. Even though the chipset
1658 * documentation doesn't mention it, we need to enter "Config
1659 * register write enable" mode to modify the ID registers.
1660 */
1661 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1662 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1663 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1664 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1665 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1666 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1667
1668 /* Init the RX buffer pointer register. */
1669 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1670 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1671 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1672 BUS_DMASYNC_PREWRITE);
1673
1674 /* Init TX descriptors. */
1675 rl_list_tx_init(sc);
1676
1677 /*
1678 * Enable transmit and receive.
1679 */
1680 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1681
1682 /*
1683 * Set the initial TX and RX configuration.
1684 */
1685 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1686 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1687
1688 /* Set the individual bit to receive frames for this host only. */
1689 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1690 rxcfg |= RL_RXCFG_RX_INDIV;
1691
1692 /* If we want promiscuous mode, set the allframes bit. */
1693 if (ifp->if_flags & IFF_PROMISC) {
1694 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1695 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1696 } else {
1697 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1698 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1699 }
1700
1701 /*
1702 * Set capture broadcast bit to capture broadcast frames.
1703 */
1704 if (ifp->if_flags & IFF_BROADCAST) {
1705 rxcfg |= RL_RXCFG_RX_BROAD;
1706 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1707 } else {
1708 rxcfg &= ~RL_RXCFG_RX_BROAD;
1709 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1710 }
1711
1712 /*
1713 * Program the multicast filter, if necessary.
1714 */
1715 rl_setmulti(sc);
1716
1717#ifdef DEVICE_POLLING
1718 /*
1719 * Disable interrupts if we are polling.
1720 */
1721 if (ifp->if_flags & IFF_POLLING)
1722 CSR_WRITE_2(sc, RL_IMR, 0);
1723 else /* otherwise ... */
1724#endif /* DEVICE_POLLING */
1725 /*
1726 * Enable interrupts.
1727 */
1728 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1729
1730 /* Set initial TX threshold */
1731 sc->rl_txthresh = RL_TX_THRESH_INIT;
1732
1733 /* Start RX/TX process. */
1734 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1735
1736 /* Enable receiver and transmitter. */
1737 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1738
1739 mii_mediachg(mii);
1740
1741 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1742
1743 ifp->if_flags |= IFF_RUNNING;
1744 ifp->if_flags &= ~IFF_OACTIVE;
1745
1746 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1747 RL_UNLOCK(sc);
1748
1749 return;
1750}
1751
1752/*
1753 * Set media options.
1754 */
1755static int
1756rl_ifmedia_upd(ifp)
1757 struct ifnet *ifp;
1758{
1759 struct rl_softc *sc;
1760 struct mii_data *mii;
1761
1762 sc = ifp->if_softc;
1763 mii = device_get_softc(sc->rl_miibus);
1764 mii_mediachg(mii);
1765
1766 return(0);
1767}
1768
1769/*
1770 * Report current media status.
1771 */
1772static void
1773rl_ifmedia_sts(ifp, ifmr)
1774 struct ifnet *ifp;
1775 struct ifmediareq *ifmr;
1776{
1777 struct rl_softc *sc;
1778 struct mii_data *mii;
1779
1780 sc = ifp->if_softc;
1781 mii = device_get_softc(sc->rl_miibus);
1782
1783 mii_pollstat(mii);
1784 ifmr->ifm_active = mii->mii_media_active;
1785 ifmr->ifm_status = mii->mii_media_status;
1786
1787 return;
1788}
1789
1790static int
1791rl_ioctl(ifp, command, data)
1792 struct ifnet *ifp;
1793 u_long command;
1794 caddr_t data;
1795{
1796 struct rl_softc *sc = ifp->if_softc;
1797 struct ifreq *ifr = (struct ifreq *) data;
1798 struct mii_data *mii;
1799 int error = 0;
1800
1801 RL_LOCK(sc);
1802
1803 switch(command) {
1804 case SIOCSIFFLAGS:
1805 if (ifp->if_flags & IFF_UP) {
1806 rl_init(sc);
1807 } else {
1808 if (ifp->if_flags & IFF_RUNNING)
1809 rl_stop(sc);
1810 }
1811 error = 0;
1812 break;
1813 case SIOCADDMULTI:
1814 case SIOCDELMULTI:
1815 rl_setmulti(sc);
1816 error = 0;
1817 break;
1818 case SIOCGIFMEDIA:
1819 case SIOCSIFMEDIA:
1820 mii = device_get_softc(sc->rl_miibus);
1821 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1822 break;
1823 default:
1824 error = ether_ioctl(ifp, command, data);
1825 break;
1826 }
1827
1828 RL_UNLOCK(sc);
1829
1830 return(error);
1831}
1832
1833static void
1834rl_watchdog(ifp)
1835 struct ifnet *ifp;
1836{
1837 struct rl_softc *sc;
1838
1839 sc = ifp->if_softc;
1840 RL_LOCK(sc);
1841 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1842 ifp->if_oerrors++;
1843
1844 rl_txeof(sc);
1845 rl_rxeof(sc);
1846 rl_init(sc);
1847 RL_UNLOCK(sc);
1848
1849 return;
1850}
1851
1852/*
1853 * Stop the adapter and free any mbufs allocated to the
1854 * RX and TX lists.
1855 */
1856static void
1857rl_stop(sc)
1858 struct rl_softc *sc;
1859{
1860 register int i;
1861 struct ifnet *ifp;
1862
1863 RL_LOCK(sc);
1864 ifp = &sc->arpcom.ac_if;
1865 ifp->if_timer = 0;
1866
1867 untimeout(rl_tick, sc, sc->rl_stat_ch);
1868 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1869#ifdef DEVICE_POLLING
1870 ether_poll_deregister(ifp);
1871#endif /* DEVICE_POLLING */
1872
1873 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1874 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1875 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1876
1877 /*
1878 * Free the TX list buffers.
1879 */
1880 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1881 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1882 bus_dmamap_unload(sc->rl_tag,
1883 sc->rl_cdata.rl_tx_dmamap[i]);
1884 bus_dmamap_destroy(sc->rl_tag,
1885 sc->rl_cdata.rl_tx_dmamap[i]);
1886 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1887 sc->rl_cdata.rl_tx_chain[i] = NULL;
1888 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1889 }
1890 }
1891
1892 RL_UNLOCK(sc);
1893 return;
1894}
1895
1896/*
1897 * Device suspend routine. Stop the interface and save some PCI
1898 * settings in case the BIOS doesn't restore them properly on
1899 * resume.
1900 */
1901static int
1902rl_suspend(dev)
1903 device_t dev;
1904{
1905 register int i;
1906 struct rl_softc *sc;
1907
1908 sc = device_get_softc(dev);
1909
1910 rl_stop(sc);
1911
1912 for (i = 0; i < 5; i++)
1913 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
1914 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1915 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1916 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1917 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1918
1919 sc->suspended = 1;
1920
1921 return (0);
1922}
1923
1924/*
1925 * Device resume routine. Restore some PCI settings in case the BIOS
1926 * doesn't, re-enable busmastering, and restart the interface if
1927 * appropriate.
1928 */
1929static int
1930rl_resume(dev)
1931 device_t dev;
1932{
1933 register int i;
1934 struct rl_softc *sc;
1935 struct ifnet *ifp;
1936
1937 sc = device_get_softc(dev);
1938 ifp = &sc->arpcom.ac_if;
1939
1940 /* better way to do this? */
1941 for (i = 0; i < 5; i++)
1942 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
1943 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1944 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1945 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1946 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1947
1948 /* reenable busmastering */
1949 pci_enable_busmaster(dev);
1950 pci_enable_io(dev, RL_RES);
1951
1952 /* reinitialize interface if necessary */
1953 if (ifp->if_flags & IFF_UP)
1954 rl_init(sc);
1955
1956 sc->suspended = 0;
1957
1958 return (0);
1959}
1960
1961/*
1962 * Stop all chip I/O so that the kernel's probe routines don't
1963 * get confused by errant DMAs when rebooting.
1964 */
1965static void
1966rl_shutdown(dev)
1967 device_t dev;
1968{
1969 struct rl_softc *sc;
1970
1971 sc = device_get_softc(dev);
1972
1973 rl_stop(sc);
1974
1975 return;
1976}
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