1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
| 1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
|
32 * $FreeBSD: head/sys/pci/if_rl.c 94883 2002-04-16 22:03:14Z luigi $
| 32 * $FreeBSD: head/sys/pci/if_rl.c 96112 2002-05-06 13:43:00Z jhb $
|
33 */
34
35/*
36 * RealTek 8129/8139 PCI NIC driver
37 *
38 * Supports several extremely cheap PCI 10/100 adapters based on
39 * the RealTek chipset. Datasheets can be obtained from
40 * www.realtek.com.tw.
41 *
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
45 */
46
47/*
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
53 *
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
62 *
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
68 * levels.
69 *
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
73 *
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
78 * filter.
79 *
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
84 */
85
86#include <sys/param.h>
87#include <sys/systm.h>
88#include <sys/sockio.h>
89#include <sys/mbuf.h>
90#include <sys/malloc.h>
91#include <sys/kernel.h>
92#include <sys/socket.h>
93
94#include <net/if.h>
95#include <net/if_arp.h>
96#include <net/ethernet.h>
97#include <net/if_dl.h>
98#include <net/if_media.h>
99
100#include <net/bpf.h>
101
102#include <machine/bus_pio.h>
103#include <machine/bus_memio.h>
104#include <machine/bus.h>
105#include <machine/resource.h>
106#include <sys/bus.h>
107#include <sys/rman.h>
108
109#include <dev/mii/mii.h>
110#include <dev/mii/miivar.h>
111
112#include <pci/pcireg.h>
113#include <pci/pcivar.h>
114
115MODULE_DEPEND(rl, miibus, 1, 1, 1);
116
117/* "controller miibus0" required. See GENERIC if you get errors here. */
118#include "miibus_if.h"
119
120/*
121 * Default to using PIO access for this driver. On SMP systems,
122 * there appear to be problems with memory mapped mode: it looks like
123 * doing too many memory mapped access back to back in rapid succession
124 * can hang the bus. I'm inclined to blame this on crummy design/construction
125 * on the part of RealTek. Memory mapped mode does appear to work on
126 * uniprocessor systems though.
127 */
128#define RL_USEIOSPACE
129
130#include <pci/if_rlreg.h>
131
132#ifndef lint
133static const char rcsid[] =
| 33 */
34
35/*
36 * RealTek 8129/8139 PCI NIC driver
37 *
38 * Supports several extremely cheap PCI 10/100 adapters based on
39 * the RealTek chipset. Datasheets can be obtained from
40 * www.realtek.com.tw.
41 *
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
45 */
46
47/*
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
53 *
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
62 *
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
68 * levels.
69 *
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
73 *
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
78 * filter.
79 *
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
84 */
85
86#include <sys/param.h>
87#include <sys/systm.h>
88#include <sys/sockio.h>
89#include <sys/mbuf.h>
90#include <sys/malloc.h>
91#include <sys/kernel.h>
92#include <sys/socket.h>
93
94#include <net/if.h>
95#include <net/if_arp.h>
96#include <net/ethernet.h>
97#include <net/if_dl.h>
98#include <net/if_media.h>
99
100#include <net/bpf.h>
101
102#include <machine/bus_pio.h>
103#include <machine/bus_memio.h>
104#include <machine/bus.h>
105#include <machine/resource.h>
106#include <sys/bus.h>
107#include <sys/rman.h>
108
109#include <dev/mii/mii.h>
110#include <dev/mii/miivar.h>
111
112#include <pci/pcireg.h>
113#include <pci/pcivar.h>
114
115MODULE_DEPEND(rl, miibus, 1, 1, 1);
116
117/* "controller miibus0" required. See GENERIC if you get errors here. */
118#include "miibus_if.h"
119
120/*
121 * Default to using PIO access for this driver. On SMP systems,
122 * there appear to be problems with memory mapped mode: it looks like
123 * doing too many memory mapped access back to back in rapid succession
124 * can hang the bus. I'm inclined to blame this on crummy design/construction
125 * on the part of RealTek. Memory mapped mode does appear to work on
126 * uniprocessor systems though.
127 */
128#define RL_USEIOSPACE
129
130#include <pci/if_rlreg.h>
131
132#ifndef lint
133static const char rcsid[] =
|
134 "$FreeBSD: head/sys/pci/if_rl.c 94883 2002-04-16 22:03:14Z luigi $";
| 134 "$FreeBSD: head/sys/pci/if_rl.c 96112 2002-05-06 13:43:00Z jhb $";
|
135#endif
136
137/*
138 * Various supported device vendors/types and their names.
139 */
140static struct rl_type rl_devs[] = {
141 { RT_VENDORID, RT_DEVICEID_8129,
142 "RealTek 8129 10/100BaseTX" },
143 { RT_VENDORID, RT_DEVICEID_8139,
144 "RealTek 8139 10/100BaseTX" },
145 { RT_VENDORID, RT_DEVICEID_8138,
146 "RealTek 8139 10/100BaseTX CardBus" },
147 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
148 "Accton MPX 5030/5038 10/100BaseTX" },
149 { DELTA_VENDORID, DELTA_DEVICEID_8139,
150 "Delta Electronics 8139 10/100BaseTX" },
151 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
152 "Addtron Technolgy 8139 10/100BaseTX" },
153 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS,
154 "D-Link DFE-530TX+ 10/100BaseTX" },
| 135#endif
136
137/*
138 * Various supported device vendors/types and their names.
139 */
140static struct rl_type rl_devs[] = {
141 { RT_VENDORID, RT_DEVICEID_8129,
142 "RealTek 8129 10/100BaseTX" },
143 { RT_VENDORID, RT_DEVICEID_8139,
144 "RealTek 8139 10/100BaseTX" },
145 { RT_VENDORID, RT_DEVICEID_8138,
146 "RealTek 8139 10/100BaseTX CardBus" },
147 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
148 "Accton MPX 5030/5038 10/100BaseTX" },
149 { DELTA_VENDORID, DELTA_DEVICEID_8139,
150 "Delta Electronics 8139 10/100BaseTX" },
151 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
152 "Addtron Technolgy 8139 10/100BaseTX" },
153 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS,
154 "D-Link DFE-530TX+ 10/100BaseTX" },
|
| 155 { DLINK_VENDORID, DLINK_DEVICEID_690TXD,
156 "D-Link DFE-690TXD 10/100BaseTX" },
|
155 { NORTEL_VENDORID, ACCTON_DEVICEID_5030,
156 "Nortel Networks 10/100BaseTX" },
157 { 0, 0, NULL }
158};
159
160static int rl_probe (device_t);
161static int rl_attach (device_t);
162static int rl_detach (device_t);
163
164static int rl_encap (struct rl_softc *, struct mbuf * );
165
166static void rl_rxeof (struct rl_softc *);
167static void rl_txeof (struct rl_softc *);
168static void rl_intr (void *);
169static void rl_tick (void *);
170static void rl_start (struct ifnet *);
171static int rl_ioctl (struct ifnet *, u_long, caddr_t);
172static void rl_init (void *);
173static void rl_stop (struct rl_softc *);
174static void rl_watchdog (struct ifnet *);
175static int rl_suspend (device_t);
176static int rl_resume (device_t);
177static void rl_shutdown (device_t);
178static int rl_ifmedia_upd (struct ifnet *);
179static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
180
181static void rl_eeprom_putbyte (struct rl_softc *, int);
182static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *);
183static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
184static void rl_mii_sync (struct rl_softc *);
185static void rl_mii_send (struct rl_softc *, u_int32_t, int);
186static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *);
187static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *);
188
189static int rl_miibus_readreg (device_t, int, int);
190static int rl_miibus_writereg (device_t, int, int, int);
191static void rl_miibus_statchg (device_t);
192
193static u_int8_t rl_calchash (caddr_t);
194static void rl_setmulti (struct rl_softc *);
195static void rl_reset (struct rl_softc *);
196static int rl_list_tx_init (struct rl_softc *);
197
198static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int);
199static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int);
200
201#ifdef RL_USEIOSPACE
202#define RL_RES SYS_RES_IOPORT
203#define RL_RID RL_PCI_LOIO
204#else
205#define RL_RES SYS_RES_MEMORY
206#define RL_RID RL_PCI_LOMEM
207#endif
208
209static device_method_t rl_methods[] = {
210 /* Device interface */
211 DEVMETHOD(device_probe, rl_probe),
212 DEVMETHOD(device_attach, rl_attach),
213 DEVMETHOD(device_detach, rl_detach),
214 DEVMETHOD(device_suspend, rl_suspend),
215 DEVMETHOD(device_resume, rl_resume),
216 DEVMETHOD(device_shutdown, rl_shutdown),
217
218 /* bus interface */
219 DEVMETHOD(bus_print_child, bus_generic_print_child),
220 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
221
222 /* MII interface */
223 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
224 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
225 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
226
227 { 0, 0 }
228};
229
230static driver_t rl_driver = {
231 "rl",
232 rl_methods,
233 sizeof(struct rl_softc)
234};
235
236static devclass_t rl_devclass;
237
238DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
239DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0);
240DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
241
242#define EE_SET(x) \
243 CSR_WRITE_1(sc, RL_EECMD, \
244 CSR_READ_1(sc, RL_EECMD) | x)
245
246#define EE_CLR(x) \
247 CSR_WRITE_1(sc, RL_EECMD, \
248 CSR_READ_1(sc, RL_EECMD) & ~x)
249
250static void
251rl_dma_map_rxbuf(arg, segs, nseg, error)
252 void *arg;
253 bus_dma_segment_t *segs;
254 int nseg, error;
255{
256 struct rl_softc *sc;
257
258 sc = arg;
259 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
260
261 return;
262}
263
264static void
265rl_dma_map_txbuf(arg, segs, nseg, error)
266 void *arg;
267 bus_dma_segment_t *segs;
268 int nseg, error;
269{
270 struct rl_softc *sc;
271
272 sc = arg;
273 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
274
275 return;
276}
277
278/*
279 * Send a read command and address to the EEPROM, check for ACK.
280 */
281static void rl_eeprom_putbyte(sc, addr)
282 struct rl_softc *sc;
283 int addr;
284{
285 register int d, i;
286
287 d = addr | sc->rl_eecmd_read;
288
289 /*
290 * Feed in each bit and strobe the clock.
291 */
292 for (i = 0x400; i; i >>= 1) {
293 if (d & i) {
294 EE_SET(RL_EE_DATAIN);
295 } else {
296 EE_CLR(RL_EE_DATAIN);
297 }
298 DELAY(100);
299 EE_SET(RL_EE_CLK);
300 DELAY(150);
301 EE_CLR(RL_EE_CLK);
302 DELAY(100);
303 }
304
305 return;
306}
307
308/*
309 * Read a word of data stored in the EEPROM at address 'addr.'
310 */
311static void rl_eeprom_getword(sc, addr, dest)
312 struct rl_softc *sc;
313 int addr;
314 u_int16_t *dest;
315{
316 register int i;
317 u_int16_t word = 0;
318
319 /* Enter EEPROM access mode. */
320 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
321
322 /*
323 * Send address of word we want to read.
324 */
325 rl_eeprom_putbyte(sc, addr);
326
327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
328
329 /*
330 * Start reading bits from EEPROM.
331 */
332 for (i = 0x8000; i; i >>= 1) {
333 EE_SET(RL_EE_CLK);
334 DELAY(100);
335 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
336 word |= i;
337 EE_CLR(RL_EE_CLK);
338 DELAY(100);
339 }
340
341 /* Turn off EEPROM access mode. */
342 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
343
344 *dest = word;
345
346 return;
347}
348
349/*
350 * Read a sequence of words from the EEPROM.
351 */
352static void rl_read_eeprom(sc, dest, off, cnt, swap)
353 struct rl_softc *sc;
354 caddr_t dest;
355 int off;
356 int cnt;
357 int swap;
358{
359 int i;
360 u_int16_t word = 0, *ptr;
361
362 for (i = 0; i < cnt; i++) {
363 rl_eeprom_getword(sc, off + i, &word);
364 ptr = (u_int16_t *)(dest + (i * 2));
365 if (swap)
366 *ptr = ntohs(word);
367 else
368 *ptr = word;
369 }
370
371 return;
372}
373
374
375/*
376 * MII access routines are provided for the 8129, which
377 * doesn't have a built-in PHY. For the 8139, we fake things
378 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
379 * direct access PHY registers.
380 */
381#define MII_SET(x) \
382 CSR_WRITE_1(sc, RL_MII, \
383 CSR_READ_1(sc, RL_MII) | x)
384
385#define MII_CLR(x) \
386 CSR_WRITE_1(sc, RL_MII, \
387 CSR_READ_1(sc, RL_MII) & ~x)
388
389/*
390 * Sync the PHYs by setting data bit and strobing the clock 32 times.
391 */
392static void rl_mii_sync(sc)
393 struct rl_softc *sc;
394{
395 register int i;
396
397 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
398
399 for (i = 0; i < 32; i++) {
400 MII_SET(RL_MII_CLK);
401 DELAY(1);
402 MII_CLR(RL_MII_CLK);
403 DELAY(1);
404 }
405
406 return;
407}
408
409/*
410 * Clock a series of bits through the MII.
411 */
412static void rl_mii_send(sc, bits, cnt)
413 struct rl_softc *sc;
414 u_int32_t bits;
415 int cnt;
416{
417 int i;
418
419 MII_CLR(RL_MII_CLK);
420
421 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
422 if (bits & i) {
423 MII_SET(RL_MII_DATAOUT);
424 } else {
425 MII_CLR(RL_MII_DATAOUT);
426 }
427 DELAY(1);
428 MII_CLR(RL_MII_CLK);
429 DELAY(1);
430 MII_SET(RL_MII_CLK);
431 }
432}
433
434/*
435 * Read an PHY register through the MII.
436 */
437static int rl_mii_readreg(sc, frame)
438 struct rl_softc *sc;
439 struct rl_mii_frame *frame;
440
441{
442 int i, ack;
443
444 RL_LOCK(sc);
445
446 /*
447 * Set up frame for RX.
448 */
449 frame->mii_stdelim = RL_MII_STARTDELIM;
450 frame->mii_opcode = RL_MII_READOP;
451 frame->mii_turnaround = 0;
452 frame->mii_data = 0;
453
454 CSR_WRITE_2(sc, RL_MII, 0);
455
456 /*
457 * Turn on data xmit.
458 */
459 MII_SET(RL_MII_DIR);
460
461 rl_mii_sync(sc);
462
463 /*
464 * Send command/address info.
465 */
466 rl_mii_send(sc, frame->mii_stdelim, 2);
467 rl_mii_send(sc, frame->mii_opcode, 2);
468 rl_mii_send(sc, frame->mii_phyaddr, 5);
469 rl_mii_send(sc, frame->mii_regaddr, 5);
470
471 /* Idle bit */
472 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
473 DELAY(1);
474 MII_SET(RL_MII_CLK);
475 DELAY(1);
476
477 /* Turn off xmit. */
478 MII_CLR(RL_MII_DIR);
479
480 /* Check for ack */
481 MII_CLR(RL_MII_CLK);
482 DELAY(1);
483 MII_SET(RL_MII_CLK);
484 DELAY(1);
485 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
486
487 /*
488 * Now try reading data bits. If the ack failed, we still
489 * need to clock through 16 cycles to keep the PHY(s) in sync.
490 */
491 if (ack) {
492 for(i = 0; i < 16; i++) {
493 MII_CLR(RL_MII_CLK);
494 DELAY(1);
495 MII_SET(RL_MII_CLK);
496 DELAY(1);
497 }
498 goto fail;
499 }
500
501 for (i = 0x8000; i; i >>= 1) {
502 MII_CLR(RL_MII_CLK);
503 DELAY(1);
504 if (!ack) {
505 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
506 frame->mii_data |= i;
507 DELAY(1);
508 }
509 MII_SET(RL_MII_CLK);
510 DELAY(1);
511 }
512
513fail:
514
515 MII_CLR(RL_MII_CLK);
516 DELAY(1);
517 MII_SET(RL_MII_CLK);
518 DELAY(1);
519
520 RL_UNLOCK(sc);
521
522 if (ack)
523 return(1);
524 return(0);
525}
526
527/*
528 * Write to a PHY register through the MII.
529 */
530static int rl_mii_writereg(sc, frame)
531 struct rl_softc *sc;
532 struct rl_mii_frame *frame;
533
534{
535 RL_LOCK(sc);
536
537 /*
538 * Set up frame for TX.
539 */
540
541 frame->mii_stdelim = RL_MII_STARTDELIM;
542 frame->mii_opcode = RL_MII_WRITEOP;
543 frame->mii_turnaround = RL_MII_TURNAROUND;
544
545 /*
546 * Turn on data output.
547 */
548 MII_SET(RL_MII_DIR);
549
550 rl_mii_sync(sc);
551
552 rl_mii_send(sc, frame->mii_stdelim, 2);
553 rl_mii_send(sc, frame->mii_opcode, 2);
554 rl_mii_send(sc, frame->mii_phyaddr, 5);
555 rl_mii_send(sc, frame->mii_regaddr, 5);
556 rl_mii_send(sc, frame->mii_turnaround, 2);
557 rl_mii_send(sc, frame->mii_data, 16);
558
559 /* Idle bit. */
560 MII_SET(RL_MII_CLK);
561 DELAY(1);
562 MII_CLR(RL_MII_CLK);
563 DELAY(1);
564
565 /*
566 * Turn off xmit.
567 */
568 MII_CLR(RL_MII_DIR);
569
570 RL_UNLOCK(sc);
571
572 return(0);
573}
574
575static int rl_miibus_readreg(dev, phy, reg)
576 device_t dev;
577 int phy, reg;
578{
579 struct rl_softc *sc;
580 struct rl_mii_frame frame;
581 u_int16_t rval = 0;
582 u_int16_t rl8139_reg = 0;
583
584 sc = device_get_softc(dev);
585 RL_LOCK(sc);
586
587 if (sc->rl_type == RL_8139) {
588 /* Pretend the internal PHY is only at address 0 */
589 if (phy) {
590 RL_UNLOCK(sc);
591 return(0);
592 }
593 switch(reg) {
594 case MII_BMCR:
595 rl8139_reg = RL_BMCR;
596 break;
597 case MII_BMSR:
598 rl8139_reg = RL_BMSR;
599 break;
600 case MII_ANAR:
601 rl8139_reg = RL_ANAR;
602 break;
603 case MII_ANER:
604 rl8139_reg = RL_ANER;
605 break;
606 case MII_ANLPAR:
607 rl8139_reg = RL_LPAR;
608 break;
609 case MII_PHYIDR1:
610 case MII_PHYIDR2:
611 RL_UNLOCK(sc);
612 return(0);
613 break;
614 /*
615 * Allow the rlphy driver to read the media status
616 * register. If we have a link partner which does not
617 * support NWAY, this is the register which will tell
618 * us the results of parallel detection.
619 */
620 case RL_MEDIASTAT:
621 rval = CSR_READ_1(sc, RL_MEDIASTAT);
622 RL_UNLOCK(sc);
623 return(rval);
624 break;
625 default:
626 printf("rl%d: bad phy register\n", sc->rl_unit);
627 RL_UNLOCK(sc);
628 return(0);
629 }
630 rval = CSR_READ_2(sc, rl8139_reg);
631 RL_UNLOCK(sc);
632 return(rval);
633 }
634
635 bzero((char *)&frame, sizeof(frame));
636
637 frame.mii_phyaddr = phy;
638 frame.mii_regaddr = reg;
639 rl_mii_readreg(sc, &frame);
640 RL_UNLOCK(sc);
641
642 return(frame.mii_data);
643}
644
645static int rl_miibus_writereg(dev, phy, reg, data)
646 device_t dev;
647 int phy, reg, data;
648{
649 struct rl_softc *sc;
650 struct rl_mii_frame frame;
651 u_int16_t rl8139_reg = 0;
652
653 sc = device_get_softc(dev);
654 RL_LOCK(sc);
655
656 if (sc->rl_type == RL_8139) {
657 /* Pretend the internal PHY is only at address 0 */
658 if (phy) {
659 RL_UNLOCK(sc);
660 return(0);
661 }
662 switch(reg) {
663 case MII_BMCR:
664 rl8139_reg = RL_BMCR;
665 break;
666 case MII_BMSR:
667 rl8139_reg = RL_BMSR;
668 break;
669 case MII_ANAR:
670 rl8139_reg = RL_ANAR;
671 break;
672 case MII_ANER:
673 rl8139_reg = RL_ANER;
674 break;
675 case MII_ANLPAR:
676 rl8139_reg = RL_LPAR;
677 break;
678 case MII_PHYIDR1:
679 case MII_PHYIDR2:
680 RL_UNLOCK(sc);
681 return(0);
682 break;
683 default:
684 printf("rl%d: bad phy register\n", sc->rl_unit);
685 RL_UNLOCK(sc);
686 return(0);
687 }
688 CSR_WRITE_2(sc, rl8139_reg, data);
689 RL_UNLOCK(sc);
690 return(0);
691 }
692
693 bzero((char *)&frame, sizeof(frame));
694
695 frame.mii_phyaddr = phy;
696 frame.mii_regaddr = reg;
697 frame.mii_data = data;
698
699 rl_mii_writereg(sc, &frame);
700
701 RL_UNLOCK(sc);
702 return(0);
703}
704
705static void rl_miibus_statchg(dev)
706 device_t dev;
707{
708 return;
709}
710
711/*
712 * Calculate CRC of a multicast group address, return the upper 6 bits.
713 */
714static u_int8_t rl_calchash(addr)
715 caddr_t addr;
716{
717 u_int32_t crc, carry;
718 int i, j;
719 u_int8_t c;
720
721 /* Compute CRC for the address value. */
722 crc = 0xFFFFFFFF; /* initial value */
723
724 for (i = 0; i < 6; i++) {
725 c = *(addr + i);
726 for (j = 0; j < 8; j++) {
727 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
728 crc <<= 1;
729 c >>= 1;
730 if (carry)
731 crc = (crc ^ 0x04c11db6) | carry;
732 }
733 }
734
735 /* return the filter bit position */
736 return(crc >> 26);
737}
738
739/*
740 * Program the 64-bit multicast hash filter.
741 */
742static void rl_setmulti(sc)
743 struct rl_softc *sc;
744{
745 struct ifnet *ifp;
746 int h = 0;
747 u_int32_t hashes[2] = { 0, 0 };
748 struct ifmultiaddr *ifma;
749 u_int32_t rxfilt;
750 int mcnt = 0;
751
752 ifp = &sc->arpcom.ac_if;
753
754 rxfilt = CSR_READ_4(sc, RL_RXCFG);
755
756 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
757 rxfilt |= RL_RXCFG_RX_MULTI;
758 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
759 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
760 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
761 return;
762 }
763
764 /* first, zot all the existing hash bits */
765 CSR_WRITE_4(sc, RL_MAR0, 0);
766 CSR_WRITE_4(sc, RL_MAR4, 0);
767
768 /* now program new ones */
769 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
770 if (ifma->ifma_addr->sa_family != AF_LINK)
771 continue;
772 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
773 if (h < 32)
774 hashes[0] |= (1 << h);
775 else
776 hashes[1] |= (1 << (h - 32));
777 mcnt++;
778 }
779
780 if (mcnt)
781 rxfilt |= RL_RXCFG_RX_MULTI;
782 else
783 rxfilt &= ~RL_RXCFG_RX_MULTI;
784
785 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
786 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
787 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
788
789 return;
790}
791
792static void rl_reset(sc)
793 struct rl_softc *sc;
794{
795 register int i;
796
797 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
798
799 for (i = 0; i < RL_TIMEOUT; i++) {
800 DELAY(10);
801 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
802 break;
803 }
804 if (i == RL_TIMEOUT)
805 printf("rl%d: reset never completed!\n", sc->rl_unit);
806
807 return;
808}
809
810/*
811 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
812 * IDs against our list and return a device name if we find a match.
813 */
814static int rl_probe(dev)
815 device_t dev;
816{
817 struct rl_type *t;
818
819 t = rl_devs;
820
821 while(t->rl_name != NULL) {
822 if ((pci_get_vendor(dev) == t->rl_vid) &&
823 (pci_get_device(dev) == t->rl_did)) {
824 device_set_desc(dev, t->rl_name);
825 return(0);
826 }
827 t++;
828 }
829
830 return(ENXIO);
831}
832
833/*
834 * Attach the interface. Allocate softc structures, do ifmedia
835 * setup and ethernet/BPF attach.
836 */
837static int rl_attach(dev)
838 device_t dev;
839{
840 u_char eaddr[ETHER_ADDR_LEN];
841 u_int32_t command;
842 struct rl_softc *sc;
843 struct ifnet *ifp;
844 u_int16_t rl_did = 0;
845 int unit, error = 0, rid;
846
847 sc = device_get_softc(dev);
848 unit = device_get_unit(dev);
849 bzero(sc, sizeof(struct rl_softc));
850
851 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
852 MTX_DEF | MTX_RECURSE);
853 RL_LOCK(sc);
854
855 /*
856 * Handle power management nonsense.
857 */
858
859 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
860 u_int32_t iobase, membase, irq;
861
862 /* Save important PCI config data. */
863 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
864 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
865 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
866
867 /* Reset the power state. */
868 printf("rl%d: chip is is in D%d power mode "
869 "-- setting to D0\n", unit,
870 pci_get_powerstate(dev));
871
872 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
873
874 /* Restore PCI config data. */
875 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
876 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
877 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
878 }
879
880 /*
881 * Map control/status registers.
882 */
883 pci_enable_busmaster(dev);
884 pci_enable_io(dev, SYS_RES_IOPORT);
885 pci_enable_io(dev, SYS_RES_MEMORY);
886 command = pci_read_config(dev, PCIR_COMMAND, 4);
887
888#ifdef RL_USEIOSPACE
889 if (!(command & PCIM_CMD_PORTEN)) {
890 printf("rl%d: failed to enable I/O ports!\n", unit);
891 error = ENXIO;
892 goto fail;
893 }
894#else
895 if (!(command & PCIM_CMD_MEMEN)) {
896 printf("rl%d: failed to enable memory mapping!\n", unit);
897 error = ENXIO;
898 goto fail;
899 }
900#endif
901
902 rid = RL_RID;
903 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
904 0, ~0, 1, RF_ACTIVE);
905
906 if (sc->rl_res == NULL) {
907 printf ("rl%d: couldn't map ports/memory\n", unit);
908 error = ENXIO;
909 goto fail;
910 }
911
912 /* Detect the Realtek 8139B. For some reason, this chip is very
913 * unstable when left to autoselect the media
914 * The best workaround is to set the device to the required
915 * media type or to set it to the 10 Meg speed.
916 */
917
918 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) {
919 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit);
920 }
921
922 sc->rl_btag = rman_get_bustag(sc->rl_res);
923 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
924
925 rid = 0;
926 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
927 RF_SHAREABLE | RF_ACTIVE);
928
929 if (sc->rl_irq == NULL) {
930 printf("rl%d: couldn't map interrupt\n", unit);
931 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
932 error = ENXIO;
933 goto fail;
934 }
935
936 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
937 rl_intr, sc, &sc->rl_intrhand);
938
939 if (error) {
940 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
941 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
942 printf("rl%d: couldn't set up irq\n", unit);
943 goto fail;
944 }
945
946 callout_handle_init(&sc->rl_stat_ch);
947
948 /* Reset the adapter. */
949 rl_reset(sc);
950 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
951 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0);
952 if (rl_did != 0x8129)
953 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
954
955 /*
956 * Get station address from the EEPROM.
957 */
958 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
959
960 /*
961 * A RealTek chip was detected. Inform the world.
962 */
963 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
964
965 sc->rl_unit = unit;
966 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
967
968 /*
969 * Now read the exact device type from the EEPROM to find
970 * out if it's an 8129 or 8139.
971 */
972 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
973
974 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
975 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
| 157 { NORTEL_VENDORID, ACCTON_DEVICEID_5030,
158 "Nortel Networks 10/100BaseTX" },
159 { 0, 0, NULL }
160};
161
162static int rl_probe (device_t);
163static int rl_attach (device_t);
164static int rl_detach (device_t);
165
166static int rl_encap (struct rl_softc *, struct mbuf * );
167
168static void rl_rxeof (struct rl_softc *);
169static void rl_txeof (struct rl_softc *);
170static void rl_intr (void *);
171static void rl_tick (void *);
172static void rl_start (struct ifnet *);
173static int rl_ioctl (struct ifnet *, u_long, caddr_t);
174static void rl_init (void *);
175static void rl_stop (struct rl_softc *);
176static void rl_watchdog (struct ifnet *);
177static int rl_suspend (device_t);
178static int rl_resume (device_t);
179static void rl_shutdown (device_t);
180static int rl_ifmedia_upd (struct ifnet *);
181static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
182
183static void rl_eeprom_putbyte (struct rl_softc *, int);
184static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *);
185static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
186static void rl_mii_sync (struct rl_softc *);
187static void rl_mii_send (struct rl_softc *, u_int32_t, int);
188static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *);
189static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *);
190
191static int rl_miibus_readreg (device_t, int, int);
192static int rl_miibus_writereg (device_t, int, int, int);
193static void rl_miibus_statchg (device_t);
194
195static u_int8_t rl_calchash (caddr_t);
196static void rl_setmulti (struct rl_softc *);
197static void rl_reset (struct rl_softc *);
198static int rl_list_tx_init (struct rl_softc *);
199
200static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int);
201static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int);
202
203#ifdef RL_USEIOSPACE
204#define RL_RES SYS_RES_IOPORT
205#define RL_RID RL_PCI_LOIO
206#else
207#define RL_RES SYS_RES_MEMORY
208#define RL_RID RL_PCI_LOMEM
209#endif
210
211static device_method_t rl_methods[] = {
212 /* Device interface */
213 DEVMETHOD(device_probe, rl_probe),
214 DEVMETHOD(device_attach, rl_attach),
215 DEVMETHOD(device_detach, rl_detach),
216 DEVMETHOD(device_suspend, rl_suspend),
217 DEVMETHOD(device_resume, rl_resume),
218 DEVMETHOD(device_shutdown, rl_shutdown),
219
220 /* bus interface */
221 DEVMETHOD(bus_print_child, bus_generic_print_child),
222 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
223
224 /* MII interface */
225 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
226 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
227 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
228
229 { 0, 0 }
230};
231
232static driver_t rl_driver = {
233 "rl",
234 rl_methods,
235 sizeof(struct rl_softc)
236};
237
238static devclass_t rl_devclass;
239
240DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
241DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0);
242DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
243
244#define EE_SET(x) \
245 CSR_WRITE_1(sc, RL_EECMD, \
246 CSR_READ_1(sc, RL_EECMD) | x)
247
248#define EE_CLR(x) \
249 CSR_WRITE_1(sc, RL_EECMD, \
250 CSR_READ_1(sc, RL_EECMD) & ~x)
251
252static void
253rl_dma_map_rxbuf(arg, segs, nseg, error)
254 void *arg;
255 bus_dma_segment_t *segs;
256 int nseg, error;
257{
258 struct rl_softc *sc;
259
260 sc = arg;
261 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
262
263 return;
264}
265
266static void
267rl_dma_map_txbuf(arg, segs, nseg, error)
268 void *arg;
269 bus_dma_segment_t *segs;
270 int nseg, error;
271{
272 struct rl_softc *sc;
273
274 sc = arg;
275 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
276
277 return;
278}
279
280/*
281 * Send a read command and address to the EEPROM, check for ACK.
282 */
283static void rl_eeprom_putbyte(sc, addr)
284 struct rl_softc *sc;
285 int addr;
286{
287 register int d, i;
288
289 d = addr | sc->rl_eecmd_read;
290
291 /*
292 * Feed in each bit and strobe the clock.
293 */
294 for (i = 0x400; i; i >>= 1) {
295 if (d & i) {
296 EE_SET(RL_EE_DATAIN);
297 } else {
298 EE_CLR(RL_EE_DATAIN);
299 }
300 DELAY(100);
301 EE_SET(RL_EE_CLK);
302 DELAY(150);
303 EE_CLR(RL_EE_CLK);
304 DELAY(100);
305 }
306
307 return;
308}
309
310/*
311 * Read a word of data stored in the EEPROM at address 'addr.'
312 */
313static void rl_eeprom_getword(sc, addr, dest)
314 struct rl_softc *sc;
315 int addr;
316 u_int16_t *dest;
317{
318 register int i;
319 u_int16_t word = 0;
320
321 /* Enter EEPROM access mode. */
322 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
323
324 /*
325 * Send address of word we want to read.
326 */
327 rl_eeprom_putbyte(sc, addr);
328
329 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
330
331 /*
332 * Start reading bits from EEPROM.
333 */
334 for (i = 0x8000; i; i >>= 1) {
335 EE_SET(RL_EE_CLK);
336 DELAY(100);
337 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
338 word |= i;
339 EE_CLR(RL_EE_CLK);
340 DELAY(100);
341 }
342
343 /* Turn off EEPROM access mode. */
344 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
345
346 *dest = word;
347
348 return;
349}
350
351/*
352 * Read a sequence of words from the EEPROM.
353 */
354static void rl_read_eeprom(sc, dest, off, cnt, swap)
355 struct rl_softc *sc;
356 caddr_t dest;
357 int off;
358 int cnt;
359 int swap;
360{
361 int i;
362 u_int16_t word = 0, *ptr;
363
364 for (i = 0; i < cnt; i++) {
365 rl_eeprom_getword(sc, off + i, &word);
366 ptr = (u_int16_t *)(dest + (i * 2));
367 if (swap)
368 *ptr = ntohs(word);
369 else
370 *ptr = word;
371 }
372
373 return;
374}
375
376
377/*
378 * MII access routines are provided for the 8129, which
379 * doesn't have a built-in PHY. For the 8139, we fake things
380 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
381 * direct access PHY registers.
382 */
383#define MII_SET(x) \
384 CSR_WRITE_1(sc, RL_MII, \
385 CSR_READ_1(sc, RL_MII) | x)
386
387#define MII_CLR(x) \
388 CSR_WRITE_1(sc, RL_MII, \
389 CSR_READ_1(sc, RL_MII) & ~x)
390
391/*
392 * Sync the PHYs by setting data bit and strobing the clock 32 times.
393 */
394static void rl_mii_sync(sc)
395 struct rl_softc *sc;
396{
397 register int i;
398
399 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
400
401 for (i = 0; i < 32; i++) {
402 MII_SET(RL_MII_CLK);
403 DELAY(1);
404 MII_CLR(RL_MII_CLK);
405 DELAY(1);
406 }
407
408 return;
409}
410
411/*
412 * Clock a series of bits through the MII.
413 */
414static void rl_mii_send(sc, bits, cnt)
415 struct rl_softc *sc;
416 u_int32_t bits;
417 int cnt;
418{
419 int i;
420
421 MII_CLR(RL_MII_CLK);
422
423 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
424 if (bits & i) {
425 MII_SET(RL_MII_DATAOUT);
426 } else {
427 MII_CLR(RL_MII_DATAOUT);
428 }
429 DELAY(1);
430 MII_CLR(RL_MII_CLK);
431 DELAY(1);
432 MII_SET(RL_MII_CLK);
433 }
434}
435
436/*
437 * Read an PHY register through the MII.
438 */
439static int rl_mii_readreg(sc, frame)
440 struct rl_softc *sc;
441 struct rl_mii_frame *frame;
442
443{
444 int i, ack;
445
446 RL_LOCK(sc);
447
448 /*
449 * Set up frame for RX.
450 */
451 frame->mii_stdelim = RL_MII_STARTDELIM;
452 frame->mii_opcode = RL_MII_READOP;
453 frame->mii_turnaround = 0;
454 frame->mii_data = 0;
455
456 CSR_WRITE_2(sc, RL_MII, 0);
457
458 /*
459 * Turn on data xmit.
460 */
461 MII_SET(RL_MII_DIR);
462
463 rl_mii_sync(sc);
464
465 /*
466 * Send command/address info.
467 */
468 rl_mii_send(sc, frame->mii_stdelim, 2);
469 rl_mii_send(sc, frame->mii_opcode, 2);
470 rl_mii_send(sc, frame->mii_phyaddr, 5);
471 rl_mii_send(sc, frame->mii_regaddr, 5);
472
473 /* Idle bit */
474 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
475 DELAY(1);
476 MII_SET(RL_MII_CLK);
477 DELAY(1);
478
479 /* Turn off xmit. */
480 MII_CLR(RL_MII_DIR);
481
482 /* Check for ack */
483 MII_CLR(RL_MII_CLK);
484 DELAY(1);
485 MII_SET(RL_MII_CLK);
486 DELAY(1);
487 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
488
489 /*
490 * Now try reading data bits. If the ack failed, we still
491 * need to clock through 16 cycles to keep the PHY(s) in sync.
492 */
493 if (ack) {
494 for(i = 0; i < 16; i++) {
495 MII_CLR(RL_MII_CLK);
496 DELAY(1);
497 MII_SET(RL_MII_CLK);
498 DELAY(1);
499 }
500 goto fail;
501 }
502
503 for (i = 0x8000; i; i >>= 1) {
504 MII_CLR(RL_MII_CLK);
505 DELAY(1);
506 if (!ack) {
507 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
508 frame->mii_data |= i;
509 DELAY(1);
510 }
511 MII_SET(RL_MII_CLK);
512 DELAY(1);
513 }
514
515fail:
516
517 MII_CLR(RL_MII_CLK);
518 DELAY(1);
519 MII_SET(RL_MII_CLK);
520 DELAY(1);
521
522 RL_UNLOCK(sc);
523
524 if (ack)
525 return(1);
526 return(0);
527}
528
529/*
530 * Write to a PHY register through the MII.
531 */
532static int rl_mii_writereg(sc, frame)
533 struct rl_softc *sc;
534 struct rl_mii_frame *frame;
535
536{
537 RL_LOCK(sc);
538
539 /*
540 * Set up frame for TX.
541 */
542
543 frame->mii_stdelim = RL_MII_STARTDELIM;
544 frame->mii_opcode = RL_MII_WRITEOP;
545 frame->mii_turnaround = RL_MII_TURNAROUND;
546
547 /*
548 * Turn on data output.
549 */
550 MII_SET(RL_MII_DIR);
551
552 rl_mii_sync(sc);
553
554 rl_mii_send(sc, frame->mii_stdelim, 2);
555 rl_mii_send(sc, frame->mii_opcode, 2);
556 rl_mii_send(sc, frame->mii_phyaddr, 5);
557 rl_mii_send(sc, frame->mii_regaddr, 5);
558 rl_mii_send(sc, frame->mii_turnaround, 2);
559 rl_mii_send(sc, frame->mii_data, 16);
560
561 /* Idle bit. */
562 MII_SET(RL_MII_CLK);
563 DELAY(1);
564 MII_CLR(RL_MII_CLK);
565 DELAY(1);
566
567 /*
568 * Turn off xmit.
569 */
570 MII_CLR(RL_MII_DIR);
571
572 RL_UNLOCK(sc);
573
574 return(0);
575}
576
577static int rl_miibus_readreg(dev, phy, reg)
578 device_t dev;
579 int phy, reg;
580{
581 struct rl_softc *sc;
582 struct rl_mii_frame frame;
583 u_int16_t rval = 0;
584 u_int16_t rl8139_reg = 0;
585
586 sc = device_get_softc(dev);
587 RL_LOCK(sc);
588
589 if (sc->rl_type == RL_8139) {
590 /* Pretend the internal PHY is only at address 0 */
591 if (phy) {
592 RL_UNLOCK(sc);
593 return(0);
594 }
595 switch(reg) {
596 case MII_BMCR:
597 rl8139_reg = RL_BMCR;
598 break;
599 case MII_BMSR:
600 rl8139_reg = RL_BMSR;
601 break;
602 case MII_ANAR:
603 rl8139_reg = RL_ANAR;
604 break;
605 case MII_ANER:
606 rl8139_reg = RL_ANER;
607 break;
608 case MII_ANLPAR:
609 rl8139_reg = RL_LPAR;
610 break;
611 case MII_PHYIDR1:
612 case MII_PHYIDR2:
613 RL_UNLOCK(sc);
614 return(0);
615 break;
616 /*
617 * Allow the rlphy driver to read the media status
618 * register. If we have a link partner which does not
619 * support NWAY, this is the register which will tell
620 * us the results of parallel detection.
621 */
622 case RL_MEDIASTAT:
623 rval = CSR_READ_1(sc, RL_MEDIASTAT);
624 RL_UNLOCK(sc);
625 return(rval);
626 break;
627 default:
628 printf("rl%d: bad phy register\n", sc->rl_unit);
629 RL_UNLOCK(sc);
630 return(0);
631 }
632 rval = CSR_READ_2(sc, rl8139_reg);
633 RL_UNLOCK(sc);
634 return(rval);
635 }
636
637 bzero((char *)&frame, sizeof(frame));
638
639 frame.mii_phyaddr = phy;
640 frame.mii_regaddr = reg;
641 rl_mii_readreg(sc, &frame);
642 RL_UNLOCK(sc);
643
644 return(frame.mii_data);
645}
646
647static int rl_miibus_writereg(dev, phy, reg, data)
648 device_t dev;
649 int phy, reg, data;
650{
651 struct rl_softc *sc;
652 struct rl_mii_frame frame;
653 u_int16_t rl8139_reg = 0;
654
655 sc = device_get_softc(dev);
656 RL_LOCK(sc);
657
658 if (sc->rl_type == RL_8139) {
659 /* Pretend the internal PHY is only at address 0 */
660 if (phy) {
661 RL_UNLOCK(sc);
662 return(0);
663 }
664 switch(reg) {
665 case MII_BMCR:
666 rl8139_reg = RL_BMCR;
667 break;
668 case MII_BMSR:
669 rl8139_reg = RL_BMSR;
670 break;
671 case MII_ANAR:
672 rl8139_reg = RL_ANAR;
673 break;
674 case MII_ANER:
675 rl8139_reg = RL_ANER;
676 break;
677 case MII_ANLPAR:
678 rl8139_reg = RL_LPAR;
679 break;
680 case MII_PHYIDR1:
681 case MII_PHYIDR2:
682 RL_UNLOCK(sc);
683 return(0);
684 break;
685 default:
686 printf("rl%d: bad phy register\n", sc->rl_unit);
687 RL_UNLOCK(sc);
688 return(0);
689 }
690 CSR_WRITE_2(sc, rl8139_reg, data);
691 RL_UNLOCK(sc);
692 return(0);
693 }
694
695 bzero((char *)&frame, sizeof(frame));
696
697 frame.mii_phyaddr = phy;
698 frame.mii_regaddr = reg;
699 frame.mii_data = data;
700
701 rl_mii_writereg(sc, &frame);
702
703 RL_UNLOCK(sc);
704 return(0);
705}
706
707static void rl_miibus_statchg(dev)
708 device_t dev;
709{
710 return;
711}
712
713/*
714 * Calculate CRC of a multicast group address, return the upper 6 bits.
715 */
716static u_int8_t rl_calchash(addr)
717 caddr_t addr;
718{
719 u_int32_t crc, carry;
720 int i, j;
721 u_int8_t c;
722
723 /* Compute CRC for the address value. */
724 crc = 0xFFFFFFFF; /* initial value */
725
726 for (i = 0; i < 6; i++) {
727 c = *(addr + i);
728 for (j = 0; j < 8; j++) {
729 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
730 crc <<= 1;
731 c >>= 1;
732 if (carry)
733 crc = (crc ^ 0x04c11db6) | carry;
734 }
735 }
736
737 /* return the filter bit position */
738 return(crc >> 26);
739}
740
741/*
742 * Program the 64-bit multicast hash filter.
743 */
744static void rl_setmulti(sc)
745 struct rl_softc *sc;
746{
747 struct ifnet *ifp;
748 int h = 0;
749 u_int32_t hashes[2] = { 0, 0 };
750 struct ifmultiaddr *ifma;
751 u_int32_t rxfilt;
752 int mcnt = 0;
753
754 ifp = &sc->arpcom.ac_if;
755
756 rxfilt = CSR_READ_4(sc, RL_RXCFG);
757
758 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
759 rxfilt |= RL_RXCFG_RX_MULTI;
760 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
761 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
762 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
763 return;
764 }
765
766 /* first, zot all the existing hash bits */
767 CSR_WRITE_4(sc, RL_MAR0, 0);
768 CSR_WRITE_4(sc, RL_MAR4, 0);
769
770 /* now program new ones */
771 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
772 if (ifma->ifma_addr->sa_family != AF_LINK)
773 continue;
774 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
775 if (h < 32)
776 hashes[0] |= (1 << h);
777 else
778 hashes[1] |= (1 << (h - 32));
779 mcnt++;
780 }
781
782 if (mcnt)
783 rxfilt |= RL_RXCFG_RX_MULTI;
784 else
785 rxfilt &= ~RL_RXCFG_RX_MULTI;
786
787 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
788 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
789 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
790
791 return;
792}
793
794static void rl_reset(sc)
795 struct rl_softc *sc;
796{
797 register int i;
798
799 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
800
801 for (i = 0; i < RL_TIMEOUT; i++) {
802 DELAY(10);
803 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
804 break;
805 }
806 if (i == RL_TIMEOUT)
807 printf("rl%d: reset never completed!\n", sc->rl_unit);
808
809 return;
810}
811
812/*
813 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
814 * IDs against our list and return a device name if we find a match.
815 */
816static int rl_probe(dev)
817 device_t dev;
818{
819 struct rl_type *t;
820
821 t = rl_devs;
822
823 while(t->rl_name != NULL) {
824 if ((pci_get_vendor(dev) == t->rl_vid) &&
825 (pci_get_device(dev) == t->rl_did)) {
826 device_set_desc(dev, t->rl_name);
827 return(0);
828 }
829 t++;
830 }
831
832 return(ENXIO);
833}
834
835/*
836 * Attach the interface. Allocate softc structures, do ifmedia
837 * setup and ethernet/BPF attach.
838 */
839static int rl_attach(dev)
840 device_t dev;
841{
842 u_char eaddr[ETHER_ADDR_LEN];
843 u_int32_t command;
844 struct rl_softc *sc;
845 struct ifnet *ifp;
846 u_int16_t rl_did = 0;
847 int unit, error = 0, rid;
848
849 sc = device_get_softc(dev);
850 unit = device_get_unit(dev);
851 bzero(sc, sizeof(struct rl_softc));
852
853 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
854 MTX_DEF | MTX_RECURSE);
855 RL_LOCK(sc);
856
857 /*
858 * Handle power management nonsense.
859 */
860
861 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
862 u_int32_t iobase, membase, irq;
863
864 /* Save important PCI config data. */
865 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
866 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
867 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
868
869 /* Reset the power state. */
870 printf("rl%d: chip is is in D%d power mode "
871 "-- setting to D0\n", unit,
872 pci_get_powerstate(dev));
873
874 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
875
876 /* Restore PCI config data. */
877 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
878 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
879 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
880 }
881
882 /*
883 * Map control/status registers.
884 */
885 pci_enable_busmaster(dev);
886 pci_enable_io(dev, SYS_RES_IOPORT);
887 pci_enable_io(dev, SYS_RES_MEMORY);
888 command = pci_read_config(dev, PCIR_COMMAND, 4);
889
890#ifdef RL_USEIOSPACE
891 if (!(command & PCIM_CMD_PORTEN)) {
892 printf("rl%d: failed to enable I/O ports!\n", unit);
893 error = ENXIO;
894 goto fail;
895 }
896#else
897 if (!(command & PCIM_CMD_MEMEN)) {
898 printf("rl%d: failed to enable memory mapping!\n", unit);
899 error = ENXIO;
900 goto fail;
901 }
902#endif
903
904 rid = RL_RID;
905 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid,
906 0, ~0, 1, RF_ACTIVE);
907
908 if (sc->rl_res == NULL) {
909 printf ("rl%d: couldn't map ports/memory\n", unit);
910 error = ENXIO;
911 goto fail;
912 }
913
914 /* Detect the Realtek 8139B. For some reason, this chip is very
915 * unstable when left to autoselect the media
916 * The best workaround is to set the device to the required
917 * media type or to set it to the 10 Meg speed.
918 */
919
920 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) {
921 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit);
922 }
923
924 sc->rl_btag = rman_get_bustag(sc->rl_res);
925 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
926
927 rid = 0;
928 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
929 RF_SHAREABLE | RF_ACTIVE);
930
931 if (sc->rl_irq == NULL) {
932 printf("rl%d: couldn't map interrupt\n", unit);
933 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
934 error = ENXIO;
935 goto fail;
936 }
937
938 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET,
939 rl_intr, sc, &sc->rl_intrhand);
940
941 if (error) {
942 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
943 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
944 printf("rl%d: couldn't set up irq\n", unit);
945 goto fail;
946 }
947
948 callout_handle_init(&sc->rl_stat_ch);
949
950 /* Reset the adapter. */
951 rl_reset(sc);
952 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
953 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0);
954 if (rl_did != 0x8129)
955 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
956
957 /*
958 * Get station address from the EEPROM.
959 */
960 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0);
961
962 /*
963 * A RealTek chip was detected. Inform the world.
964 */
965 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":");
966
967 sc->rl_unit = unit;
968 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
969
970 /*
971 * Now read the exact device type from the EEPROM to find
972 * out if it's an 8129 or 8139.
973 */
974 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
975
976 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
977 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
|
976 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS)
| 978 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS ||
979 rl_did == DLINK_DEVICEID_690TXD)
|
977 sc->rl_type = RL_8139;
978 else if (rl_did == RT_DEVICEID_8129)
979 sc->rl_type = RL_8129;
980 else {
981 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
982 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
983 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
984 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
985 error = ENXIO;
986 goto fail;
987 }
988
989 /*
990 * Allocate the parent bus DMA tag appropriate for PCI.
991 */
992#define RL_NSEG_NEW 32
993 error = bus_dma_tag_create(NULL, /* parent */
994 1, 0, /* alignment, boundary */
995 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
996 BUS_SPACE_MAXADDR, /* highaddr */
997 NULL, NULL, /* filter, filterarg */
998 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
999 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1000 BUS_DMA_ALLOCNOW, /* flags */
1001 &sc->rl_parent_tag);
1002
1003 /*
1004 * Now allocate a tag for the DMA descriptor lists.
1005 * All of our lists are allocated as a contiguous block
1006 * of memory.
1007 */
1008 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
1009 1, 0, /* alignment, boundary */
1010 BUS_SPACE_MAXADDR, /* lowaddr */
1011 BUS_SPACE_MAXADDR, /* highaddr */
1012 NULL, NULL, /* filter, filterarg */
1013 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
1014 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1015 0, /* flags */
1016 &sc->rl_tag);
1017
1018 /*
1019 * Now allocate a chunk of DMA-able memory based on the
1020 * tag we just created.
1021 */
1022 error = bus_dmamem_alloc(sc->rl_tag,
1023 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT,
1024 &sc->rl_cdata.rl_rx_dmamap);
1025
1026 if (sc->rl_cdata.rl_rx_buf == NULL) {
1027 printf("rl%d: no memory for list buffers!\n", unit);
1028 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1029 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1030 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1031 bus_dma_tag_destroy(sc->rl_tag);
1032 error = ENXIO;
1033 goto fail;
1034 }
1035
1036 /* Leave a few bytes before the start of the RX ring buffer. */
1037 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1038 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
1039
1040 /* Do MII setup */
1041 if (mii_phy_probe(dev, &sc->rl_miibus,
1042 rl_ifmedia_upd, rl_ifmedia_sts)) {
1043 printf("rl%d: MII without any phy!\n", sc->rl_unit);
1044 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1045 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1046 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1047 bus_dmamem_free(sc->rl_tag,
1048 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap);
1049 bus_dma_tag_destroy(sc->rl_tag);
1050 error = ENXIO;
1051 goto fail;
1052 }
1053
1054 ifp = &sc->arpcom.ac_if;
1055 ifp->if_softc = sc;
1056 ifp->if_unit = unit;
1057 ifp->if_name = "rl";
1058 ifp->if_mtu = ETHERMTU;
1059 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1060 ifp->if_ioctl = rl_ioctl;
1061 ifp->if_output = ether_output;
1062 ifp->if_start = rl_start;
1063 ifp->if_watchdog = rl_watchdog;
1064 ifp->if_init = rl_init;
1065 ifp->if_baudrate = 10000000;
1066 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1067
1068 /*
1069 * Call MI attach routine.
1070 */
1071 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1072 RL_UNLOCK(sc);
1073 return(0);
1074
1075fail:
1076 RL_UNLOCK(sc);
1077 mtx_destroy(&sc->rl_mtx);
1078 return(error);
1079}
1080
1081static int rl_detach(dev)
1082 device_t dev;
1083{
1084 struct rl_softc *sc;
1085 struct ifnet *ifp;
1086
1087 sc = device_get_softc(dev);
1088 RL_LOCK(sc);
1089 ifp = &sc->arpcom.ac_if;
1090
1091 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1092 rl_stop(sc);
1093
1094 bus_generic_detach(dev);
1095 device_delete_child(dev, sc->rl_miibus);
1096
1097 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1098 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1099 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1100
1101 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1102 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1103 sc->rl_cdata.rl_rx_dmamap);
1104 bus_dma_tag_destroy(sc->rl_tag);
1105 bus_dma_tag_destroy(sc->rl_parent_tag);
1106
1107 RL_UNLOCK(sc);
1108 mtx_destroy(&sc->rl_mtx);
1109
1110 return(0);
1111}
1112
1113/*
1114 * Initialize the transmit descriptors.
1115 */
1116static int rl_list_tx_init(sc)
1117 struct rl_softc *sc;
1118{
1119 struct rl_chain_data *cd;
1120 int i;
1121
1122 cd = &sc->rl_cdata;
1123 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1124 cd->rl_tx_chain[i] = NULL;
1125 CSR_WRITE_4(sc,
1126 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
1127 }
1128
1129 sc->rl_cdata.cur_tx = 0;
1130 sc->rl_cdata.last_tx = 0;
1131
1132 return(0);
1133}
1134
1135/*
1136 * A frame has been uploaded: pass the resulting mbuf chain up to
1137 * the higher level protocols.
1138 *
1139 * You know there's something wrong with a PCI bus-master chip design
1140 * when you have to use m_devget().
1141 *
1142 * The receive operation is badly documented in the datasheet, so I'll
1143 * attempt to document it here. The driver provides a buffer area and
1144 * places its base address in the RX buffer start address register.
1145 * The chip then begins copying frames into the RX buffer. Each frame
1146 * is preceded by a 32-bit RX status word which specifies the length
1147 * of the frame and certain other status bits. Each frame (starting with
1148 * the status word) is also 32-bit aligned. The frame length is in the
1149 * first 16 bits of the status word; the lower 15 bits correspond with
1150 * the 'rx status register' mentioned in the datasheet.
1151 *
1152 * Note: to make the Alpha happy, the frame payload needs to be aligned
1153 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1154 * as the offset argument to m_devget().
1155 */
1156static void rl_rxeof(sc)
1157 struct rl_softc *sc;
1158{
1159 struct ether_header *eh;
1160 struct mbuf *m;
1161 struct ifnet *ifp;
1162 int total_len = 0;
1163 u_int32_t rxstat;
1164 caddr_t rxbufpos;
1165 int wrap = 0;
1166 u_int16_t cur_rx;
1167 u_int16_t limit;
1168 u_int16_t rx_bytes = 0, max_bytes;
1169
1170 ifp = &sc->arpcom.ac_if;
1171
1172 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1173 BUS_DMASYNC_POSTWRITE);
1174
1175 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1176
1177 /* Do not try to read past this point. */
1178 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1179
1180 if (limit < cur_rx)
1181 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1182 else
1183 max_bytes = limit - cur_rx;
1184
1185 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1186#ifdef DEVICE_POLLING
1187 if (ifp->if_ipending & IFF_POLLING) {
1188 if (sc->rxcycles <= 0)
1189 break;
1190 sc->rxcycles--;
1191 }
1192#endif /* DEVICE_POLLING */
1193 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1194 rxstat = *(u_int32_t *)rxbufpos;
1195
1196 /*
1197 * Here's a totally undocumented fact for you. When the
1198 * RealTek chip is in the process of copying a packet into
1199 * RAM for you, the length will be 0xfff0. If you spot a
1200 * packet header with this value, you need to stop. The
1201 * datasheet makes absolutely no mention of this and
1202 * RealTek should be shot for this.
1203 */
1204 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1205 break;
1206
1207 if (!(rxstat & RL_RXSTAT_RXOK)) {
1208 ifp->if_ierrors++;
1209 rl_init(sc);
1210 return;
1211 }
1212
1213 /* No errors; receive the packet. */
1214 total_len = rxstat >> 16;
1215 rx_bytes += total_len + 4;
1216
1217 /*
1218 * XXX The RealTek chip includes the CRC with every
1219 * received frame, and there's no way to turn this
1220 * behavior off (at least, I can't find anything in
1221 * the manual that explains how to do it) so we have
1222 * to trim off the CRC manually.
1223 */
1224 total_len -= ETHER_CRC_LEN;
1225
1226 /*
1227 * Avoid trying to read more bytes than we know
1228 * the chip has prepared for us.
1229 */
1230 if (rx_bytes > max_bytes)
1231 break;
1232
1233 rxbufpos = sc->rl_cdata.rl_rx_buf +
1234 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1235
1236 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1237 rxbufpos = sc->rl_cdata.rl_rx_buf;
1238
1239 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1240
1241 if (total_len > wrap) {
1242 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1243 NULL);
1244 if (m == NULL) {
1245 ifp->if_ierrors++;
1246 } else {
1247 m_copyback(m, wrap, total_len - wrap,
1248 sc->rl_cdata.rl_rx_buf);
1249 }
1250 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1251 } else {
1252 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1253 NULL);
1254 if (m == NULL) {
1255 ifp->if_ierrors++;
1256 }
1257 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1258 }
1259
1260 /*
1261 * Round up to 32-bit boundary.
1262 */
1263 cur_rx = (cur_rx + 3) & ~3;
1264 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1265
1266 if (m == NULL)
1267 continue;
1268
1269 eh = mtod(m, struct ether_header *);
1270 ifp->if_ipackets++;
1271
1272 /* Remove header from mbuf and pass it on. */
1273 m_adj(m, sizeof(struct ether_header));
1274 ether_input(ifp, eh, m);
1275 }
1276
1277 return;
1278}
1279
1280/*
1281 * A frame was downloaded to the chip. It's safe for us to clean up
1282 * the list buffers.
1283 */
1284static void rl_txeof(sc)
1285 struct rl_softc *sc;
1286{
1287 struct ifnet *ifp;
1288 u_int32_t txstat;
1289
1290 ifp = &sc->arpcom.ac_if;
1291
1292 /* Clear the timeout timer. */
1293 ifp->if_timer = 0;
1294
1295 /*
1296 * Go through our tx list and free mbufs for those
1297 * frames that have been uploaded.
1298 */
1299 do {
1300 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1301 if (!(txstat & (RL_TXSTAT_TX_OK|
1302 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1303 break;
1304
1305 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1306
1307 if (RL_LAST_TXMBUF(sc) != NULL) {
1308 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1309 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1310 m_freem(RL_LAST_TXMBUF(sc));
1311 RL_LAST_TXMBUF(sc) = NULL;
1312 }
1313 if (txstat & RL_TXSTAT_TX_OK)
1314 ifp->if_opackets++;
1315 else {
1316 int oldthresh;
1317 ifp->if_oerrors++;
1318 if ((txstat & RL_TXSTAT_TXABRT) ||
1319 (txstat & RL_TXSTAT_OUTOFWIN))
1320 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1321 oldthresh = sc->rl_txthresh;
1322 /* error recovery */
1323 rl_reset(sc);
1324 rl_init(sc);
1325 /*
1326 * If there was a transmit underrun,
1327 * bump the TX threshold.
1328 */
1329 if (txstat & RL_TXSTAT_TX_UNDERRUN)
1330 sc->rl_txthresh = oldthresh + 32;
1331 return;
1332 }
1333 RL_INC(sc->rl_cdata.last_tx);
1334 ifp->if_flags &= ~IFF_OACTIVE;
1335 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1336
1337 return;
1338}
1339
1340static void rl_tick(xsc)
1341 void *xsc;
1342{
1343 struct rl_softc *sc;
1344 struct mii_data *mii;
1345
1346 sc = xsc;
1347 RL_LOCK(sc);
1348 mii = device_get_softc(sc->rl_miibus);
1349
1350 mii_tick(mii);
1351
1352 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1353 RL_UNLOCK(sc);
1354
1355 return;
1356}
1357
1358#ifdef DEVICE_POLLING
1359static void
1360rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1361{
1362 struct rl_softc *sc = ifp->if_softc;
1363
1364 RL_LOCK(sc);
1365 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1366 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1367 goto done;
1368 }
1369
1370 sc->rxcycles = count;
1371 rl_rxeof(sc);
1372 rl_txeof(sc);
1373 if (ifp->if_snd.ifq_head != NULL)
1374 rl_start(ifp);
1375
1376 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1377 u_int16_t status;
1378
1379 status = CSR_READ_2(sc, RL_ISR);
1380 if (status)
1381 CSR_WRITE_2(sc, RL_ISR, status);
1382
1383 /*
1384 * XXX check behaviour on receiver stalls.
1385 */
1386
1387 if (status & RL_ISR_SYSTEM_ERR) {
1388 rl_reset(sc);
1389 rl_init(sc);
1390 }
1391 }
1392done:
1393 RL_UNLOCK(sc);
1394}
1395#endif /* DEVICE_POLLING */
1396
1397static void rl_intr(arg)
1398 void *arg;
1399{
1400 struct rl_softc *sc;
1401 struct ifnet *ifp;
1402 u_int16_t status;
1403
1404 sc = arg;
1405
1406 if (sc->suspended) {
1407 return;
1408 }
1409
1410 RL_LOCK(sc);
1411 ifp = &sc->arpcom.ac_if;
1412
1413#ifdef DEVICE_POLLING
1414 if (ifp->if_ipending & IFF_POLLING)
1415 goto done;
1416 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
1417 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1418 rl_poll(ifp, 0, 1);
1419 goto done;
1420 }
1421#endif /* DEVICE_POLLING */
1422
1423 for (;;) {
1424
1425 status = CSR_READ_2(sc, RL_ISR);
1426 if (status)
1427 CSR_WRITE_2(sc, RL_ISR, status);
1428
1429 if ((status & RL_INTRS) == 0)
1430 break;
1431
1432 if (status & RL_ISR_RX_OK)
1433 rl_rxeof(sc);
1434
1435 if (status & RL_ISR_RX_ERR)
1436 rl_rxeof(sc);
1437
1438 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1439 rl_txeof(sc);
1440
1441 if (status & RL_ISR_SYSTEM_ERR) {
1442 rl_reset(sc);
1443 rl_init(sc);
1444 }
1445
1446 }
1447
1448 if (ifp->if_snd.ifq_head != NULL)
1449 rl_start(ifp);
1450
1451#ifdef DEVICE_POLLING
1452done:
1453#endif
1454 RL_UNLOCK(sc);
1455
1456 return;
1457}
1458
1459/*
1460 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1461 * pointers to the fragment pointers.
1462 */
1463static int rl_encap(sc, m_head)
1464 struct rl_softc *sc;
1465 struct mbuf *m_head;
1466{
1467 struct mbuf *m_new = NULL;
1468
1469 /*
1470 * The RealTek is brain damaged and wants longword-aligned
1471 * TX buffers, plus we can only have one fragment buffer
1472 * per packet. We have to copy pretty much all the time.
1473 */
1474
1475 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1476 if (m_new == NULL)
1477 return(1);
1478 if (m_head->m_pkthdr.len > MHLEN) {
1479 MCLGET(m_new, M_DONTWAIT);
1480 if (!(m_new->m_flags & M_EXT)) {
1481 m_freem(m_new);
1482 return(1);
1483 }
1484 }
1485 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1486 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1487 m_freem(m_head);
1488 m_head = m_new;
1489
1490 /* Pad frames to at least 60 bytes. */
1491 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1492 /*
1493 * Make security concious people happy: zero out the
1494 * bytes in the pad area, since we don't know what
1495 * this mbuf cluster buffer's previous user might
1496 * have left in it.
1497 */
1498 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1499 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1500 m_head->m_pkthdr.len +=
1501 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1502 m_head->m_len = m_head->m_pkthdr.len;
1503 }
1504
1505 RL_CUR_TXMBUF(sc) = m_head;
1506
1507 return(0);
1508}
1509
1510/*
1511 * Main transmit routine.
1512 */
1513
1514static void rl_start(ifp)
1515 struct ifnet *ifp;
1516{
1517 struct rl_softc *sc;
1518 struct mbuf *m_head = NULL;
1519
1520 sc = ifp->if_softc;
1521 RL_LOCK(sc);
1522
1523 while(RL_CUR_TXMBUF(sc) == NULL) {
1524 IF_DEQUEUE(&ifp->if_snd, m_head);
1525 if (m_head == NULL)
1526 break;
1527
1528 if (rl_encap(sc, m_head)) {
1529 IF_PREPEND(&ifp->if_snd, m_head);
1530 ifp->if_flags |= IFF_OACTIVE;
1531 break;
1532 }
1533
1534 /*
1535 * If there's a BPF listener, bounce a copy of this frame
1536 * to him.
1537 */
1538 if (ifp->if_bpf)
1539 bpf_mtap(ifp, RL_CUR_TXMBUF(sc));
1540
1541 /*
1542 * Transmit the frame.
1543 */
1544 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1545 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1546 mtod(RL_CUR_TXMBUF(sc), void *),
1547 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1548 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1549 BUS_DMASYNC_PREREAD);
1550 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1551 RL_TXTHRESH(sc->rl_txthresh) |
1552 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1553
1554 RL_INC(sc->rl_cdata.cur_tx);
1555 }
1556
1557 /*
1558 * We broke out of the loop because all our TX slots are
1559 * full. Mark the NIC as busy until it drains some of the
1560 * packets from the queue.
1561 */
1562 if (RL_CUR_TXMBUF(sc) != NULL)
1563 ifp->if_flags |= IFF_OACTIVE;
1564
1565 /*
1566 * Set a timeout in case the chip goes out to lunch.
1567 */
1568 ifp->if_timer = 5;
1569 RL_UNLOCK(sc);
1570
1571 return;
1572}
1573
1574static void rl_init(xsc)
1575 void *xsc;
1576{
1577 struct rl_softc *sc = xsc;
1578 struct ifnet *ifp = &sc->arpcom.ac_if;
1579 struct mii_data *mii;
1580 int i;
1581 u_int32_t rxcfg = 0;
1582
1583 RL_LOCK(sc);
1584 mii = device_get_softc(sc->rl_miibus);
1585
1586 /*
1587 * Cancel pending I/O and free all RX/TX buffers.
1588 */
1589 rl_stop(sc);
1590
1591 /* Init our MAC address */
1592 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1593 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1594 }
1595
1596 /* Init the RX buffer pointer register. */
1597 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1598 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1599 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1600 BUS_DMASYNC_PREWRITE);
1601
1602 /* Init TX descriptors. */
1603 rl_list_tx_init(sc);
1604
1605 /*
1606 * Enable transmit and receive.
1607 */
1608 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1609
1610 /*
1611 * Set the initial TX and RX configuration.
1612 */
1613 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1614 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1615
1616 /* Set the individual bit to receive frames for this host only. */
1617 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1618 rxcfg |= RL_RXCFG_RX_INDIV;
1619
1620 /* If we want promiscuous mode, set the allframes bit. */
1621 if (ifp->if_flags & IFF_PROMISC) {
1622 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1623 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1624 } else {
1625 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1626 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1627 }
1628
1629 /*
1630 * Set capture broadcast bit to capture broadcast frames.
1631 */
1632 if (ifp->if_flags & IFF_BROADCAST) {
1633 rxcfg |= RL_RXCFG_RX_BROAD;
1634 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1635 } else {
1636 rxcfg &= ~RL_RXCFG_RX_BROAD;
1637 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1638 }
1639
1640 /*
1641 * Program the multicast filter, if necessary.
1642 */
1643 rl_setmulti(sc);
1644
1645#ifdef DEVICE_POLLING
1646 /*
1647 * Disable interrupts if we are polling.
1648 */
1649 if (ifp->if_ipending & IFF_POLLING)
1650 CSR_WRITE_2(sc, RL_IMR, 0);
1651 else /* otherwise ... */
1652#endif /* DEVICE_POLLING */
1653 /*
1654 * Enable interrupts.
1655 */
1656 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1657
1658 /* Set initial TX threshold */
1659 sc->rl_txthresh = RL_TX_THRESH_INIT;
1660
1661 /* Start RX/TX process. */
1662 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1663
1664 /* Enable receiver and transmitter. */
1665 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1666
1667 mii_mediachg(mii);
1668
1669 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1670
1671 ifp->if_flags |= IFF_RUNNING;
1672 ifp->if_flags &= ~IFF_OACTIVE;
1673
1674 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1675 RL_UNLOCK(sc);
1676
1677 return;
1678}
1679
1680/*
1681 * Set media options.
1682 */
1683static int rl_ifmedia_upd(ifp)
1684 struct ifnet *ifp;
1685{
1686 struct rl_softc *sc;
1687 struct mii_data *mii;
1688
1689 sc = ifp->if_softc;
1690 mii = device_get_softc(sc->rl_miibus);
1691 mii_mediachg(mii);
1692
1693 return(0);
1694}
1695
1696/*
1697 * Report current media status.
1698 */
1699static void rl_ifmedia_sts(ifp, ifmr)
1700 struct ifnet *ifp;
1701 struct ifmediareq *ifmr;
1702{
1703 struct rl_softc *sc;
1704 struct mii_data *mii;
1705
1706 sc = ifp->if_softc;
1707 mii = device_get_softc(sc->rl_miibus);
1708
1709 mii_pollstat(mii);
1710 ifmr->ifm_active = mii->mii_media_active;
1711 ifmr->ifm_status = mii->mii_media_status;
1712
1713 return;
1714}
1715
1716static int rl_ioctl(ifp, command, data)
1717 struct ifnet *ifp;
1718 u_long command;
1719 caddr_t data;
1720{
1721 struct rl_softc *sc = ifp->if_softc;
1722 struct ifreq *ifr = (struct ifreq *) data;
1723 struct mii_data *mii;
1724 int error = 0;
1725
1726 RL_LOCK(sc);
1727
1728 switch(command) {
1729 case SIOCSIFADDR:
1730 case SIOCGIFADDR:
1731 case SIOCSIFMTU:
1732 error = ether_ioctl(ifp, command, data);
1733 break;
1734 case SIOCSIFFLAGS:
1735 if (ifp->if_flags & IFF_UP) {
1736 rl_init(sc);
1737 } else {
1738 if (ifp->if_flags & IFF_RUNNING)
1739 rl_stop(sc);
1740 }
1741 error = 0;
1742 break;
1743 case SIOCADDMULTI:
1744 case SIOCDELMULTI:
1745 rl_setmulti(sc);
1746 error = 0;
1747 break;
1748 case SIOCGIFMEDIA:
1749 case SIOCSIFMEDIA:
1750 mii = device_get_softc(sc->rl_miibus);
1751 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1752 break;
1753 default:
1754 error = EINVAL;
1755 break;
1756 }
1757
1758 RL_UNLOCK(sc);
1759
1760 return(error);
1761}
1762
1763static void rl_watchdog(ifp)
1764 struct ifnet *ifp;
1765{
1766 struct rl_softc *sc;
1767
1768 sc = ifp->if_softc;
1769 RL_LOCK(sc);
1770 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1771 ifp->if_oerrors++;
1772
1773 rl_txeof(sc);
1774 rl_rxeof(sc);
1775 rl_init(sc);
1776 RL_UNLOCK(sc);
1777
1778 return;
1779}
1780
1781/*
1782 * Stop the adapter and free any mbufs allocated to the
1783 * RX and TX lists.
1784 */
1785static void rl_stop(sc)
1786 struct rl_softc *sc;
1787{
1788 register int i;
1789 struct ifnet *ifp;
1790
1791 RL_LOCK(sc);
1792 ifp = &sc->arpcom.ac_if;
1793 ifp->if_timer = 0;
1794
1795 untimeout(rl_tick, sc, sc->rl_stat_ch);
1796 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1797#ifdef DEVICE_POLLING
1798 ether_poll_deregister(ifp);
1799#endif /* DEVICE_POLLING */
1800
1801 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1802 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1803 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1804
1805 /*
1806 * Free the TX list buffers.
1807 */
1808 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1809 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1810 bus_dmamap_unload(sc->rl_tag,
1811 sc->rl_cdata.rl_tx_dmamap[i]);
1812 bus_dmamap_destroy(sc->rl_tag,
1813 sc->rl_cdata.rl_tx_dmamap[i]);
1814 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1815 sc->rl_cdata.rl_tx_chain[i] = NULL;
1816 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1817 }
1818 }
1819
1820 RL_UNLOCK(sc);
1821 return;
1822}
1823
1824/*
1825 * Device suspend routine. Stop the interface and save some PCI
1826 * settings in case the BIOS doesn't restore them properly on
1827 * resume.
1828 */
1829static int rl_suspend(dev)
1830 device_t dev;
1831{
1832 register int i;
1833 struct rl_softc *sc;
1834
1835 sc = device_get_softc(dev);
1836
1837 rl_stop(sc);
1838
1839 for (i = 0; i < 5; i++)
1840 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
1841 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1842 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1843 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1844 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1845
1846 sc->suspended = 1;
1847
1848 return (0);
1849}
1850
1851/*
1852 * Device resume routine. Restore some PCI settings in case the BIOS
1853 * doesn't, re-enable busmastering, and restart the interface if
1854 * appropriate.
1855 */
1856static int rl_resume(dev)
1857 device_t dev;
1858{
1859 register int i;
1860 struct rl_softc *sc;
1861 struct ifnet *ifp;
1862
1863 sc = device_get_softc(dev);
1864 ifp = &sc->arpcom.ac_if;
1865
1866 /* better way to do this? */
1867 for (i = 0; i < 5; i++)
1868 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
1869 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1870 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1871 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1872 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1873
1874 /* reenable busmastering */
1875 pci_enable_busmaster(dev);
1876 pci_enable_io(dev, RL_RES);
1877
1878 /* reinitialize interface if necessary */
1879 if (ifp->if_flags & IFF_UP)
1880 rl_init(sc);
1881
1882 sc->suspended = 0;
1883
1884 return (0);
1885}
1886
1887/*
1888 * Stop all chip I/O so that the kernel's probe routines don't
1889 * get confused by errant DMAs when rebooting.
1890 */
1891static void rl_shutdown(dev)
1892 device_t dev;
1893{
1894 struct rl_softc *sc;
1895
1896 sc = device_get_softc(dev);
1897
1898 rl_stop(sc);
1899
1900 return;
1901}
| 980 sc->rl_type = RL_8139;
981 else if (rl_did == RT_DEVICEID_8129)
982 sc->rl_type = RL_8129;
983 else {
984 printf("rl%d: unknown device ID: %x\n", unit, rl_did);
985 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
986 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
987 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
988 error = ENXIO;
989 goto fail;
990 }
991
992 /*
993 * Allocate the parent bus DMA tag appropriate for PCI.
994 */
995#define RL_NSEG_NEW 32
996 error = bus_dma_tag_create(NULL, /* parent */
997 1, 0, /* alignment, boundary */
998 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
999 BUS_SPACE_MAXADDR, /* highaddr */
1000 NULL, NULL, /* filter, filterarg */
1001 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
1002 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1003 BUS_DMA_ALLOCNOW, /* flags */
1004 &sc->rl_parent_tag);
1005
1006 /*
1007 * Now allocate a tag for the DMA descriptor lists.
1008 * All of our lists are allocated as a contiguous block
1009 * of memory.
1010 */
1011 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
1012 1, 0, /* alignment, boundary */
1013 BUS_SPACE_MAXADDR, /* lowaddr */
1014 BUS_SPACE_MAXADDR, /* highaddr */
1015 NULL, NULL, /* filter, filterarg */
1016 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
1017 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1018 0, /* flags */
1019 &sc->rl_tag);
1020
1021 /*
1022 * Now allocate a chunk of DMA-able memory based on the
1023 * tag we just created.
1024 */
1025 error = bus_dmamem_alloc(sc->rl_tag,
1026 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT,
1027 &sc->rl_cdata.rl_rx_dmamap);
1028
1029 if (sc->rl_cdata.rl_rx_buf == NULL) {
1030 printf("rl%d: no memory for list buffers!\n", unit);
1031 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1032 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1033 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1034 bus_dma_tag_destroy(sc->rl_tag);
1035 error = ENXIO;
1036 goto fail;
1037 }
1038
1039 /* Leave a few bytes before the start of the RX ring buffer. */
1040 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1041 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
1042
1043 /* Do MII setup */
1044 if (mii_phy_probe(dev, &sc->rl_miibus,
1045 rl_ifmedia_upd, rl_ifmedia_sts)) {
1046 printf("rl%d: MII without any phy!\n", sc->rl_unit);
1047 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1048 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1049 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1050 bus_dmamem_free(sc->rl_tag,
1051 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap);
1052 bus_dma_tag_destroy(sc->rl_tag);
1053 error = ENXIO;
1054 goto fail;
1055 }
1056
1057 ifp = &sc->arpcom.ac_if;
1058 ifp->if_softc = sc;
1059 ifp->if_unit = unit;
1060 ifp->if_name = "rl";
1061 ifp->if_mtu = ETHERMTU;
1062 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1063 ifp->if_ioctl = rl_ioctl;
1064 ifp->if_output = ether_output;
1065 ifp->if_start = rl_start;
1066 ifp->if_watchdog = rl_watchdog;
1067 ifp->if_init = rl_init;
1068 ifp->if_baudrate = 10000000;
1069 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1070
1071 /*
1072 * Call MI attach routine.
1073 */
1074 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1075 RL_UNLOCK(sc);
1076 return(0);
1077
1078fail:
1079 RL_UNLOCK(sc);
1080 mtx_destroy(&sc->rl_mtx);
1081 return(error);
1082}
1083
1084static int rl_detach(dev)
1085 device_t dev;
1086{
1087 struct rl_softc *sc;
1088 struct ifnet *ifp;
1089
1090 sc = device_get_softc(dev);
1091 RL_LOCK(sc);
1092 ifp = &sc->arpcom.ac_if;
1093
1094 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1095 rl_stop(sc);
1096
1097 bus_generic_detach(dev);
1098 device_delete_child(dev, sc->rl_miibus);
1099
1100 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1101 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1102 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1103
1104 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1105 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1106 sc->rl_cdata.rl_rx_dmamap);
1107 bus_dma_tag_destroy(sc->rl_tag);
1108 bus_dma_tag_destroy(sc->rl_parent_tag);
1109
1110 RL_UNLOCK(sc);
1111 mtx_destroy(&sc->rl_mtx);
1112
1113 return(0);
1114}
1115
1116/*
1117 * Initialize the transmit descriptors.
1118 */
1119static int rl_list_tx_init(sc)
1120 struct rl_softc *sc;
1121{
1122 struct rl_chain_data *cd;
1123 int i;
1124
1125 cd = &sc->rl_cdata;
1126 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1127 cd->rl_tx_chain[i] = NULL;
1128 CSR_WRITE_4(sc,
1129 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000);
1130 }
1131
1132 sc->rl_cdata.cur_tx = 0;
1133 sc->rl_cdata.last_tx = 0;
1134
1135 return(0);
1136}
1137
1138/*
1139 * A frame has been uploaded: pass the resulting mbuf chain up to
1140 * the higher level protocols.
1141 *
1142 * You know there's something wrong with a PCI bus-master chip design
1143 * when you have to use m_devget().
1144 *
1145 * The receive operation is badly documented in the datasheet, so I'll
1146 * attempt to document it here. The driver provides a buffer area and
1147 * places its base address in the RX buffer start address register.
1148 * The chip then begins copying frames into the RX buffer. Each frame
1149 * is preceded by a 32-bit RX status word which specifies the length
1150 * of the frame and certain other status bits. Each frame (starting with
1151 * the status word) is also 32-bit aligned. The frame length is in the
1152 * first 16 bits of the status word; the lower 15 bits correspond with
1153 * the 'rx status register' mentioned in the datasheet.
1154 *
1155 * Note: to make the Alpha happy, the frame payload needs to be aligned
1156 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1157 * as the offset argument to m_devget().
1158 */
1159static void rl_rxeof(sc)
1160 struct rl_softc *sc;
1161{
1162 struct ether_header *eh;
1163 struct mbuf *m;
1164 struct ifnet *ifp;
1165 int total_len = 0;
1166 u_int32_t rxstat;
1167 caddr_t rxbufpos;
1168 int wrap = 0;
1169 u_int16_t cur_rx;
1170 u_int16_t limit;
1171 u_int16_t rx_bytes = 0, max_bytes;
1172
1173 ifp = &sc->arpcom.ac_if;
1174
1175 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1176 BUS_DMASYNC_POSTWRITE);
1177
1178 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1179
1180 /* Do not try to read past this point. */
1181 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1182
1183 if (limit < cur_rx)
1184 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1185 else
1186 max_bytes = limit - cur_rx;
1187
1188 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1189#ifdef DEVICE_POLLING
1190 if (ifp->if_ipending & IFF_POLLING) {
1191 if (sc->rxcycles <= 0)
1192 break;
1193 sc->rxcycles--;
1194 }
1195#endif /* DEVICE_POLLING */
1196 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1197 rxstat = *(u_int32_t *)rxbufpos;
1198
1199 /*
1200 * Here's a totally undocumented fact for you. When the
1201 * RealTek chip is in the process of copying a packet into
1202 * RAM for you, the length will be 0xfff0. If you spot a
1203 * packet header with this value, you need to stop. The
1204 * datasheet makes absolutely no mention of this and
1205 * RealTek should be shot for this.
1206 */
1207 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1208 break;
1209
1210 if (!(rxstat & RL_RXSTAT_RXOK)) {
1211 ifp->if_ierrors++;
1212 rl_init(sc);
1213 return;
1214 }
1215
1216 /* No errors; receive the packet. */
1217 total_len = rxstat >> 16;
1218 rx_bytes += total_len + 4;
1219
1220 /*
1221 * XXX The RealTek chip includes the CRC with every
1222 * received frame, and there's no way to turn this
1223 * behavior off (at least, I can't find anything in
1224 * the manual that explains how to do it) so we have
1225 * to trim off the CRC manually.
1226 */
1227 total_len -= ETHER_CRC_LEN;
1228
1229 /*
1230 * Avoid trying to read more bytes than we know
1231 * the chip has prepared for us.
1232 */
1233 if (rx_bytes > max_bytes)
1234 break;
1235
1236 rxbufpos = sc->rl_cdata.rl_rx_buf +
1237 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN);
1238
1239 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1240 rxbufpos = sc->rl_cdata.rl_rx_buf;
1241
1242 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1243
1244 if (total_len > wrap) {
1245 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1246 NULL);
1247 if (m == NULL) {
1248 ifp->if_ierrors++;
1249 } else {
1250 m_copyback(m, wrap, total_len - wrap,
1251 sc->rl_cdata.rl_rx_buf);
1252 }
1253 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1254 } else {
1255 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1256 NULL);
1257 if (m == NULL) {
1258 ifp->if_ierrors++;
1259 }
1260 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1261 }
1262
1263 /*
1264 * Round up to 32-bit boundary.
1265 */
1266 cur_rx = (cur_rx + 3) & ~3;
1267 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1268
1269 if (m == NULL)
1270 continue;
1271
1272 eh = mtod(m, struct ether_header *);
1273 ifp->if_ipackets++;
1274
1275 /* Remove header from mbuf and pass it on. */
1276 m_adj(m, sizeof(struct ether_header));
1277 ether_input(ifp, eh, m);
1278 }
1279
1280 return;
1281}
1282
1283/*
1284 * A frame was downloaded to the chip. It's safe for us to clean up
1285 * the list buffers.
1286 */
1287static void rl_txeof(sc)
1288 struct rl_softc *sc;
1289{
1290 struct ifnet *ifp;
1291 u_int32_t txstat;
1292
1293 ifp = &sc->arpcom.ac_if;
1294
1295 /* Clear the timeout timer. */
1296 ifp->if_timer = 0;
1297
1298 /*
1299 * Go through our tx list and free mbufs for those
1300 * frames that have been uploaded.
1301 */
1302 do {
1303 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1304 if (!(txstat & (RL_TXSTAT_TX_OK|
1305 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1306 break;
1307
1308 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1309
1310 if (RL_LAST_TXMBUF(sc) != NULL) {
1311 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1312 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1313 m_freem(RL_LAST_TXMBUF(sc));
1314 RL_LAST_TXMBUF(sc) = NULL;
1315 }
1316 if (txstat & RL_TXSTAT_TX_OK)
1317 ifp->if_opackets++;
1318 else {
1319 int oldthresh;
1320 ifp->if_oerrors++;
1321 if ((txstat & RL_TXSTAT_TXABRT) ||
1322 (txstat & RL_TXSTAT_OUTOFWIN))
1323 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1324 oldthresh = sc->rl_txthresh;
1325 /* error recovery */
1326 rl_reset(sc);
1327 rl_init(sc);
1328 /*
1329 * If there was a transmit underrun,
1330 * bump the TX threshold.
1331 */
1332 if (txstat & RL_TXSTAT_TX_UNDERRUN)
1333 sc->rl_txthresh = oldthresh + 32;
1334 return;
1335 }
1336 RL_INC(sc->rl_cdata.last_tx);
1337 ifp->if_flags &= ~IFF_OACTIVE;
1338 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1339
1340 return;
1341}
1342
1343static void rl_tick(xsc)
1344 void *xsc;
1345{
1346 struct rl_softc *sc;
1347 struct mii_data *mii;
1348
1349 sc = xsc;
1350 RL_LOCK(sc);
1351 mii = device_get_softc(sc->rl_miibus);
1352
1353 mii_tick(mii);
1354
1355 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1356 RL_UNLOCK(sc);
1357
1358 return;
1359}
1360
1361#ifdef DEVICE_POLLING
1362static void
1363rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1364{
1365 struct rl_softc *sc = ifp->if_softc;
1366
1367 RL_LOCK(sc);
1368 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1369 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1370 goto done;
1371 }
1372
1373 sc->rxcycles = count;
1374 rl_rxeof(sc);
1375 rl_txeof(sc);
1376 if (ifp->if_snd.ifq_head != NULL)
1377 rl_start(ifp);
1378
1379 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1380 u_int16_t status;
1381
1382 status = CSR_READ_2(sc, RL_ISR);
1383 if (status)
1384 CSR_WRITE_2(sc, RL_ISR, status);
1385
1386 /*
1387 * XXX check behaviour on receiver stalls.
1388 */
1389
1390 if (status & RL_ISR_SYSTEM_ERR) {
1391 rl_reset(sc);
1392 rl_init(sc);
1393 }
1394 }
1395done:
1396 RL_UNLOCK(sc);
1397}
1398#endif /* DEVICE_POLLING */
1399
1400static void rl_intr(arg)
1401 void *arg;
1402{
1403 struct rl_softc *sc;
1404 struct ifnet *ifp;
1405 u_int16_t status;
1406
1407 sc = arg;
1408
1409 if (sc->suspended) {
1410 return;
1411 }
1412
1413 RL_LOCK(sc);
1414 ifp = &sc->arpcom.ac_if;
1415
1416#ifdef DEVICE_POLLING
1417 if (ifp->if_ipending & IFF_POLLING)
1418 goto done;
1419 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */
1420 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1421 rl_poll(ifp, 0, 1);
1422 goto done;
1423 }
1424#endif /* DEVICE_POLLING */
1425
1426 for (;;) {
1427
1428 status = CSR_READ_2(sc, RL_ISR);
1429 if (status)
1430 CSR_WRITE_2(sc, RL_ISR, status);
1431
1432 if ((status & RL_INTRS) == 0)
1433 break;
1434
1435 if (status & RL_ISR_RX_OK)
1436 rl_rxeof(sc);
1437
1438 if (status & RL_ISR_RX_ERR)
1439 rl_rxeof(sc);
1440
1441 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1442 rl_txeof(sc);
1443
1444 if (status & RL_ISR_SYSTEM_ERR) {
1445 rl_reset(sc);
1446 rl_init(sc);
1447 }
1448
1449 }
1450
1451 if (ifp->if_snd.ifq_head != NULL)
1452 rl_start(ifp);
1453
1454#ifdef DEVICE_POLLING
1455done:
1456#endif
1457 RL_UNLOCK(sc);
1458
1459 return;
1460}
1461
1462/*
1463 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1464 * pointers to the fragment pointers.
1465 */
1466static int rl_encap(sc, m_head)
1467 struct rl_softc *sc;
1468 struct mbuf *m_head;
1469{
1470 struct mbuf *m_new = NULL;
1471
1472 /*
1473 * The RealTek is brain damaged and wants longword-aligned
1474 * TX buffers, plus we can only have one fragment buffer
1475 * per packet. We have to copy pretty much all the time.
1476 */
1477
1478 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1479 if (m_new == NULL)
1480 return(1);
1481 if (m_head->m_pkthdr.len > MHLEN) {
1482 MCLGET(m_new, M_DONTWAIT);
1483 if (!(m_new->m_flags & M_EXT)) {
1484 m_freem(m_new);
1485 return(1);
1486 }
1487 }
1488 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1489 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1490 m_freem(m_head);
1491 m_head = m_new;
1492
1493 /* Pad frames to at least 60 bytes. */
1494 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1495 /*
1496 * Make security concious people happy: zero out the
1497 * bytes in the pad area, since we don't know what
1498 * this mbuf cluster buffer's previous user might
1499 * have left in it.
1500 */
1501 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1502 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1503 m_head->m_pkthdr.len +=
1504 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1505 m_head->m_len = m_head->m_pkthdr.len;
1506 }
1507
1508 RL_CUR_TXMBUF(sc) = m_head;
1509
1510 return(0);
1511}
1512
1513/*
1514 * Main transmit routine.
1515 */
1516
1517static void rl_start(ifp)
1518 struct ifnet *ifp;
1519{
1520 struct rl_softc *sc;
1521 struct mbuf *m_head = NULL;
1522
1523 sc = ifp->if_softc;
1524 RL_LOCK(sc);
1525
1526 while(RL_CUR_TXMBUF(sc) == NULL) {
1527 IF_DEQUEUE(&ifp->if_snd, m_head);
1528 if (m_head == NULL)
1529 break;
1530
1531 if (rl_encap(sc, m_head)) {
1532 IF_PREPEND(&ifp->if_snd, m_head);
1533 ifp->if_flags |= IFF_OACTIVE;
1534 break;
1535 }
1536
1537 /*
1538 * If there's a BPF listener, bounce a copy of this frame
1539 * to him.
1540 */
1541 if (ifp->if_bpf)
1542 bpf_mtap(ifp, RL_CUR_TXMBUF(sc));
1543
1544 /*
1545 * Transmit the frame.
1546 */
1547 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1548 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1549 mtod(RL_CUR_TXMBUF(sc), void *),
1550 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1551 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1552 BUS_DMASYNC_PREREAD);
1553 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1554 RL_TXTHRESH(sc->rl_txthresh) |
1555 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1556
1557 RL_INC(sc->rl_cdata.cur_tx);
1558 }
1559
1560 /*
1561 * We broke out of the loop because all our TX slots are
1562 * full. Mark the NIC as busy until it drains some of the
1563 * packets from the queue.
1564 */
1565 if (RL_CUR_TXMBUF(sc) != NULL)
1566 ifp->if_flags |= IFF_OACTIVE;
1567
1568 /*
1569 * Set a timeout in case the chip goes out to lunch.
1570 */
1571 ifp->if_timer = 5;
1572 RL_UNLOCK(sc);
1573
1574 return;
1575}
1576
1577static void rl_init(xsc)
1578 void *xsc;
1579{
1580 struct rl_softc *sc = xsc;
1581 struct ifnet *ifp = &sc->arpcom.ac_if;
1582 struct mii_data *mii;
1583 int i;
1584 u_int32_t rxcfg = 0;
1585
1586 RL_LOCK(sc);
1587 mii = device_get_softc(sc->rl_miibus);
1588
1589 /*
1590 * Cancel pending I/O and free all RX/TX buffers.
1591 */
1592 rl_stop(sc);
1593
1594 /* Init our MAC address */
1595 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1596 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]);
1597 }
1598
1599 /* Init the RX buffer pointer register. */
1600 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1601 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1602 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1603 BUS_DMASYNC_PREWRITE);
1604
1605 /* Init TX descriptors. */
1606 rl_list_tx_init(sc);
1607
1608 /*
1609 * Enable transmit and receive.
1610 */
1611 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1612
1613 /*
1614 * Set the initial TX and RX configuration.
1615 */
1616 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1617 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1618
1619 /* Set the individual bit to receive frames for this host only. */
1620 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1621 rxcfg |= RL_RXCFG_RX_INDIV;
1622
1623 /* If we want promiscuous mode, set the allframes bit. */
1624 if (ifp->if_flags & IFF_PROMISC) {
1625 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1626 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1627 } else {
1628 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1629 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1630 }
1631
1632 /*
1633 * Set capture broadcast bit to capture broadcast frames.
1634 */
1635 if (ifp->if_flags & IFF_BROADCAST) {
1636 rxcfg |= RL_RXCFG_RX_BROAD;
1637 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1638 } else {
1639 rxcfg &= ~RL_RXCFG_RX_BROAD;
1640 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1641 }
1642
1643 /*
1644 * Program the multicast filter, if necessary.
1645 */
1646 rl_setmulti(sc);
1647
1648#ifdef DEVICE_POLLING
1649 /*
1650 * Disable interrupts if we are polling.
1651 */
1652 if (ifp->if_ipending & IFF_POLLING)
1653 CSR_WRITE_2(sc, RL_IMR, 0);
1654 else /* otherwise ... */
1655#endif /* DEVICE_POLLING */
1656 /*
1657 * Enable interrupts.
1658 */
1659 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1660
1661 /* Set initial TX threshold */
1662 sc->rl_txthresh = RL_TX_THRESH_INIT;
1663
1664 /* Start RX/TX process. */
1665 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1666
1667 /* Enable receiver and transmitter. */
1668 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1669
1670 mii_mediachg(mii);
1671
1672 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1673
1674 ifp->if_flags |= IFF_RUNNING;
1675 ifp->if_flags &= ~IFF_OACTIVE;
1676
1677 sc->rl_stat_ch = timeout(rl_tick, sc, hz);
1678 RL_UNLOCK(sc);
1679
1680 return;
1681}
1682
1683/*
1684 * Set media options.
1685 */
1686static int rl_ifmedia_upd(ifp)
1687 struct ifnet *ifp;
1688{
1689 struct rl_softc *sc;
1690 struct mii_data *mii;
1691
1692 sc = ifp->if_softc;
1693 mii = device_get_softc(sc->rl_miibus);
1694 mii_mediachg(mii);
1695
1696 return(0);
1697}
1698
1699/*
1700 * Report current media status.
1701 */
1702static void rl_ifmedia_sts(ifp, ifmr)
1703 struct ifnet *ifp;
1704 struct ifmediareq *ifmr;
1705{
1706 struct rl_softc *sc;
1707 struct mii_data *mii;
1708
1709 sc = ifp->if_softc;
1710 mii = device_get_softc(sc->rl_miibus);
1711
1712 mii_pollstat(mii);
1713 ifmr->ifm_active = mii->mii_media_active;
1714 ifmr->ifm_status = mii->mii_media_status;
1715
1716 return;
1717}
1718
1719static int rl_ioctl(ifp, command, data)
1720 struct ifnet *ifp;
1721 u_long command;
1722 caddr_t data;
1723{
1724 struct rl_softc *sc = ifp->if_softc;
1725 struct ifreq *ifr = (struct ifreq *) data;
1726 struct mii_data *mii;
1727 int error = 0;
1728
1729 RL_LOCK(sc);
1730
1731 switch(command) {
1732 case SIOCSIFADDR:
1733 case SIOCGIFADDR:
1734 case SIOCSIFMTU:
1735 error = ether_ioctl(ifp, command, data);
1736 break;
1737 case SIOCSIFFLAGS:
1738 if (ifp->if_flags & IFF_UP) {
1739 rl_init(sc);
1740 } else {
1741 if (ifp->if_flags & IFF_RUNNING)
1742 rl_stop(sc);
1743 }
1744 error = 0;
1745 break;
1746 case SIOCADDMULTI:
1747 case SIOCDELMULTI:
1748 rl_setmulti(sc);
1749 error = 0;
1750 break;
1751 case SIOCGIFMEDIA:
1752 case SIOCSIFMEDIA:
1753 mii = device_get_softc(sc->rl_miibus);
1754 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1755 break;
1756 default:
1757 error = EINVAL;
1758 break;
1759 }
1760
1761 RL_UNLOCK(sc);
1762
1763 return(error);
1764}
1765
1766static void rl_watchdog(ifp)
1767 struct ifnet *ifp;
1768{
1769 struct rl_softc *sc;
1770
1771 sc = ifp->if_softc;
1772 RL_LOCK(sc);
1773 printf("rl%d: watchdog timeout\n", sc->rl_unit);
1774 ifp->if_oerrors++;
1775
1776 rl_txeof(sc);
1777 rl_rxeof(sc);
1778 rl_init(sc);
1779 RL_UNLOCK(sc);
1780
1781 return;
1782}
1783
1784/*
1785 * Stop the adapter and free any mbufs allocated to the
1786 * RX and TX lists.
1787 */
1788static void rl_stop(sc)
1789 struct rl_softc *sc;
1790{
1791 register int i;
1792 struct ifnet *ifp;
1793
1794 RL_LOCK(sc);
1795 ifp = &sc->arpcom.ac_if;
1796 ifp->if_timer = 0;
1797
1798 untimeout(rl_tick, sc, sc->rl_stat_ch);
1799 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1800#ifdef DEVICE_POLLING
1801 ether_poll_deregister(ifp);
1802#endif /* DEVICE_POLLING */
1803
1804 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1805 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1806 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1807
1808 /*
1809 * Free the TX list buffers.
1810 */
1811 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1812 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1813 bus_dmamap_unload(sc->rl_tag,
1814 sc->rl_cdata.rl_tx_dmamap[i]);
1815 bus_dmamap_destroy(sc->rl_tag,
1816 sc->rl_cdata.rl_tx_dmamap[i]);
1817 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1818 sc->rl_cdata.rl_tx_chain[i] = NULL;
1819 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000);
1820 }
1821 }
1822
1823 RL_UNLOCK(sc);
1824 return;
1825}
1826
1827/*
1828 * Device suspend routine. Stop the interface and save some PCI
1829 * settings in case the BIOS doesn't restore them properly on
1830 * resume.
1831 */
1832static int rl_suspend(dev)
1833 device_t dev;
1834{
1835 register int i;
1836 struct rl_softc *sc;
1837
1838 sc = device_get_softc(dev);
1839
1840 rl_stop(sc);
1841
1842 for (i = 0; i < 5; i++)
1843 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
1844 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1845 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1846 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1847 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1848
1849 sc->suspended = 1;
1850
1851 return (0);
1852}
1853
1854/*
1855 * Device resume routine. Restore some PCI settings in case the BIOS
1856 * doesn't, re-enable busmastering, and restart the interface if
1857 * appropriate.
1858 */
1859static int rl_resume(dev)
1860 device_t dev;
1861{
1862 register int i;
1863 struct rl_softc *sc;
1864 struct ifnet *ifp;
1865
1866 sc = device_get_softc(dev);
1867 ifp = &sc->arpcom.ac_if;
1868
1869 /* better way to do this? */
1870 for (i = 0; i < 5; i++)
1871 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
1872 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1873 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1874 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1875 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1876
1877 /* reenable busmastering */
1878 pci_enable_busmaster(dev);
1879 pci_enable_io(dev, RL_RES);
1880
1881 /* reinitialize interface if necessary */
1882 if (ifp->if_flags & IFF_UP)
1883 rl_init(sc);
1884
1885 sc->suspended = 0;
1886
1887 return (0);
1888}
1889
1890/*
1891 * Stop all chip I/O so that the kernel's probe routines don't
1892 * get confused by errant DMAs when rebooting.
1893 */
1894static void rl_shutdown(dev)
1895 device_t dev;
1896{
1897 struct rl_softc *sc;
1898
1899 sc = device_get_softc(dev);
1900
1901 rl_stop(sc);
1902
1903 return;
1904}
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