147 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
148 "RealTek 8139 10/100BaseTX CardBus" },
149 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
150 "RealTek 8100 10/100BaseTX" },
151 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
152 "Accton MPX 5030/5038 10/100BaseTX" },
153 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
154 "Delta Electronics 8139 10/100BaseTX" },
155 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
156 "Addtron Technolgy 8139 10/100BaseTX" },
157 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
158 "D-Link DFE-530TX+ 10/100BaseTX" },
159 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
160 "D-Link DFE-690TXD 10/100BaseTX" },
161 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
162 "Nortel Networks 10/100BaseTX" },
163 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
164 "Corega FEther CB-TXD" },
165 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
166 "Corega FEtherII CB-TXD" },
167 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
168 "Peppercon AG ROL-F" },
169 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
170 "Planex FNW-3603-TX" },
171 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
172 "Planex FNW-3800-TX" },
173 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
174 "Compaq HNE-300" },
175 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
176 "LevelOne FPC-0106TX" },
177 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
178 "Edimax EP-4103DL CardBus" }
179};
180
181static int rl_attach(device_t);
182static int rl_detach(device_t);
183static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
184static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
185static void rl_eeprom_putbyte(struct rl_softc *, int);
186static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
187static int rl_encap(struct rl_softc *, struct mbuf * );
188static int rl_list_tx_init(struct rl_softc *);
189static int rl_ifmedia_upd(struct ifnet *);
190static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
191static int rl_ioctl(struct ifnet *, u_long, caddr_t);
192static void rl_intr(void *);
193static void rl_init(void *);
194static void rl_init_locked(struct rl_softc *sc);
195static void rl_mii_send(struct rl_softc *, uint32_t, int);
196static void rl_mii_sync(struct rl_softc *);
197static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
198static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
199static int rl_miibus_readreg(device_t, int, int);
200static void rl_miibus_statchg(device_t);
201static int rl_miibus_writereg(device_t, int, int, int);
202#ifdef DEVICE_POLLING
203static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
204static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
205#endif
206static int rl_probe(device_t);
207static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
208static void rl_reset(struct rl_softc *);
209static int rl_resume(device_t);
210static void rl_rxeof(struct rl_softc *);
211static void rl_setmulti(struct rl_softc *);
212static int rl_shutdown(device_t);
213static void rl_start(struct ifnet *);
214static void rl_start_locked(struct ifnet *);
215static void rl_stop(struct rl_softc *);
216static int rl_suspend(device_t);
217static void rl_tick(void *);
218static void rl_txeof(struct rl_softc *);
219static void rl_watchdog(struct rl_softc *);
220
221#ifdef RL_USEIOSPACE
222#define RL_RES SYS_RES_IOPORT
223#define RL_RID RL_PCI_LOIO
224#else
225#define RL_RES SYS_RES_MEMORY
226#define RL_RID RL_PCI_LOMEM
227#endif
228
229static device_method_t rl_methods[] = {
230 /* Device interface */
231 DEVMETHOD(device_probe, rl_probe),
232 DEVMETHOD(device_attach, rl_attach),
233 DEVMETHOD(device_detach, rl_detach),
234 DEVMETHOD(device_suspend, rl_suspend),
235 DEVMETHOD(device_resume, rl_resume),
236 DEVMETHOD(device_shutdown, rl_shutdown),
237
238 /* bus interface */
239 DEVMETHOD(bus_print_child, bus_generic_print_child),
240 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
241
242 /* MII interface */
243 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
244 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
245 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
246
247 { 0, 0 }
248};
249
250static driver_t rl_driver = {
251 "rl",
252 rl_methods,
253 sizeof(struct rl_softc)
254};
255
256static devclass_t rl_devclass;
257
258DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
259DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
260DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
261
262#define EE_SET(x) \
263 CSR_WRITE_1(sc, RL_EECMD, \
264 CSR_READ_1(sc, RL_EECMD) | x)
265
266#define EE_CLR(x) \
267 CSR_WRITE_1(sc, RL_EECMD, \
268 CSR_READ_1(sc, RL_EECMD) & ~x)
269
270static void
271rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
272{
273 struct rl_softc *sc = arg;
274
275 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
276}
277
278static void
279rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
280{
281 struct rl_softc *sc = arg;
282
283 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
284}
285
286/*
287 * Send a read command and address to the EEPROM, check for ACK.
288 */
289static void
290rl_eeprom_putbyte(struct rl_softc *sc, int addr)
291{
292 register int d, i;
293
294 d = addr | sc->rl_eecmd_read;
295
296 /*
297 * Feed in each bit and strobe the clock.
298 */
299 for (i = 0x400; i; i >>= 1) {
300 if (d & i) {
301 EE_SET(RL_EE_DATAIN);
302 } else {
303 EE_CLR(RL_EE_DATAIN);
304 }
305 DELAY(100);
306 EE_SET(RL_EE_CLK);
307 DELAY(150);
308 EE_CLR(RL_EE_CLK);
309 DELAY(100);
310 }
311}
312
313/*
314 * Read a word of data stored in the EEPROM at address 'addr.'
315 */
316static void
317rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
318{
319 register int i;
320 uint16_t word = 0;
321
322 /* Enter EEPROM access mode. */
323 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
324
325 /*
326 * Send address of word we want to read.
327 */
328 rl_eeprom_putbyte(sc, addr);
329
330 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
331
332 /*
333 * Start reading bits from EEPROM.
334 */
335 for (i = 0x8000; i; i >>= 1) {
336 EE_SET(RL_EE_CLK);
337 DELAY(100);
338 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
339 word |= i;
340 EE_CLR(RL_EE_CLK);
341 DELAY(100);
342 }
343
344 /* Turn off EEPROM access mode. */
345 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
346
347 *dest = word;
348}
349
350/*
351 * Read a sequence of words from the EEPROM.
352 */
353static void
354rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
355{
356 int i;
357 uint16_t word = 0, *ptr;
358
359 for (i = 0; i < cnt; i++) {
360 rl_eeprom_getword(sc, off + i, &word);
361 ptr = (uint16_t *)(dest + (i * 2));
362 if (swap)
363 *ptr = ntohs(word);
364 else
365 *ptr = word;
366 }
367}
368
369/*
370 * MII access routines are provided for the 8129, which
371 * doesn't have a built-in PHY. For the 8139, we fake things
372 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
373 * direct access PHY registers.
374 */
375#define MII_SET(x) \
376 CSR_WRITE_1(sc, RL_MII, \
377 CSR_READ_1(sc, RL_MII) | (x))
378
379#define MII_CLR(x) \
380 CSR_WRITE_1(sc, RL_MII, \
381 CSR_READ_1(sc, RL_MII) & ~(x))
382
383/*
384 * Sync the PHYs by setting data bit and strobing the clock 32 times.
385 */
386static void
387rl_mii_sync(struct rl_softc *sc)
388{
389 register int i;
390
391 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
392
393 for (i = 0; i < 32; i++) {
394 MII_SET(RL_MII_CLK);
395 DELAY(1);
396 MII_CLR(RL_MII_CLK);
397 DELAY(1);
398 }
399}
400
401/*
402 * Clock a series of bits through the MII.
403 */
404static void
405rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
406{
407 int i;
408
409 MII_CLR(RL_MII_CLK);
410
411 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
412 if (bits & i) {
413 MII_SET(RL_MII_DATAOUT);
414 } else {
415 MII_CLR(RL_MII_DATAOUT);
416 }
417 DELAY(1);
418 MII_CLR(RL_MII_CLK);
419 DELAY(1);
420 MII_SET(RL_MII_CLK);
421 }
422}
423
424/*
425 * Read an PHY register through the MII.
426 */
427static int
428rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
429{
430 int i, ack;
431
432 /* Set up frame for RX. */
433 frame->mii_stdelim = RL_MII_STARTDELIM;
434 frame->mii_opcode = RL_MII_READOP;
435 frame->mii_turnaround = 0;
436 frame->mii_data = 0;
437
438 CSR_WRITE_2(sc, RL_MII, 0);
439
440 /* Turn on data xmit. */
441 MII_SET(RL_MII_DIR);
442
443 rl_mii_sync(sc);
444
445 /* Send command/address info. */
446 rl_mii_send(sc, frame->mii_stdelim, 2);
447 rl_mii_send(sc, frame->mii_opcode, 2);
448 rl_mii_send(sc, frame->mii_phyaddr, 5);
449 rl_mii_send(sc, frame->mii_regaddr, 5);
450
451 /* Idle bit */
452 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
453 DELAY(1);
454 MII_SET(RL_MII_CLK);
455 DELAY(1);
456
457 /* Turn off xmit. */
458 MII_CLR(RL_MII_DIR);
459
460 /* Check for ack */
461 MII_CLR(RL_MII_CLK);
462 DELAY(1);
463 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
464 MII_SET(RL_MII_CLK);
465 DELAY(1);
466
467 /*
468 * Now try reading data bits. If the ack failed, we still
469 * need to clock through 16 cycles to keep the PHY(s) in sync.
470 */
471 if (ack) {
472 for(i = 0; i < 16; i++) {
473 MII_CLR(RL_MII_CLK);
474 DELAY(1);
475 MII_SET(RL_MII_CLK);
476 DELAY(1);
477 }
478 goto fail;
479 }
480
481 for (i = 0x8000; i; i >>= 1) {
482 MII_CLR(RL_MII_CLK);
483 DELAY(1);
484 if (!ack) {
485 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
486 frame->mii_data |= i;
487 DELAY(1);
488 }
489 MII_SET(RL_MII_CLK);
490 DELAY(1);
491 }
492
493fail:
494 MII_CLR(RL_MII_CLK);
495 DELAY(1);
496 MII_SET(RL_MII_CLK);
497 DELAY(1);
498
499 return (ack ? 1 : 0);
500}
501
502/*
503 * Write to a PHY register through the MII.
504 */
505static int
506rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
507{
508
509 /* Set up frame for TX. */
510 frame->mii_stdelim = RL_MII_STARTDELIM;
511 frame->mii_opcode = RL_MII_WRITEOP;
512 frame->mii_turnaround = RL_MII_TURNAROUND;
513
514 /* Turn on data output. */
515 MII_SET(RL_MII_DIR);
516
517 rl_mii_sync(sc);
518
519 rl_mii_send(sc, frame->mii_stdelim, 2);
520 rl_mii_send(sc, frame->mii_opcode, 2);
521 rl_mii_send(sc, frame->mii_phyaddr, 5);
522 rl_mii_send(sc, frame->mii_regaddr, 5);
523 rl_mii_send(sc, frame->mii_turnaround, 2);
524 rl_mii_send(sc, frame->mii_data, 16);
525
526 /* Idle bit. */
527 MII_SET(RL_MII_CLK);
528 DELAY(1);
529 MII_CLR(RL_MII_CLK);
530 DELAY(1);
531
532 /* Turn off xmit. */
533 MII_CLR(RL_MII_DIR);
534
535 return (0);
536}
537
538static int
539rl_miibus_readreg(device_t dev, int phy, int reg)
540{
541 struct rl_softc *sc;
542 struct rl_mii_frame frame;
543 uint16_t rval = 0;
544 uint16_t rl8139_reg = 0;
545
546 sc = device_get_softc(dev);
547
548 if (sc->rl_type == RL_8139) {
549 /* Pretend the internal PHY is only at address 0 */
550 if (phy) {
551 return (0);
552 }
553 switch (reg) {
554 case MII_BMCR:
555 rl8139_reg = RL_BMCR;
556 break;
557 case MII_BMSR:
558 rl8139_reg = RL_BMSR;
559 break;
560 case MII_ANAR:
561 rl8139_reg = RL_ANAR;
562 break;
563 case MII_ANER:
564 rl8139_reg = RL_ANER;
565 break;
566 case MII_ANLPAR:
567 rl8139_reg = RL_LPAR;
568 break;
569 case MII_PHYIDR1:
570 case MII_PHYIDR2:
571 return (0);
572 /*
573 * Allow the rlphy driver to read the media status
574 * register. If we have a link partner which does not
575 * support NWAY, this is the register which will tell
576 * us the results of parallel detection.
577 */
578 case RL_MEDIASTAT:
579 rval = CSR_READ_1(sc, RL_MEDIASTAT);
580 return (rval);
581 default:
582 device_printf(sc->rl_dev, "bad phy register\n");
583 return (0);
584 }
585 rval = CSR_READ_2(sc, rl8139_reg);
586 return (rval);
587 }
588
589 bzero((char *)&frame, sizeof(frame));
590 frame.mii_phyaddr = phy;
591 frame.mii_regaddr = reg;
592 rl_mii_readreg(sc, &frame);
593
594 return (frame.mii_data);
595}
596
597static int
598rl_miibus_writereg(device_t dev, int phy, int reg, int data)
599{
600 struct rl_softc *sc;
601 struct rl_mii_frame frame;
602 uint16_t rl8139_reg = 0;
603
604 sc = device_get_softc(dev);
605
606 if (sc->rl_type == RL_8139) {
607 /* Pretend the internal PHY is only at address 0 */
608 if (phy) {
609 return (0);
610 }
611 switch (reg) {
612 case MII_BMCR:
613 rl8139_reg = RL_BMCR;
614 break;
615 case MII_BMSR:
616 rl8139_reg = RL_BMSR;
617 break;
618 case MII_ANAR:
619 rl8139_reg = RL_ANAR;
620 break;
621 case MII_ANER:
622 rl8139_reg = RL_ANER;
623 break;
624 case MII_ANLPAR:
625 rl8139_reg = RL_LPAR;
626 break;
627 case MII_PHYIDR1:
628 case MII_PHYIDR2:
629 return (0);
630 break;
631 default:
632 device_printf(sc->rl_dev, "bad phy register\n");
633 return (0);
634 }
635 CSR_WRITE_2(sc, rl8139_reg, data);
636 return (0);
637 }
638
639 bzero((char *)&frame, sizeof(frame));
640 frame.mii_phyaddr = phy;
641 frame.mii_regaddr = reg;
642 frame.mii_data = data;
643 rl_mii_writereg(sc, &frame);
644
645 return (0);
646}
647
648static void
649rl_miibus_statchg(device_t dev)
650{
651}
652
653/*
654 * Program the 64-bit multicast hash filter.
655 */
656static void
657rl_setmulti(struct rl_softc *sc)
658{
659 struct ifnet *ifp = sc->rl_ifp;
660 int h = 0;
661 uint32_t hashes[2] = { 0, 0 };
662 struct ifmultiaddr *ifma;
663 uint32_t rxfilt;
664 int mcnt = 0;
665
666 RL_LOCK_ASSERT(sc);
667
668 rxfilt = CSR_READ_4(sc, RL_RXCFG);
669
670 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
671 rxfilt |= RL_RXCFG_RX_MULTI;
672 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
673 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
674 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
675 return;
676 }
677
678 /* first, zot all the existing hash bits */
679 CSR_WRITE_4(sc, RL_MAR0, 0);
680 CSR_WRITE_4(sc, RL_MAR4, 0);
681
682 /* now program new ones */
683 IF_ADDR_LOCK(ifp);
684 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
685 if (ifma->ifma_addr->sa_family != AF_LINK)
686 continue;
687 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
688 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
689 if (h < 32)
690 hashes[0] |= (1 << h);
691 else
692 hashes[1] |= (1 << (h - 32));
693 mcnt++;
694 }
695 IF_ADDR_UNLOCK(ifp);
696
697 if (mcnt)
698 rxfilt |= RL_RXCFG_RX_MULTI;
699 else
700 rxfilt &= ~RL_RXCFG_RX_MULTI;
701
702 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
703 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
704 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
705}
706
707static void
708rl_reset(struct rl_softc *sc)
709{
710 register int i;
711
712 RL_LOCK_ASSERT(sc);
713
714 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
715
716 for (i = 0; i < RL_TIMEOUT; i++) {
717 DELAY(10);
718 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
719 break;
720 }
721 if (i == RL_TIMEOUT)
722 device_printf(sc->rl_dev, "reset never completed!\n");
723}
724
725/*
726 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
727 * IDs against our list and return a device name if we find a match.
728 */
729static int
730rl_probe(device_t dev)
731{
732 struct rl_type *t;
733 uint16_t devid, revid, vendor;
734 int i;
735
736 vendor = pci_get_vendor(dev);
737 devid = pci_get_device(dev);
738 revid = pci_get_revid(dev);
739
740 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
741 if (revid == 0x20) {
742 /* 8139C+, let re(4) take care of this device. */
743 return (ENXIO);
744 }
745 }
746 t = rl_devs;
747 for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) {
748 if (vendor == t->rl_vid && devid == t->rl_did) {
749 device_set_desc(dev, t->rl_name);
750 return (BUS_PROBE_DEFAULT);
751 }
752 }
753
754 return (ENXIO);
755}
756
757/*
758 * Attach the interface. Allocate softc structures, do ifmedia
759 * setup and ethernet/BPF attach.
760 */
761static int
762rl_attach(device_t dev)
763{
764 uint8_t eaddr[ETHER_ADDR_LEN];
765 uint16_t as[3];
766 struct ifnet *ifp;
767 struct rl_softc *sc;
768 struct rl_type *t;
769 int error = 0, i, rid;
770 int unit;
771 uint16_t rl_did = 0;
772
773 sc = device_get_softc(dev);
774 unit = device_get_unit(dev);
775 sc->rl_dev = dev;
776
777 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
778 MTX_DEF);
779 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
780
781 pci_enable_busmaster(dev);
782
783 /* Map control/status registers. */
784 rid = RL_RID;
785 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
786
787 if (sc->rl_res == NULL) {
788 device_printf(dev, "couldn't map ports/memory\n");
789 error = ENXIO;
790 goto fail;
791 }
792
793#ifdef notdef
794 /*
795 * Detect the Realtek 8139B. For some reason, this chip is very
796 * unstable when left to autoselect the media
797 * The best workaround is to set the device to the required
798 * media type or to set it to the 10 Meg speed.
799 */
800 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
801 device_printf(dev,
802"Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
803#endif
804
805 sc->rl_btag = rman_get_bustag(sc->rl_res);
806 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
807
808 /* Allocate interrupt */
809 rid = 0;
810 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
811 RF_SHAREABLE | RF_ACTIVE);
812
813 if (sc->rl_irq[0] == NULL) {
814 device_printf(dev, "couldn't map interrupt\n");
815 error = ENXIO;
816 goto fail;
817 }
818
819 /*
820 * Reset the adapter. Only take the lock here as it's needed in
821 * order to call rl_reset().
822 */
823 RL_LOCK(sc);
824 rl_reset(sc);
825 RL_UNLOCK(sc);
826
827 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
828 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
829 if (rl_did != 0x8129)
830 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
831
832 /*
833 * Get station address from the EEPROM.
834 */
835 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
836 for (i = 0; i < 3; i++) {
837 eaddr[(i * 2) + 0] = as[i] & 0xff;
838 eaddr[(i * 2) + 1] = as[i] >> 8;
839 }
840
841 /*
842 * Now read the exact device type from the EEPROM to find
843 * out if it's an 8129 or 8139.
844 */
845 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
846
847 t = rl_devs;
848 sc->rl_type = 0;
849 while(t->rl_name != NULL) {
850 if (rl_did == t->rl_did) {
851 sc->rl_type = t->rl_basetype;
852 break;
853 }
854 t++;
855 }
856
857 if (sc->rl_type == 0) {
858 device_printf(dev, "unknown device ID: %x\n", rl_did);
859 error = ENXIO;
860 goto fail;
861 }
862
863 /*
864 * Allocate the parent bus DMA tag appropriate for PCI.
865 */
866#define RL_NSEG_NEW 32
867 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
868 1, 0, /* alignment, boundary */
869 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
870 BUS_SPACE_MAXADDR, /* highaddr */
871 NULL, NULL, /* filter, filterarg */
872 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
873 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
874 BUS_DMA_ALLOCNOW, /* flags */
875 NULL, NULL, /* lockfunc, lockarg */
876 &sc->rl_parent_tag);
877 if (error)
878 goto fail;
879
880 /*
881 * Now allocate a tag for the DMA descriptor lists.
882 * All of our lists are allocated as a contiguous block
883 * of memory.
884 */
885 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
886 1, 0, /* alignment, boundary */
887 BUS_SPACE_MAXADDR, /* lowaddr */
888 BUS_SPACE_MAXADDR, /* highaddr */
889 NULL, NULL, /* filter, filterarg */
890 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
891 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
892 BUS_DMA_ALLOCNOW, /* flags */
893 NULL, NULL, /* lockfunc, lockarg */
894 &sc->rl_tag);
895 if (error)
896 goto fail;
897
898 /*
899 * Now allocate a chunk of DMA-able memory based on the
900 * tag we just created.
901 */
902 error = bus_dmamem_alloc(sc->rl_tag,
903 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
904 &sc->rl_cdata.rl_rx_dmamap);
905 if (error) {
906 device_printf(dev, "no memory for list buffers!\n");
907 bus_dma_tag_destroy(sc->rl_tag);
908 sc->rl_tag = NULL;
909 goto fail;
910 }
911
912 /* Leave a few bytes before the start of the RX ring buffer. */
913 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
914 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t);
915
916 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
917 if (ifp == NULL) {
918 device_printf(dev, "can not if_alloc()\n");
919 error = ENOSPC;
920 goto fail;
921 }
922
923 /* Do MII setup */
924 if (mii_phy_probe(dev, &sc->rl_miibus,
925 rl_ifmedia_upd, rl_ifmedia_sts)) {
926 device_printf(dev, "MII without any phy!\n");
927 error = ENXIO;
928 goto fail;
929 }
930
931 ifp->if_softc = sc;
932 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
933 ifp->if_mtu = ETHERMTU;
934 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
935 ifp->if_ioctl = rl_ioctl;
936 ifp->if_start = rl_start;
937 ifp->if_init = rl_init;
938 ifp->if_capabilities = IFCAP_VLAN_MTU;
939 ifp->if_capenable = ifp->if_capabilities;
940#ifdef DEVICE_POLLING
941 ifp->if_capabilities |= IFCAP_POLLING;
942#endif
943 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
944 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
945 IFQ_SET_READY(&ifp->if_snd);
946
947 /*
948 * Call MI attach routine.
949 */
950 ether_ifattach(ifp, eaddr);
951
952 /* Hook interrupt last to avoid having to lock softc */
953 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
954 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
955 if (error) {
956 device_printf(sc->rl_dev, "couldn't set up irq\n");
957 ether_ifdetach(ifp);
958 }
959
960fail:
961 if (error)
962 rl_detach(dev);
963
964 return (error);
965}
966
967/*
968 * Shutdown hardware and free up resources. This can be called any
969 * time after the mutex has been initialized. It is called in both
970 * the error case in attach and the normal detach case so it needs
971 * to be careful about only freeing resources that have actually been
972 * allocated.
973 */
974static int
975rl_detach(device_t dev)
976{
977 struct rl_softc *sc;
978 struct ifnet *ifp;
979
980 sc = device_get_softc(dev);
981 ifp = sc->rl_ifp;
982
983 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
984
985#ifdef DEVICE_POLLING
986 if (ifp->if_capenable & IFCAP_POLLING)
987 ether_poll_deregister(ifp);
988#endif
989 /* These should only be active if attach succeeded */
990 if (device_is_attached(dev)) {
991 RL_LOCK(sc);
992 rl_stop(sc);
993 RL_UNLOCK(sc);
994 callout_drain(&sc->rl_stat_callout);
995 ether_ifdetach(ifp);
996 }
997#if 0
998 sc->suspended = 1;
999#endif
1000 if (sc->rl_miibus)
1001 device_delete_child(dev, sc->rl_miibus);
1002 bus_generic_detach(dev);
1003
1004 if (sc->rl_intrhand[0])
1005 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1006 if (sc->rl_irq[0])
1007 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
1008 if (sc->rl_res)
1009 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1010
1011 if (ifp)
1012 if_free(ifp);
1013
1014 if (sc->rl_tag) {
1015 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1016 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1017 sc->rl_cdata.rl_rx_dmamap);
1018 bus_dma_tag_destroy(sc->rl_tag);
1019 }
1020 if (sc->rl_parent_tag)
1021 bus_dma_tag_destroy(sc->rl_parent_tag);
1022
1023 mtx_destroy(&sc->rl_mtx);
1024
1025 return (0);
1026}
1027
1028/*
1029 * Initialize the transmit descriptors.
1030 */
1031static int
1032rl_list_tx_init(struct rl_softc *sc)
1033{
1034 struct rl_chain_data *cd;
1035 int i;
1036
1037 RL_LOCK_ASSERT(sc);
1038
1039 cd = &sc->rl_cdata;
1040 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1041 cd->rl_tx_chain[i] = NULL;
1042 CSR_WRITE_4(sc,
1043 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1044 }
1045
1046 sc->rl_cdata.cur_tx = 0;
1047 sc->rl_cdata.last_tx = 0;
1048
1049 return (0);
1050}
1051
1052/*
1053 * A frame has been uploaded: pass the resulting mbuf chain up to
1054 * the higher level protocols.
1055 *
1056 * You know there's something wrong with a PCI bus-master chip design
1057 * when you have to use m_devget().
1058 *
1059 * The receive operation is badly documented in the datasheet, so I'll
1060 * attempt to document it here. The driver provides a buffer area and
1061 * places its base address in the RX buffer start address register.
1062 * The chip then begins copying frames into the RX buffer. Each frame
1063 * is preceded by a 32-bit RX status word which specifies the length
1064 * of the frame and certain other status bits. Each frame (starting with
1065 * the status word) is also 32-bit aligned. The frame length is in the
1066 * first 16 bits of the status word; the lower 15 bits correspond with
1067 * the 'rx status register' mentioned in the datasheet.
1068 *
1069 * Note: to make the Alpha happy, the frame payload needs to be aligned
1070 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1071 * as the offset argument to m_devget().
1072 */
1073static void
1074rl_rxeof(struct rl_softc *sc)
1075{
1076 struct mbuf *m;
1077 struct ifnet *ifp = sc->rl_ifp;
1078 uint8_t *rxbufpos;
1079 int total_len = 0;
1080 int wrap = 0;
1081 uint32_t rxstat;
1082 uint16_t cur_rx;
1083 uint16_t limit;
1084 uint16_t max_bytes, rx_bytes = 0;
1085
1086 RL_LOCK_ASSERT(sc);
1087
1088 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1089 BUS_DMASYNC_POSTREAD);
1090
1091 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1092
1093 /* Do not try to read past this point. */
1094 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1095
1096 if (limit < cur_rx)
1097 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1098 else
1099 max_bytes = limit - cur_rx;
1100
1101 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1102#ifdef DEVICE_POLLING
1103 if (ifp->if_capenable & IFCAP_POLLING) {
1104 if (sc->rxcycles <= 0)
1105 break;
1106 sc->rxcycles--;
1107 }
1108#endif
1109 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1110 rxstat = le32toh(*(uint32_t *)rxbufpos);
1111
1112 /*
1113 * Here's a totally undocumented fact for you. When the
1114 * RealTek chip is in the process of copying a packet into
1115 * RAM for you, the length will be 0xfff0. If you spot a
1116 * packet header with this value, you need to stop. The
1117 * datasheet makes absolutely no mention of this and
1118 * RealTek should be shot for this.
1119 */
1120 total_len = rxstat >> 16;
1121 if (total_len == RL_RXSTAT_UNFINISHED)
1122 break;
1123
1124 if (!(rxstat & RL_RXSTAT_RXOK) ||
1125 total_len < ETHER_MIN_LEN ||
1126 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1127 ifp->if_ierrors++;
1128 rl_init_locked(sc);
1129 return;
1130 }
1131
1132 /* No errors; receive the packet. */
1133 rx_bytes += total_len + 4;
1134
1135 /*
1136 * XXX The RealTek chip includes the CRC with every
1137 * received frame, and there's no way to turn this
1138 * behavior off (at least, I can't find anything in
1139 * the manual that explains how to do it) so we have
1140 * to trim off the CRC manually.
1141 */
1142 total_len -= ETHER_CRC_LEN;
1143
1144 /*
1145 * Avoid trying to read more bytes than we know
1146 * the chip has prepared for us.
1147 */
1148 if (rx_bytes > max_bytes)
1149 break;
1150
1151 rxbufpos = sc->rl_cdata.rl_rx_buf +
1152 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1153 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1154 rxbufpos = sc->rl_cdata.rl_rx_buf;
1155
1156 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1157 if (total_len > wrap) {
1158 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1159 NULL);
1160 if (m == NULL) {
1161 ifp->if_ierrors++;
1162 } else {
1163 m_copyback(m, wrap, total_len - wrap,
1164 sc->rl_cdata.rl_rx_buf);
1165 }
1166 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1167 } else {
1168 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1169 NULL);
1170 if (m == NULL)
1171 ifp->if_ierrors++;
1172 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1173 }
1174
1175 /* Round up to 32-bit boundary. */
1176 cur_rx = (cur_rx + 3) & ~3;
1177 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1178
1179 if (m == NULL)
1180 continue;
1181
1182 ifp->if_ipackets++;
1183 RL_UNLOCK(sc);
1184 (*ifp->if_input)(ifp, m);
1185 RL_LOCK(sc);
1186 }
1187}
1188
1189/*
1190 * A frame was downloaded to the chip. It's safe for us to clean up
1191 * the list buffers.
1192 */
1193static void
1194rl_txeof(struct rl_softc *sc)
1195{
1196 struct ifnet *ifp = sc->rl_ifp;
1197 uint32_t txstat;
1198
1199 RL_LOCK_ASSERT(sc);
1200
1201 /*
1202 * Go through our tx list and free mbufs for those
1203 * frames that have been uploaded.
1204 */
1205 do {
1206 if (RL_LAST_TXMBUF(sc) == NULL)
1207 break;
1208 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1209 if (!(txstat & (RL_TXSTAT_TX_OK|
1210 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1211 break;
1212
1213 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1214
1215 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1216 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1217 m_freem(RL_LAST_TXMBUF(sc));
1218 RL_LAST_TXMBUF(sc) = NULL;
1219 /*
1220 * If there was a transmit underrun, bump the TX threshold.
1221 * Make sure not to overflow the 63 * 32byte we can address
1222 * with the 6 available bit.
1223 */
1224 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1225 (sc->rl_txthresh < 2016))
1226 sc->rl_txthresh += 32;
1227 if (txstat & RL_TXSTAT_TX_OK)
1228 ifp->if_opackets++;
1229 else {
1230 int oldthresh;
1231 ifp->if_oerrors++;
1232 if ((txstat & RL_TXSTAT_TXABRT) ||
1233 (txstat & RL_TXSTAT_OUTOFWIN))
1234 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1235 oldthresh = sc->rl_txthresh;
1236 /* error recovery */
1237 rl_reset(sc);
1238 rl_init_locked(sc);
1239 /* restore original threshold */
1240 sc->rl_txthresh = oldthresh;
1241 return;
1242 }
1243 RL_INC(sc->rl_cdata.last_tx);
1244 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1245 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1246
1247 if (RL_LAST_TXMBUF(sc) == NULL)
1248 sc->rl_watchdog_timer = 0;
1249 else if (sc->rl_watchdog_timer == 0)
1250 sc->rl_watchdog_timer = 5;
1251}
1252
1253static void
1254rl_tick(void *xsc)
1255{
1256 struct rl_softc *sc = xsc;
1257 struct mii_data *mii;
1258
1259 RL_LOCK_ASSERT(sc);
1260 mii = device_get_softc(sc->rl_miibus);
1261 mii_tick(mii);
1262
1263 rl_watchdog(sc);
1264
1265 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1266}
1267
1268#ifdef DEVICE_POLLING
1269static void
1270rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1271{
1272 struct rl_softc *sc = ifp->if_softc;
1273
1274 RL_LOCK(sc);
1275 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1276 rl_poll_locked(ifp, cmd, count);
1277 RL_UNLOCK(sc);
1278}
1279
1280static void
1281rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1282{
1283 struct rl_softc *sc = ifp->if_softc;
1284
1285 RL_LOCK_ASSERT(sc);
1286
1287 sc->rxcycles = count;
1288 rl_rxeof(sc);
1289 rl_txeof(sc);
1290
1291 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1292 rl_start_locked(ifp);
1293
1294 if (cmd == POLL_AND_CHECK_STATUS) {
1295 uint16_t status;
1296
1297 /* We should also check the status register. */
1298 status = CSR_READ_2(sc, RL_ISR);
1299 if (status == 0xffff)
1300 return;
1301 if (status != 0)
1302 CSR_WRITE_2(sc, RL_ISR, status);
1303
1304 /* XXX We should check behaviour on receiver stalls. */
1305
1306 if (status & RL_ISR_SYSTEM_ERR) {
1307 rl_reset(sc);
1308 rl_init_locked(sc);
1309 }
1310 }
1311}
1312#endif /* DEVICE_POLLING */
1313
1314static void
1315rl_intr(void *arg)
1316{
1317 struct rl_softc *sc = arg;
1318 struct ifnet *ifp = sc->rl_ifp;
1319 uint16_t status;
1320
1321 RL_LOCK(sc);
1322
1323 if (sc->suspended)
1324 goto done_locked;
1325
1326#ifdef DEVICE_POLLING
1327 if (ifp->if_capenable & IFCAP_POLLING)
1328 goto done_locked;
1329#endif
1330
1331 for (;;) {
1332 status = CSR_READ_2(sc, RL_ISR);
1333 /* If the card has gone away, the read returns 0xffff. */
1334 if (status == 0xffff)
1335 break;
1336 if (status != 0)
1337 CSR_WRITE_2(sc, RL_ISR, status);
1338 if ((status & RL_INTRS) == 0)
1339 break;
1340 if (status & RL_ISR_RX_OK)
1341 rl_rxeof(sc);
1342 if (status & RL_ISR_RX_ERR)
1343 rl_rxeof(sc);
1344 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1345 rl_txeof(sc);
1346 if (status & RL_ISR_SYSTEM_ERR) {
1347 rl_reset(sc);
1348 rl_init_locked(sc);
1349 }
1350 }
1351
1352 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1353 rl_start_locked(ifp);
1354
1355done_locked:
1356 RL_UNLOCK(sc);
1357}
1358
1359/*
1360 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1361 * pointers to the fragment pointers.
1362 */
1363static int
1364rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1365{
1366 struct mbuf *m_new = NULL;
1367
1368 RL_LOCK_ASSERT(sc);
1369
1370 /*
1371 * The RealTek is brain damaged and wants longword-aligned
1372 * TX buffers, plus we can only have one fragment buffer
1373 * per packet. We have to copy pretty much all the time.
1374 */
1375 m_new = m_defrag(m_head, M_DONTWAIT);
1376
1377 if (m_new == NULL) {
1378 m_freem(m_head);
1379 return (1);
1380 }
1381 m_head = m_new;
1382
1383 /* Pad frames to at least 60 bytes. */
1384 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1385 /*
1386 * Make security concious people happy: zero out the
1387 * bytes in the pad area, since we don't know what
1388 * this mbuf cluster buffer's previous user might
1389 * have left in it.
1390 */
1391 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1392 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1393 m_head->m_pkthdr.len +=
1394 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1395 m_head->m_len = m_head->m_pkthdr.len;
1396 }
1397
1398 RL_CUR_TXMBUF(sc) = m_head;
1399
1400 return (0);
1401}
1402
1403/*
1404 * Main transmit routine.
1405 */
1406static void
1407rl_start(struct ifnet *ifp)
1408{
1409 struct rl_softc *sc = ifp->if_softc;
1410
1411 RL_LOCK(sc);
1412 rl_start_locked(ifp);
1413 RL_UNLOCK(sc);
1414}
1415
1416static void
1417rl_start_locked(struct ifnet *ifp)
1418{
1419 struct rl_softc *sc = ifp->if_softc;
1420 struct mbuf *m_head = NULL;
1421
1422 RL_LOCK_ASSERT(sc);
1423
1424 while (RL_CUR_TXMBUF(sc) == NULL) {
1425
1426 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1427
1428 if (m_head == NULL)
1429 break;
1430
1431 if (rl_encap(sc, m_head))
1432 break;
1433
1434 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1435 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1436
1437 /* Transmit the frame. */
1438 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1439 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1440 mtod(RL_CUR_TXMBUF(sc), void *),
1441 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1442 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1443 BUS_DMASYNC_PREREAD);
1444 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1445 RL_TXTHRESH(sc->rl_txthresh) |
1446 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1447
1448 RL_INC(sc->rl_cdata.cur_tx);
1449
1450 /* Set a timeout in case the chip goes out to lunch. */
1451 sc->rl_watchdog_timer = 5;
1452 }
1453
1454 /*
1455 * We broke out of the loop because all our TX slots are
1456 * full. Mark the NIC as busy until it drains some of the
1457 * packets from the queue.
1458 */
1459 if (RL_CUR_TXMBUF(sc) != NULL)
1460 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1461}
1462
1463static void
1464rl_init(void *xsc)
1465{
1466 struct rl_softc *sc = xsc;
1467
1468 RL_LOCK(sc);
1469 rl_init_locked(sc);
1470 RL_UNLOCK(sc);
1471}
1472
1473static void
1474rl_init_locked(struct rl_softc *sc)
1475{
1476 struct ifnet *ifp = sc->rl_ifp;
1477 struct mii_data *mii;
1478 uint32_t rxcfg = 0;
1479 uint32_t eaddr[2];
1480
1481 RL_LOCK_ASSERT(sc);
1482
1483 mii = device_get_softc(sc->rl_miibus);
1484
1485 /*
1486 * Cancel pending I/O and free all RX/TX buffers.
1487 */
1488 rl_stop(sc);
1489
1490 /*
1491 * Init our MAC address. Even though the chipset
1492 * documentation doesn't mention it, we need to enter "Config
1493 * register write enable" mode to modify the ID registers.
1494 */
1495 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1496 bzero(eaddr, sizeof(eaddr));
1497 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1498 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1499 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1500 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1501
1502 /* Init the RX buffer pointer register. */
1503 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1504 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1505 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1506 BUS_DMASYNC_PREWRITE);
1507
1508 /* Init TX descriptors. */
1509 rl_list_tx_init(sc);
1510
1511 /*
1512 * Enable transmit and receive.
1513 */
1514 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1515
1516 /*
1517 * Set the initial TX and RX configuration.
1518 */
1519 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1520 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1521
1522 /* Set the individual bit to receive frames for this host only. */
1523 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1524 rxcfg |= RL_RXCFG_RX_INDIV;
1525
1526 /* If we want promiscuous mode, set the allframes bit. */
1527 if (ifp->if_flags & IFF_PROMISC) {
1528 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1529 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1530 } else {
1531 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1532 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1533 }
1534
1535 /* Set capture broadcast bit to capture broadcast frames. */
1536 if (ifp->if_flags & IFF_BROADCAST) {
1537 rxcfg |= RL_RXCFG_RX_BROAD;
1538 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1539 } else {
1540 rxcfg &= ~RL_RXCFG_RX_BROAD;
1541 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1542 }
1543
1544 /* Program the multicast filter, if necessary. */
1545 rl_setmulti(sc);
1546
1547#ifdef DEVICE_POLLING
1548 /* Disable interrupts if we are polling. */
1549 if (ifp->if_capenable & IFCAP_POLLING)
1550 CSR_WRITE_2(sc, RL_IMR, 0);
1551 else
1552#endif
1553 /* Enable interrupts. */
1554 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1555
1556 /* Set initial TX threshold */
1557 sc->rl_txthresh = RL_TX_THRESH_INIT;
1558
1559 /* Start RX/TX process. */
1560 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1561
1562 /* Enable receiver and transmitter. */
1563 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1564
1565 mii_mediachg(mii);
1566
1567 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1568
1569 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1570 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1571
1572 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1573}
1574
1575/*
1576 * Set media options.
1577 */
1578static int
1579rl_ifmedia_upd(struct ifnet *ifp)
1580{
1581 struct rl_softc *sc = ifp->if_softc;
1582 struct mii_data *mii;
1583
1584 mii = device_get_softc(sc->rl_miibus);
1585
1586 RL_LOCK(sc);
1587 mii_mediachg(mii);
1588 RL_UNLOCK(sc);
1589
1590 return (0);
1591}
1592
1593/*
1594 * Report current media status.
1595 */
1596static void
1597rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1598{
1599 struct rl_softc *sc = ifp->if_softc;
1600 struct mii_data *mii;
1601
1602 mii = device_get_softc(sc->rl_miibus);
1603
1604 RL_LOCK(sc);
1605 mii_pollstat(mii);
1606 RL_UNLOCK(sc);
1607 ifmr->ifm_active = mii->mii_media_active;
1608 ifmr->ifm_status = mii->mii_media_status;
1609}
1610
1611static int
1612rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1613{
1614 struct ifreq *ifr = (struct ifreq *)data;
1615 struct mii_data *mii;
1616 struct rl_softc *sc = ifp->if_softc;
1617 int error = 0;
1618
1619 switch (command) {
1620 case SIOCSIFFLAGS:
1621 RL_LOCK(sc);
1622 if (ifp->if_flags & IFF_UP) {
1623 rl_init_locked(sc);
1624 } else {
1625 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1626 rl_stop(sc);
1627 }
1628 RL_UNLOCK(sc);
1629 error = 0;
1630 break;
1631 case SIOCADDMULTI:
1632 case SIOCDELMULTI:
1633 RL_LOCK(sc);
1634 rl_setmulti(sc);
1635 RL_UNLOCK(sc);
1636 error = 0;
1637 break;
1638 case SIOCGIFMEDIA:
1639 case SIOCSIFMEDIA:
1640 mii = device_get_softc(sc->rl_miibus);
1641 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1642 break;
1643 case SIOCSIFCAP:
1644#ifdef DEVICE_POLLING
1645 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1646 !(ifp->if_capenable & IFCAP_POLLING)) {
1647 error = ether_poll_register(rl_poll, ifp);
1648 if (error)
1649 return(error);
1650 RL_LOCK(sc);
1651 /* Disable interrupts */
1652 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1653 ifp->if_capenable |= IFCAP_POLLING;
1654 RL_UNLOCK(sc);
1655 return (error);
1656
1657 }
1658 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1659 ifp->if_capenable & IFCAP_POLLING) {
1660 error = ether_poll_deregister(ifp);
1661 /* Enable interrupts. */
1662 RL_LOCK(sc);
1663 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1664 ifp->if_capenable &= ~IFCAP_POLLING;
1665 RL_UNLOCK(sc);
1666 return (error);
1667 }
1668#endif /* DEVICE_POLLING */
1669 break;
1670 default:
1671 error = ether_ioctl(ifp, command, data);
1672 break;
1673 }
1674
1675 return (error);
1676}
1677
1678static void
1679rl_watchdog(struct rl_softc *sc)
1680{
1681
1682 RL_LOCK_ASSERT(sc);
1683
1684 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1685 return;
1686
1687 device_printf(sc->rl_dev, "watchdog timeout\n");
1688 sc->rl_ifp->if_oerrors++;
1689
1690 rl_txeof(sc);
1691 rl_rxeof(sc);
1692 rl_init_locked(sc);
1693}
1694
1695/*
1696 * Stop the adapter and free any mbufs allocated to the
1697 * RX and TX lists.
1698 */
1699static void
1700rl_stop(struct rl_softc *sc)
1701{
1702 register int i;
1703 struct ifnet *ifp = sc->rl_ifp;
1704
1705 RL_LOCK_ASSERT(sc);
1706
1707 sc->rl_watchdog_timer = 0;
1708 callout_stop(&sc->rl_stat_callout);
1709 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1710
1711 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1712 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1713 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1714
1715 /*
1716 * Free the TX list buffers.
1717 */
1718 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1719 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1720 bus_dmamap_unload(sc->rl_tag,
1721 sc->rl_cdata.rl_tx_dmamap[i]);
1722 bus_dmamap_destroy(sc->rl_tag,
1723 sc->rl_cdata.rl_tx_dmamap[i]);
1724 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1725 sc->rl_cdata.rl_tx_chain[i] = NULL;
1726 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1727 0x0000000);
1728 }
1729 }
1730}
1731
1732/*
1733 * Device suspend routine. Stop the interface and save some PCI
1734 * settings in case the BIOS doesn't restore them properly on
1735 * resume.
1736 */
1737static int
1738rl_suspend(device_t dev)
1739{
1740 struct rl_softc *sc;
1741
1742 sc = device_get_softc(dev);
1743
1744 RL_LOCK(sc);
1745 rl_stop(sc);
1746 sc->suspended = 1;
1747 RL_UNLOCK(sc);
1748
1749 return (0);
1750}
1751
1752/*
1753 * Device resume routine. Restore some PCI settings in case the BIOS
1754 * doesn't, re-enable busmastering, and restart the interface if
1755 * appropriate.
1756 */
1757static int
1758rl_resume(device_t dev)
1759{
1760 struct rl_softc *sc;
1761 struct ifnet *ifp;
1762
1763 sc = device_get_softc(dev);
1764 ifp = sc->rl_ifp;
1765
1766 RL_LOCK(sc);
1767
1768 /* reinitialize interface if necessary */
1769 if (ifp->if_flags & IFF_UP)
1770 rl_init_locked(sc);
1771
1772 sc->suspended = 0;
1773
1774 RL_UNLOCK(sc);
1775
1776 return (0);
1777}
1778
1779/*
1780 * Stop all chip I/O so that the kernel's probe routines don't
1781 * get confused by errant DMAs when rebooting.
1782 */
1783static int
1784rl_shutdown(device_t dev)
1785{
1786 struct rl_softc *sc;
1787
1788 sc = device_get_softc(dev);
1789
1790 RL_LOCK(sc);
1791 rl_stop(sc);
1792 RL_UNLOCK(sc);
1793
1794 return (0);
1795}
| 149 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
150 "RealTek 8139 10/100BaseTX CardBus" },
151 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
152 "RealTek 8100 10/100BaseTX" },
153 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
154 "Accton MPX 5030/5038 10/100BaseTX" },
155 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
156 "Delta Electronics 8139 10/100BaseTX" },
157 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
158 "Addtron Technolgy 8139 10/100BaseTX" },
159 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
160 "D-Link DFE-530TX+ 10/100BaseTX" },
161 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
162 "D-Link DFE-690TXD 10/100BaseTX" },
163 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
164 "Nortel Networks 10/100BaseTX" },
165 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
166 "Corega FEther CB-TXD" },
167 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
168 "Corega FEtherII CB-TXD" },
169 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
170 "Peppercon AG ROL-F" },
171 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
172 "Planex FNW-3603-TX" },
173 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
174 "Planex FNW-3800-TX" },
175 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
176 "Compaq HNE-300" },
177 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
178 "LevelOne FPC-0106TX" },
179 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
180 "Edimax EP-4103DL CardBus" }
181};
182
183static int rl_attach(device_t);
184static int rl_detach(device_t);
185static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
186static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
187static void rl_eeprom_putbyte(struct rl_softc *, int);
188static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
189static int rl_encap(struct rl_softc *, struct mbuf * );
190static int rl_list_tx_init(struct rl_softc *);
191static int rl_ifmedia_upd(struct ifnet *);
192static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
193static int rl_ioctl(struct ifnet *, u_long, caddr_t);
194static void rl_intr(void *);
195static void rl_init(void *);
196static void rl_init_locked(struct rl_softc *sc);
197static void rl_mii_send(struct rl_softc *, uint32_t, int);
198static void rl_mii_sync(struct rl_softc *);
199static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
200static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
201static int rl_miibus_readreg(device_t, int, int);
202static void rl_miibus_statchg(device_t);
203static int rl_miibus_writereg(device_t, int, int, int);
204#ifdef DEVICE_POLLING
205static void rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
206static void rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
207#endif
208static int rl_probe(device_t);
209static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
210static void rl_reset(struct rl_softc *);
211static int rl_resume(device_t);
212static void rl_rxeof(struct rl_softc *);
213static void rl_setmulti(struct rl_softc *);
214static int rl_shutdown(device_t);
215static void rl_start(struct ifnet *);
216static void rl_start_locked(struct ifnet *);
217static void rl_stop(struct rl_softc *);
218static int rl_suspend(device_t);
219static void rl_tick(void *);
220static void rl_txeof(struct rl_softc *);
221static void rl_watchdog(struct rl_softc *);
222
223#ifdef RL_USEIOSPACE
224#define RL_RES SYS_RES_IOPORT
225#define RL_RID RL_PCI_LOIO
226#else
227#define RL_RES SYS_RES_MEMORY
228#define RL_RID RL_PCI_LOMEM
229#endif
230
231static device_method_t rl_methods[] = {
232 /* Device interface */
233 DEVMETHOD(device_probe, rl_probe),
234 DEVMETHOD(device_attach, rl_attach),
235 DEVMETHOD(device_detach, rl_detach),
236 DEVMETHOD(device_suspend, rl_suspend),
237 DEVMETHOD(device_resume, rl_resume),
238 DEVMETHOD(device_shutdown, rl_shutdown),
239
240 /* bus interface */
241 DEVMETHOD(bus_print_child, bus_generic_print_child),
242 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
243
244 /* MII interface */
245 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
246 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
247 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
248
249 { 0, 0 }
250};
251
252static driver_t rl_driver = {
253 "rl",
254 rl_methods,
255 sizeof(struct rl_softc)
256};
257
258static devclass_t rl_devclass;
259
260DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
261DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
262DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
263
264#define EE_SET(x) \
265 CSR_WRITE_1(sc, RL_EECMD, \
266 CSR_READ_1(sc, RL_EECMD) | x)
267
268#define EE_CLR(x) \
269 CSR_WRITE_1(sc, RL_EECMD, \
270 CSR_READ_1(sc, RL_EECMD) & ~x)
271
272static void
273rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
274{
275 struct rl_softc *sc = arg;
276
277 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
278}
279
280static void
281rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
282{
283 struct rl_softc *sc = arg;
284
285 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
286}
287
288/*
289 * Send a read command and address to the EEPROM, check for ACK.
290 */
291static void
292rl_eeprom_putbyte(struct rl_softc *sc, int addr)
293{
294 register int d, i;
295
296 d = addr | sc->rl_eecmd_read;
297
298 /*
299 * Feed in each bit and strobe the clock.
300 */
301 for (i = 0x400; i; i >>= 1) {
302 if (d & i) {
303 EE_SET(RL_EE_DATAIN);
304 } else {
305 EE_CLR(RL_EE_DATAIN);
306 }
307 DELAY(100);
308 EE_SET(RL_EE_CLK);
309 DELAY(150);
310 EE_CLR(RL_EE_CLK);
311 DELAY(100);
312 }
313}
314
315/*
316 * Read a word of data stored in the EEPROM at address 'addr.'
317 */
318static void
319rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
320{
321 register int i;
322 uint16_t word = 0;
323
324 /* Enter EEPROM access mode. */
325 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
326
327 /*
328 * Send address of word we want to read.
329 */
330 rl_eeprom_putbyte(sc, addr);
331
332 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
333
334 /*
335 * Start reading bits from EEPROM.
336 */
337 for (i = 0x8000; i; i >>= 1) {
338 EE_SET(RL_EE_CLK);
339 DELAY(100);
340 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
341 word |= i;
342 EE_CLR(RL_EE_CLK);
343 DELAY(100);
344 }
345
346 /* Turn off EEPROM access mode. */
347 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
348
349 *dest = word;
350}
351
352/*
353 * Read a sequence of words from the EEPROM.
354 */
355static void
356rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
357{
358 int i;
359 uint16_t word = 0, *ptr;
360
361 for (i = 0; i < cnt; i++) {
362 rl_eeprom_getword(sc, off + i, &word);
363 ptr = (uint16_t *)(dest + (i * 2));
364 if (swap)
365 *ptr = ntohs(word);
366 else
367 *ptr = word;
368 }
369}
370
371/*
372 * MII access routines are provided for the 8129, which
373 * doesn't have a built-in PHY. For the 8139, we fake things
374 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
375 * direct access PHY registers.
376 */
377#define MII_SET(x) \
378 CSR_WRITE_1(sc, RL_MII, \
379 CSR_READ_1(sc, RL_MII) | (x))
380
381#define MII_CLR(x) \
382 CSR_WRITE_1(sc, RL_MII, \
383 CSR_READ_1(sc, RL_MII) & ~(x))
384
385/*
386 * Sync the PHYs by setting data bit and strobing the clock 32 times.
387 */
388static void
389rl_mii_sync(struct rl_softc *sc)
390{
391 register int i;
392
393 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
394
395 for (i = 0; i < 32; i++) {
396 MII_SET(RL_MII_CLK);
397 DELAY(1);
398 MII_CLR(RL_MII_CLK);
399 DELAY(1);
400 }
401}
402
403/*
404 * Clock a series of bits through the MII.
405 */
406static void
407rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
408{
409 int i;
410
411 MII_CLR(RL_MII_CLK);
412
413 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
414 if (bits & i) {
415 MII_SET(RL_MII_DATAOUT);
416 } else {
417 MII_CLR(RL_MII_DATAOUT);
418 }
419 DELAY(1);
420 MII_CLR(RL_MII_CLK);
421 DELAY(1);
422 MII_SET(RL_MII_CLK);
423 }
424}
425
426/*
427 * Read an PHY register through the MII.
428 */
429static int
430rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
431{
432 int i, ack;
433
434 /* Set up frame for RX. */
435 frame->mii_stdelim = RL_MII_STARTDELIM;
436 frame->mii_opcode = RL_MII_READOP;
437 frame->mii_turnaround = 0;
438 frame->mii_data = 0;
439
440 CSR_WRITE_2(sc, RL_MII, 0);
441
442 /* Turn on data xmit. */
443 MII_SET(RL_MII_DIR);
444
445 rl_mii_sync(sc);
446
447 /* Send command/address info. */
448 rl_mii_send(sc, frame->mii_stdelim, 2);
449 rl_mii_send(sc, frame->mii_opcode, 2);
450 rl_mii_send(sc, frame->mii_phyaddr, 5);
451 rl_mii_send(sc, frame->mii_regaddr, 5);
452
453 /* Idle bit */
454 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
455 DELAY(1);
456 MII_SET(RL_MII_CLK);
457 DELAY(1);
458
459 /* Turn off xmit. */
460 MII_CLR(RL_MII_DIR);
461
462 /* Check for ack */
463 MII_CLR(RL_MII_CLK);
464 DELAY(1);
465 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
466 MII_SET(RL_MII_CLK);
467 DELAY(1);
468
469 /*
470 * Now try reading data bits. If the ack failed, we still
471 * need to clock through 16 cycles to keep the PHY(s) in sync.
472 */
473 if (ack) {
474 for(i = 0; i < 16; i++) {
475 MII_CLR(RL_MII_CLK);
476 DELAY(1);
477 MII_SET(RL_MII_CLK);
478 DELAY(1);
479 }
480 goto fail;
481 }
482
483 for (i = 0x8000; i; i >>= 1) {
484 MII_CLR(RL_MII_CLK);
485 DELAY(1);
486 if (!ack) {
487 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
488 frame->mii_data |= i;
489 DELAY(1);
490 }
491 MII_SET(RL_MII_CLK);
492 DELAY(1);
493 }
494
495fail:
496 MII_CLR(RL_MII_CLK);
497 DELAY(1);
498 MII_SET(RL_MII_CLK);
499 DELAY(1);
500
501 return (ack ? 1 : 0);
502}
503
504/*
505 * Write to a PHY register through the MII.
506 */
507static int
508rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
509{
510
511 /* Set up frame for TX. */
512 frame->mii_stdelim = RL_MII_STARTDELIM;
513 frame->mii_opcode = RL_MII_WRITEOP;
514 frame->mii_turnaround = RL_MII_TURNAROUND;
515
516 /* Turn on data output. */
517 MII_SET(RL_MII_DIR);
518
519 rl_mii_sync(sc);
520
521 rl_mii_send(sc, frame->mii_stdelim, 2);
522 rl_mii_send(sc, frame->mii_opcode, 2);
523 rl_mii_send(sc, frame->mii_phyaddr, 5);
524 rl_mii_send(sc, frame->mii_regaddr, 5);
525 rl_mii_send(sc, frame->mii_turnaround, 2);
526 rl_mii_send(sc, frame->mii_data, 16);
527
528 /* Idle bit. */
529 MII_SET(RL_MII_CLK);
530 DELAY(1);
531 MII_CLR(RL_MII_CLK);
532 DELAY(1);
533
534 /* Turn off xmit. */
535 MII_CLR(RL_MII_DIR);
536
537 return (0);
538}
539
540static int
541rl_miibus_readreg(device_t dev, int phy, int reg)
542{
543 struct rl_softc *sc;
544 struct rl_mii_frame frame;
545 uint16_t rval = 0;
546 uint16_t rl8139_reg = 0;
547
548 sc = device_get_softc(dev);
549
550 if (sc->rl_type == RL_8139) {
551 /* Pretend the internal PHY is only at address 0 */
552 if (phy) {
553 return (0);
554 }
555 switch (reg) {
556 case MII_BMCR:
557 rl8139_reg = RL_BMCR;
558 break;
559 case MII_BMSR:
560 rl8139_reg = RL_BMSR;
561 break;
562 case MII_ANAR:
563 rl8139_reg = RL_ANAR;
564 break;
565 case MII_ANER:
566 rl8139_reg = RL_ANER;
567 break;
568 case MII_ANLPAR:
569 rl8139_reg = RL_LPAR;
570 break;
571 case MII_PHYIDR1:
572 case MII_PHYIDR2:
573 return (0);
574 /*
575 * Allow the rlphy driver to read the media status
576 * register. If we have a link partner which does not
577 * support NWAY, this is the register which will tell
578 * us the results of parallel detection.
579 */
580 case RL_MEDIASTAT:
581 rval = CSR_READ_1(sc, RL_MEDIASTAT);
582 return (rval);
583 default:
584 device_printf(sc->rl_dev, "bad phy register\n");
585 return (0);
586 }
587 rval = CSR_READ_2(sc, rl8139_reg);
588 return (rval);
589 }
590
591 bzero((char *)&frame, sizeof(frame));
592 frame.mii_phyaddr = phy;
593 frame.mii_regaddr = reg;
594 rl_mii_readreg(sc, &frame);
595
596 return (frame.mii_data);
597}
598
599static int
600rl_miibus_writereg(device_t dev, int phy, int reg, int data)
601{
602 struct rl_softc *sc;
603 struct rl_mii_frame frame;
604 uint16_t rl8139_reg = 0;
605
606 sc = device_get_softc(dev);
607
608 if (sc->rl_type == RL_8139) {
609 /* Pretend the internal PHY is only at address 0 */
610 if (phy) {
611 return (0);
612 }
613 switch (reg) {
614 case MII_BMCR:
615 rl8139_reg = RL_BMCR;
616 break;
617 case MII_BMSR:
618 rl8139_reg = RL_BMSR;
619 break;
620 case MII_ANAR:
621 rl8139_reg = RL_ANAR;
622 break;
623 case MII_ANER:
624 rl8139_reg = RL_ANER;
625 break;
626 case MII_ANLPAR:
627 rl8139_reg = RL_LPAR;
628 break;
629 case MII_PHYIDR1:
630 case MII_PHYIDR2:
631 return (0);
632 break;
633 default:
634 device_printf(sc->rl_dev, "bad phy register\n");
635 return (0);
636 }
637 CSR_WRITE_2(sc, rl8139_reg, data);
638 return (0);
639 }
640
641 bzero((char *)&frame, sizeof(frame));
642 frame.mii_phyaddr = phy;
643 frame.mii_regaddr = reg;
644 frame.mii_data = data;
645 rl_mii_writereg(sc, &frame);
646
647 return (0);
648}
649
650static void
651rl_miibus_statchg(device_t dev)
652{
653}
654
655/*
656 * Program the 64-bit multicast hash filter.
657 */
658static void
659rl_setmulti(struct rl_softc *sc)
660{
661 struct ifnet *ifp = sc->rl_ifp;
662 int h = 0;
663 uint32_t hashes[2] = { 0, 0 };
664 struct ifmultiaddr *ifma;
665 uint32_t rxfilt;
666 int mcnt = 0;
667
668 RL_LOCK_ASSERT(sc);
669
670 rxfilt = CSR_READ_4(sc, RL_RXCFG);
671
672 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
673 rxfilt |= RL_RXCFG_RX_MULTI;
674 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
675 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
676 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
677 return;
678 }
679
680 /* first, zot all the existing hash bits */
681 CSR_WRITE_4(sc, RL_MAR0, 0);
682 CSR_WRITE_4(sc, RL_MAR4, 0);
683
684 /* now program new ones */
685 IF_ADDR_LOCK(ifp);
686 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
687 if (ifma->ifma_addr->sa_family != AF_LINK)
688 continue;
689 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
690 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
691 if (h < 32)
692 hashes[0] |= (1 << h);
693 else
694 hashes[1] |= (1 << (h - 32));
695 mcnt++;
696 }
697 IF_ADDR_UNLOCK(ifp);
698
699 if (mcnt)
700 rxfilt |= RL_RXCFG_RX_MULTI;
701 else
702 rxfilt &= ~RL_RXCFG_RX_MULTI;
703
704 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
705 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
706 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
707}
708
709static void
710rl_reset(struct rl_softc *sc)
711{
712 register int i;
713
714 RL_LOCK_ASSERT(sc);
715
716 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
717
718 for (i = 0; i < RL_TIMEOUT; i++) {
719 DELAY(10);
720 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
721 break;
722 }
723 if (i == RL_TIMEOUT)
724 device_printf(sc->rl_dev, "reset never completed!\n");
725}
726
727/*
728 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
729 * IDs against our list and return a device name if we find a match.
730 */
731static int
732rl_probe(device_t dev)
733{
734 struct rl_type *t;
735 uint16_t devid, revid, vendor;
736 int i;
737
738 vendor = pci_get_vendor(dev);
739 devid = pci_get_device(dev);
740 revid = pci_get_revid(dev);
741
742 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
743 if (revid == 0x20) {
744 /* 8139C+, let re(4) take care of this device. */
745 return (ENXIO);
746 }
747 }
748 t = rl_devs;
749 for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) {
750 if (vendor == t->rl_vid && devid == t->rl_did) {
751 device_set_desc(dev, t->rl_name);
752 return (BUS_PROBE_DEFAULT);
753 }
754 }
755
756 return (ENXIO);
757}
758
759/*
760 * Attach the interface. Allocate softc structures, do ifmedia
761 * setup and ethernet/BPF attach.
762 */
763static int
764rl_attach(device_t dev)
765{
766 uint8_t eaddr[ETHER_ADDR_LEN];
767 uint16_t as[3];
768 struct ifnet *ifp;
769 struct rl_softc *sc;
770 struct rl_type *t;
771 int error = 0, i, rid;
772 int unit;
773 uint16_t rl_did = 0;
774
775 sc = device_get_softc(dev);
776 unit = device_get_unit(dev);
777 sc->rl_dev = dev;
778
779 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
780 MTX_DEF);
781 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
782
783 pci_enable_busmaster(dev);
784
785 /* Map control/status registers. */
786 rid = RL_RID;
787 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
788
789 if (sc->rl_res == NULL) {
790 device_printf(dev, "couldn't map ports/memory\n");
791 error = ENXIO;
792 goto fail;
793 }
794
795#ifdef notdef
796 /*
797 * Detect the Realtek 8139B. For some reason, this chip is very
798 * unstable when left to autoselect the media
799 * The best workaround is to set the device to the required
800 * media type or to set it to the 10 Meg speed.
801 */
802 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
803 device_printf(dev,
804"Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
805#endif
806
807 sc->rl_btag = rman_get_bustag(sc->rl_res);
808 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
809
810 /* Allocate interrupt */
811 rid = 0;
812 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
813 RF_SHAREABLE | RF_ACTIVE);
814
815 if (sc->rl_irq[0] == NULL) {
816 device_printf(dev, "couldn't map interrupt\n");
817 error = ENXIO;
818 goto fail;
819 }
820
821 /*
822 * Reset the adapter. Only take the lock here as it's needed in
823 * order to call rl_reset().
824 */
825 RL_LOCK(sc);
826 rl_reset(sc);
827 RL_UNLOCK(sc);
828
829 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
830 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
831 if (rl_did != 0x8129)
832 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
833
834 /*
835 * Get station address from the EEPROM.
836 */
837 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
838 for (i = 0; i < 3; i++) {
839 eaddr[(i * 2) + 0] = as[i] & 0xff;
840 eaddr[(i * 2) + 1] = as[i] >> 8;
841 }
842
843 /*
844 * Now read the exact device type from the EEPROM to find
845 * out if it's an 8129 or 8139.
846 */
847 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
848
849 t = rl_devs;
850 sc->rl_type = 0;
851 while(t->rl_name != NULL) {
852 if (rl_did == t->rl_did) {
853 sc->rl_type = t->rl_basetype;
854 break;
855 }
856 t++;
857 }
858
859 if (sc->rl_type == 0) {
860 device_printf(dev, "unknown device ID: %x\n", rl_did);
861 error = ENXIO;
862 goto fail;
863 }
864
865 /*
866 * Allocate the parent bus DMA tag appropriate for PCI.
867 */
868#define RL_NSEG_NEW 32
869 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
870 1, 0, /* alignment, boundary */
871 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
872 BUS_SPACE_MAXADDR, /* highaddr */
873 NULL, NULL, /* filter, filterarg */
874 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
875 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
876 BUS_DMA_ALLOCNOW, /* flags */
877 NULL, NULL, /* lockfunc, lockarg */
878 &sc->rl_parent_tag);
879 if (error)
880 goto fail;
881
882 /*
883 * Now allocate a tag for the DMA descriptor lists.
884 * All of our lists are allocated as a contiguous block
885 * of memory.
886 */
887 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
888 1, 0, /* alignment, boundary */
889 BUS_SPACE_MAXADDR, /* lowaddr */
890 BUS_SPACE_MAXADDR, /* highaddr */
891 NULL, NULL, /* filter, filterarg */
892 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */
893 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
894 BUS_DMA_ALLOCNOW, /* flags */
895 NULL, NULL, /* lockfunc, lockarg */
896 &sc->rl_tag);
897 if (error)
898 goto fail;
899
900 /*
901 * Now allocate a chunk of DMA-able memory based on the
902 * tag we just created.
903 */
904 error = bus_dmamem_alloc(sc->rl_tag,
905 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
906 &sc->rl_cdata.rl_rx_dmamap);
907 if (error) {
908 device_printf(dev, "no memory for list buffers!\n");
909 bus_dma_tag_destroy(sc->rl_tag);
910 sc->rl_tag = NULL;
911 goto fail;
912 }
913
914 /* Leave a few bytes before the start of the RX ring buffer. */
915 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
916 sc->rl_cdata.rl_rx_buf += sizeof(uint64_t);
917
918 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
919 if (ifp == NULL) {
920 device_printf(dev, "can not if_alloc()\n");
921 error = ENOSPC;
922 goto fail;
923 }
924
925 /* Do MII setup */
926 if (mii_phy_probe(dev, &sc->rl_miibus,
927 rl_ifmedia_upd, rl_ifmedia_sts)) {
928 device_printf(dev, "MII without any phy!\n");
929 error = ENXIO;
930 goto fail;
931 }
932
933 ifp->if_softc = sc;
934 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
935 ifp->if_mtu = ETHERMTU;
936 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
937 ifp->if_ioctl = rl_ioctl;
938 ifp->if_start = rl_start;
939 ifp->if_init = rl_init;
940 ifp->if_capabilities = IFCAP_VLAN_MTU;
941 ifp->if_capenable = ifp->if_capabilities;
942#ifdef DEVICE_POLLING
943 ifp->if_capabilities |= IFCAP_POLLING;
944#endif
945 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
946 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
947 IFQ_SET_READY(&ifp->if_snd);
948
949 /*
950 * Call MI attach routine.
951 */
952 ether_ifattach(ifp, eaddr);
953
954 /* Hook interrupt last to avoid having to lock softc */
955 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
956 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
957 if (error) {
958 device_printf(sc->rl_dev, "couldn't set up irq\n");
959 ether_ifdetach(ifp);
960 }
961
962fail:
963 if (error)
964 rl_detach(dev);
965
966 return (error);
967}
968
969/*
970 * Shutdown hardware and free up resources. This can be called any
971 * time after the mutex has been initialized. It is called in both
972 * the error case in attach and the normal detach case so it needs
973 * to be careful about only freeing resources that have actually been
974 * allocated.
975 */
976static int
977rl_detach(device_t dev)
978{
979 struct rl_softc *sc;
980 struct ifnet *ifp;
981
982 sc = device_get_softc(dev);
983 ifp = sc->rl_ifp;
984
985 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
986
987#ifdef DEVICE_POLLING
988 if (ifp->if_capenable & IFCAP_POLLING)
989 ether_poll_deregister(ifp);
990#endif
991 /* These should only be active if attach succeeded */
992 if (device_is_attached(dev)) {
993 RL_LOCK(sc);
994 rl_stop(sc);
995 RL_UNLOCK(sc);
996 callout_drain(&sc->rl_stat_callout);
997 ether_ifdetach(ifp);
998 }
999#if 0
1000 sc->suspended = 1;
1001#endif
1002 if (sc->rl_miibus)
1003 device_delete_child(dev, sc->rl_miibus);
1004 bus_generic_detach(dev);
1005
1006 if (sc->rl_intrhand[0])
1007 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1008 if (sc->rl_irq[0])
1009 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
1010 if (sc->rl_res)
1011 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1012
1013 if (ifp)
1014 if_free(ifp);
1015
1016 if (sc->rl_tag) {
1017 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1018 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
1019 sc->rl_cdata.rl_rx_dmamap);
1020 bus_dma_tag_destroy(sc->rl_tag);
1021 }
1022 if (sc->rl_parent_tag)
1023 bus_dma_tag_destroy(sc->rl_parent_tag);
1024
1025 mtx_destroy(&sc->rl_mtx);
1026
1027 return (0);
1028}
1029
1030/*
1031 * Initialize the transmit descriptors.
1032 */
1033static int
1034rl_list_tx_init(struct rl_softc *sc)
1035{
1036 struct rl_chain_data *cd;
1037 int i;
1038
1039 RL_LOCK_ASSERT(sc);
1040
1041 cd = &sc->rl_cdata;
1042 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1043 cd->rl_tx_chain[i] = NULL;
1044 CSR_WRITE_4(sc,
1045 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1046 }
1047
1048 sc->rl_cdata.cur_tx = 0;
1049 sc->rl_cdata.last_tx = 0;
1050
1051 return (0);
1052}
1053
1054/*
1055 * A frame has been uploaded: pass the resulting mbuf chain up to
1056 * the higher level protocols.
1057 *
1058 * You know there's something wrong with a PCI bus-master chip design
1059 * when you have to use m_devget().
1060 *
1061 * The receive operation is badly documented in the datasheet, so I'll
1062 * attempt to document it here. The driver provides a buffer area and
1063 * places its base address in the RX buffer start address register.
1064 * The chip then begins copying frames into the RX buffer. Each frame
1065 * is preceded by a 32-bit RX status word which specifies the length
1066 * of the frame and certain other status bits. Each frame (starting with
1067 * the status word) is also 32-bit aligned. The frame length is in the
1068 * first 16 bits of the status word; the lower 15 bits correspond with
1069 * the 'rx status register' mentioned in the datasheet.
1070 *
1071 * Note: to make the Alpha happy, the frame payload needs to be aligned
1072 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1073 * as the offset argument to m_devget().
1074 */
1075static void
1076rl_rxeof(struct rl_softc *sc)
1077{
1078 struct mbuf *m;
1079 struct ifnet *ifp = sc->rl_ifp;
1080 uint8_t *rxbufpos;
1081 int total_len = 0;
1082 int wrap = 0;
1083 uint32_t rxstat;
1084 uint16_t cur_rx;
1085 uint16_t limit;
1086 uint16_t max_bytes, rx_bytes = 0;
1087
1088 RL_LOCK_ASSERT(sc);
1089
1090 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1091 BUS_DMASYNC_POSTREAD);
1092
1093 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1094
1095 /* Do not try to read past this point. */
1096 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1097
1098 if (limit < cur_rx)
1099 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1100 else
1101 max_bytes = limit - cur_rx;
1102
1103 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1104#ifdef DEVICE_POLLING
1105 if (ifp->if_capenable & IFCAP_POLLING) {
1106 if (sc->rxcycles <= 0)
1107 break;
1108 sc->rxcycles--;
1109 }
1110#endif
1111 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1112 rxstat = le32toh(*(uint32_t *)rxbufpos);
1113
1114 /*
1115 * Here's a totally undocumented fact for you. When the
1116 * RealTek chip is in the process of copying a packet into
1117 * RAM for you, the length will be 0xfff0. If you spot a
1118 * packet header with this value, you need to stop. The
1119 * datasheet makes absolutely no mention of this and
1120 * RealTek should be shot for this.
1121 */
1122 total_len = rxstat >> 16;
1123 if (total_len == RL_RXSTAT_UNFINISHED)
1124 break;
1125
1126 if (!(rxstat & RL_RXSTAT_RXOK) ||
1127 total_len < ETHER_MIN_LEN ||
1128 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1129 ifp->if_ierrors++;
1130 rl_init_locked(sc);
1131 return;
1132 }
1133
1134 /* No errors; receive the packet. */
1135 rx_bytes += total_len + 4;
1136
1137 /*
1138 * XXX The RealTek chip includes the CRC with every
1139 * received frame, and there's no way to turn this
1140 * behavior off (at least, I can't find anything in
1141 * the manual that explains how to do it) so we have
1142 * to trim off the CRC manually.
1143 */
1144 total_len -= ETHER_CRC_LEN;
1145
1146 /*
1147 * Avoid trying to read more bytes than we know
1148 * the chip has prepared for us.
1149 */
1150 if (rx_bytes > max_bytes)
1151 break;
1152
1153 rxbufpos = sc->rl_cdata.rl_rx_buf +
1154 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1155 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1156 rxbufpos = sc->rl_cdata.rl_rx_buf;
1157
1158 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1159 if (total_len > wrap) {
1160 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1161 NULL);
1162 if (m == NULL) {
1163 ifp->if_ierrors++;
1164 } else {
1165 m_copyback(m, wrap, total_len - wrap,
1166 sc->rl_cdata.rl_rx_buf);
1167 }
1168 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1169 } else {
1170 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1171 NULL);
1172 if (m == NULL)
1173 ifp->if_ierrors++;
1174 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1175 }
1176
1177 /* Round up to 32-bit boundary. */
1178 cur_rx = (cur_rx + 3) & ~3;
1179 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1180
1181 if (m == NULL)
1182 continue;
1183
1184 ifp->if_ipackets++;
1185 RL_UNLOCK(sc);
1186 (*ifp->if_input)(ifp, m);
1187 RL_LOCK(sc);
1188 }
1189}
1190
1191/*
1192 * A frame was downloaded to the chip. It's safe for us to clean up
1193 * the list buffers.
1194 */
1195static void
1196rl_txeof(struct rl_softc *sc)
1197{
1198 struct ifnet *ifp = sc->rl_ifp;
1199 uint32_t txstat;
1200
1201 RL_LOCK_ASSERT(sc);
1202
1203 /*
1204 * Go through our tx list and free mbufs for those
1205 * frames that have been uploaded.
1206 */
1207 do {
1208 if (RL_LAST_TXMBUF(sc) == NULL)
1209 break;
1210 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1211 if (!(txstat & (RL_TXSTAT_TX_OK|
1212 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1213 break;
1214
1215 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1216
1217 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1218 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1219 m_freem(RL_LAST_TXMBUF(sc));
1220 RL_LAST_TXMBUF(sc) = NULL;
1221 /*
1222 * If there was a transmit underrun, bump the TX threshold.
1223 * Make sure not to overflow the 63 * 32byte we can address
1224 * with the 6 available bit.
1225 */
1226 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1227 (sc->rl_txthresh < 2016))
1228 sc->rl_txthresh += 32;
1229 if (txstat & RL_TXSTAT_TX_OK)
1230 ifp->if_opackets++;
1231 else {
1232 int oldthresh;
1233 ifp->if_oerrors++;
1234 if ((txstat & RL_TXSTAT_TXABRT) ||
1235 (txstat & RL_TXSTAT_OUTOFWIN))
1236 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1237 oldthresh = sc->rl_txthresh;
1238 /* error recovery */
1239 rl_reset(sc);
1240 rl_init_locked(sc);
1241 /* restore original threshold */
1242 sc->rl_txthresh = oldthresh;
1243 return;
1244 }
1245 RL_INC(sc->rl_cdata.last_tx);
1246 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1247 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1248
1249 if (RL_LAST_TXMBUF(sc) == NULL)
1250 sc->rl_watchdog_timer = 0;
1251 else if (sc->rl_watchdog_timer == 0)
1252 sc->rl_watchdog_timer = 5;
1253}
1254
1255static void
1256rl_tick(void *xsc)
1257{
1258 struct rl_softc *sc = xsc;
1259 struct mii_data *mii;
1260
1261 RL_LOCK_ASSERT(sc);
1262 mii = device_get_softc(sc->rl_miibus);
1263 mii_tick(mii);
1264
1265 rl_watchdog(sc);
1266
1267 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1268}
1269
1270#ifdef DEVICE_POLLING
1271static void
1272rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1273{
1274 struct rl_softc *sc = ifp->if_softc;
1275
1276 RL_LOCK(sc);
1277 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1278 rl_poll_locked(ifp, cmd, count);
1279 RL_UNLOCK(sc);
1280}
1281
1282static void
1283rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1284{
1285 struct rl_softc *sc = ifp->if_softc;
1286
1287 RL_LOCK_ASSERT(sc);
1288
1289 sc->rxcycles = count;
1290 rl_rxeof(sc);
1291 rl_txeof(sc);
1292
1293 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1294 rl_start_locked(ifp);
1295
1296 if (cmd == POLL_AND_CHECK_STATUS) {
1297 uint16_t status;
1298
1299 /* We should also check the status register. */
1300 status = CSR_READ_2(sc, RL_ISR);
1301 if (status == 0xffff)
1302 return;
1303 if (status != 0)
1304 CSR_WRITE_2(sc, RL_ISR, status);
1305
1306 /* XXX We should check behaviour on receiver stalls. */
1307
1308 if (status & RL_ISR_SYSTEM_ERR) {
1309 rl_reset(sc);
1310 rl_init_locked(sc);
1311 }
1312 }
1313}
1314#endif /* DEVICE_POLLING */
1315
1316static void
1317rl_intr(void *arg)
1318{
1319 struct rl_softc *sc = arg;
1320 struct ifnet *ifp = sc->rl_ifp;
1321 uint16_t status;
1322
1323 RL_LOCK(sc);
1324
1325 if (sc->suspended)
1326 goto done_locked;
1327
1328#ifdef DEVICE_POLLING
1329 if (ifp->if_capenable & IFCAP_POLLING)
1330 goto done_locked;
1331#endif
1332
1333 for (;;) {
1334 status = CSR_READ_2(sc, RL_ISR);
1335 /* If the card has gone away, the read returns 0xffff. */
1336 if (status == 0xffff)
1337 break;
1338 if (status != 0)
1339 CSR_WRITE_2(sc, RL_ISR, status);
1340 if ((status & RL_INTRS) == 0)
1341 break;
1342 if (status & RL_ISR_RX_OK)
1343 rl_rxeof(sc);
1344 if (status & RL_ISR_RX_ERR)
1345 rl_rxeof(sc);
1346 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1347 rl_txeof(sc);
1348 if (status & RL_ISR_SYSTEM_ERR) {
1349 rl_reset(sc);
1350 rl_init_locked(sc);
1351 }
1352 }
1353
1354 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1355 rl_start_locked(ifp);
1356
1357done_locked:
1358 RL_UNLOCK(sc);
1359}
1360
1361/*
1362 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1363 * pointers to the fragment pointers.
1364 */
1365static int
1366rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1367{
1368 struct mbuf *m_new = NULL;
1369
1370 RL_LOCK_ASSERT(sc);
1371
1372 /*
1373 * The RealTek is brain damaged and wants longword-aligned
1374 * TX buffers, plus we can only have one fragment buffer
1375 * per packet. We have to copy pretty much all the time.
1376 */
1377 m_new = m_defrag(m_head, M_DONTWAIT);
1378
1379 if (m_new == NULL) {
1380 m_freem(m_head);
1381 return (1);
1382 }
1383 m_head = m_new;
1384
1385 /* Pad frames to at least 60 bytes. */
1386 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1387 /*
1388 * Make security concious people happy: zero out the
1389 * bytes in the pad area, since we don't know what
1390 * this mbuf cluster buffer's previous user might
1391 * have left in it.
1392 */
1393 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1394 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1395 m_head->m_pkthdr.len +=
1396 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1397 m_head->m_len = m_head->m_pkthdr.len;
1398 }
1399
1400 RL_CUR_TXMBUF(sc) = m_head;
1401
1402 return (0);
1403}
1404
1405/*
1406 * Main transmit routine.
1407 */
1408static void
1409rl_start(struct ifnet *ifp)
1410{
1411 struct rl_softc *sc = ifp->if_softc;
1412
1413 RL_LOCK(sc);
1414 rl_start_locked(ifp);
1415 RL_UNLOCK(sc);
1416}
1417
1418static void
1419rl_start_locked(struct ifnet *ifp)
1420{
1421 struct rl_softc *sc = ifp->if_softc;
1422 struct mbuf *m_head = NULL;
1423
1424 RL_LOCK_ASSERT(sc);
1425
1426 while (RL_CUR_TXMBUF(sc) == NULL) {
1427
1428 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1429
1430 if (m_head == NULL)
1431 break;
1432
1433 if (rl_encap(sc, m_head))
1434 break;
1435
1436 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1437 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1438
1439 /* Transmit the frame. */
1440 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1441 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1442 mtod(RL_CUR_TXMBUF(sc), void *),
1443 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0);
1444 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1445 BUS_DMASYNC_PREREAD);
1446 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1447 RL_TXTHRESH(sc->rl_txthresh) |
1448 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1449
1450 RL_INC(sc->rl_cdata.cur_tx);
1451
1452 /* Set a timeout in case the chip goes out to lunch. */
1453 sc->rl_watchdog_timer = 5;
1454 }
1455
1456 /*
1457 * We broke out of the loop because all our TX slots are
1458 * full. Mark the NIC as busy until it drains some of the
1459 * packets from the queue.
1460 */
1461 if (RL_CUR_TXMBUF(sc) != NULL)
1462 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1463}
1464
1465static void
1466rl_init(void *xsc)
1467{
1468 struct rl_softc *sc = xsc;
1469
1470 RL_LOCK(sc);
1471 rl_init_locked(sc);
1472 RL_UNLOCK(sc);
1473}
1474
1475static void
1476rl_init_locked(struct rl_softc *sc)
1477{
1478 struct ifnet *ifp = sc->rl_ifp;
1479 struct mii_data *mii;
1480 uint32_t rxcfg = 0;
1481 uint32_t eaddr[2];
1482
1483 RL_LOCK_ASSERT(sc);
1484
1485 mii = device_get_softc(sc->rl_miibus);
1486
1487 /*
1488 * Cancel pending I/O and free all RX/TX buffers.
1489 */
1490 rl_stop(sc);
1491
1492 /*
1493 * Init our MAC address. Even though the chipset
1494 * documentation doesn't mention it, we need to enter "Config
1495 * register write enable" mode to modify the ID registers.
1496 */
1497 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1498 bzero(eaddr, sizeof(eaddr));
1499 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1500 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1501 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1502 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1503
1504 /* Init the RX buffer pointer register. */
1505 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1506 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0);
1507 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1508 BUS_DMASYNC_PREWRITE);
1509
1510 /* Init TX descriptors. */
1511 rl_list_tx_init(sc);
1512
1513 /*
1514 * Enable transmit and receive.
1515 */
1516 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1517
1518 /*
1519 * Set the initial TX and RX configuration.
1520 */
1521 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1522 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1523
1524 /* Set the individual bit to receive frames for this host only. */
1525 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1526 rxcfg |= RL_RXCFG_RX_INDIV;
1527
1528 /* If we want promiscuous mode, set the allframes bit. */
1529 if (ifp->if_flags & IFF_PROMISC) {
1530 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1531 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1532 } else {
1533 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1534 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1535 }
1536
1537 /* Set capture broadcast bit to capture broadcast frames. */
1538 if (ifp->if_flags & IFF_BROADCAST) {
1539 rxcfg |= RL_RXCFG_RX_BROAD;
1540 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1541 } else {
1542 rxcfg &= ~RL_RXCFG_RX_BROAD;
1543 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1544 }
1545
1546 /* Program the multicast filter, if necessary. */
1547 rl_setmulti(sc);
1548
1549#ifdef DEVICE_POLLING
1550 /* Disable interrupts if we are polling. */
1551 if (ifp->if_capenable & IFCAP_POLLING)
1552 CSR_WRITE_2(sc, RL_IMR, 0);
1553 else
1554#endif
1555 /* Enable interrupts. */
1556 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1557
1558 /* Set initial TX threshold */
1559 sc->rl_txthresh = RL_TX_THRESH_INIT;
1560
1561 /* Start RX/TX process. */
1562 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1563
1564 /* Enable receiver and transmitter. */
1565 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1566
1567 mii_mediachg(mii);
1568
1569 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1570
1571 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1572 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1573
1574 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1575}
1576
1577/*
1578 * Set media options.
1579 */
1580static int
1581rl_ifmedia_upd(struct ifnet *ifp)
1582{
1583 struct rl_softc *sc = ifp->if_softc;
1584 struct mii_data *mii;
1585
1586 mii = device_get_softc(sc->rl_miibus);
1587
1588 RL_LOCK(sc);
1589 mii_mediachg(mii);
1590 RL_UNLOCK(sc);
1591
1592 return (0);
1593}
1594
1595/*
1596 * Report current media status.
1597 */
1598static void
1599rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1600{
1601 struct rl_softc *sc = ifp->if_softc;
1602 struct mii_data *mii;
1603
1604 mii = device_get_softc(sc->rl_miibus);
1605
1606 RL_LOCK(sc);
1607 mii_pollstat(mii);
1608 RL_UNLOCK(sc);
1609 ifmr->ifm_active = mii->mii_media_active;
1610 ifmr->ifm_status = mii->mii_media_status;
1611}
1612
1613static int
1614rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1615{
1616 struct ifreq *ifr = (struct ifreq *)data;
1617 struct mii_data *mii;
1618 struct rl_softc *sc = ifp->if_softc;
1619 int error = 0;
1620
1621 switch (command) {
1622 case SIOCSIFFLAGS:
1623 RL_LOCK(sc);
1624 if (ifp->if_flags & IFF_UP) {
1625 rl_init_locked(sc);
1626 } else {
1627 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1628 rl_stop(sc);
1629 }
1630 RL_UNLOCK(sc);
1631 error = 0;
1632 break;
1633 case SIOCADDMULTI:
1634 case SIOCDELMULTI:
1635 RL_LOCK(sc);
1636 rl_setmulti(sc);
1637 RL_UNLOCK(sc);
1638 error = 0;
1639 break;
1640 case SIOCGIFMEDIA:
1641 case SIOCSIFMEDIA:
1642 mii = device_get_softc(sc->rl_miibus);
1643 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1644 break;
1645 case SIOCSIFCAP:
1646#ifdef DEVICE_POLLING
1647 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1648 !(ifp->if_capenable & IFCAP_POLLING)) {
1649 error = ether_poll_register(rl_poll, ifp);
1650 if (error)
1651 return(error);
1652 RL_LOCK(sc);
1653 /* Disable interrupts */
1654 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1655 ifp->if_capenable |= IFCAP_POLLING;
1656 RL_UNLOCK(sc);
1657 return (error);
1658
1659 }
1660 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1661 ifp->if_capenable & IFCAP_POLLING) {
1662 error = ether_poll_deregister(ifp);
1663 /* Enable interrupts. */
1664 RL_LOCK(sc);
1665 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1666 ifp->if_capenable &= ~IFCAP_POLLING;
1667 RL_UNLOCK(sc);
1668 return (error);
1669 }
1670#endif /* DEVICE_POLLING */
1671 break;
1672 default:
1673 error = ether_ioctl(ifp, command, data);
1674 break;
1675 }
1676
1677 return (error);
1678}
1679
1680static void
1681rl_watchdog(struct rl_softc *sc)
1682{
1683
1684 RL_LOCK_ASSERT(sc);
1685
1686 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1687 return;
1688
1689 device_printf(sc->rl_dev, "watchdog timeout\n");
1690 sc->rl_ifp->if_oerrors++;
1691
1692 rl_txeof(sc);
1693 rl_rxeof(sc);
1694 rl_init_locked(sc);
1695}
1696
1697/*
1698 * Stop the adapter and free any mbufs allocated to the
1699 * RX and TX lists.
1700 */
1701static void
1702rl_stop(struct rl_softc *sc)
1703{
1704 register int i;
1705 struct ifnet *ifp = sc->rl_ifp;
1706
1707 RL_LOCK_ASSERT(sc);
1708
1709 sc->rl_watchdog_timer = 0;
1710 callout_stop(&sc->rl_stat_callout);
1711 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1712
1713 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1714 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1715 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1716
1717 /*
1718 * Free the TX list buffers.
1719 */
1720 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1721 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1722 bus_dmamap_unload(sc->rl_tag,
1723 sc->rl_cdata.rl_tx_dmamap[i]);
1724 bus_dmamap_destroy(sc->rl_tag,
1725 sc->rl_cdata.rl_tx_dmamap[i]);
1726 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1727 sc->rl_cdata.rl_tx_chain[i] = NULL;
1728 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1729 0x0000000);
1730 }
1731 }
1732}
1733
1734/*
1735 * Device suspend routine. Stop the interface and save some PCI
1736 * settings in case the BIOS doesn't restore them properly on
1737 * resume.
1738 */
1739static int
1740rl_suspend(device_t dev)
1741{
1742 struct rl_softc *sc;
1743
1744 sc = device_get_softc(dev);
1745
1746 RL_LOCK(sc);
1747 rl_stop(sc);
1748 sc->suspended = 1;
1749 RL_UNLOCK(sc);
1750
1751 return (0);
1752}
1753
1754/*
1755 * Device resume routine. Restore some PCI settings in case the BIOS
1756 * doesn't, re-enable busmastering, and restart the interface if
1757 * appropriate.
1758 */
1759static int
1760rl_resume(device_t dev)
1761{
1762 struct rl_softc *sc;
1763 struct ifnet *ifp;
1764
1765 sc = device_get_softc(dev);
1766 ifp = sc->rl_ifp;
1767
1768 RL_LOCK(sc);
1769
1770 /* reinitialize interface if necessary */
1771 if (ifp->if_flags & IFF_UP)
1772 rl_init_locked(sc);
1773
1774 sc->suspended = 0;
1775
1776 RL_UNLOCK(sc);
1777
1778 return (0);
1779}
1780
1781/*
1782 * Stop all chip I/O so that the kernel's probe routines don't
1783 * get confused by errant DMAs when rebooting.
1784 */
1785static int
1786rl_shutdown(device_t dev)
1787{
1788 struct rl_softc *sc;
1789
1790 sc = device_get_softc(dev);
1791
1792 RL_LOCK(sc);
1793 rl_stop(sc);
1794 RL_UNLOCK(sc);
1795
1796 return (0);
1797}
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