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machdep.c (16359) machdep.c (17256)
1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *

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30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *

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30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 * $Id: machdep.c,v 1.192 1996/06/08 11:03:01 bde Exp $
38 * $Id: machdep.c,v 1.1.1.1 1996/06/14 10:04:41 asami Exp $
39 */
40
41#include "npx.h"
39 */
40
41#include "npx.h"
42#ifndef PC98
43#include "isa.h"
44#endif
45#include "opt_sysvipc.h"
46#include "opt_ddb.h"
47#include "opt_bounce.h"
48#include "opt_machdep.h"
49#include "opt_perfmon.h"
50
51#include <sys/param.h>
52#include <sys/systm.h>

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112#include <machine/devconf.h>
113#include <machine/bootinfo.h>
114#include <machine/md_var.h>
115#ifdef PERFMON
116#include <machine/perfmon.h>
117#endif
118
119#ifdef PC98
42#include "opt_sysvipc.h"
43#include "opt_ddb.h"
44#include "opt_bounce.h"
45#include "opt_machdep.h"
46#include "opt_perfmon.h"
47
48#include <sys/param.h>
49#include <sys/systm.h>

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109#include <machine/devconf.h>
110#include <machine/bootinfo.h>
111#include <machine/md_var.h>
112#ifdef PERFMON
113#include <machine/perfmon.h>
114#endif
115
116#ifdef PC98
120#include <pc98/pc98/pc98.h>
121#include <pc98/pc98/pc98_device.h>
117#include <pc98/pc98/pc98_device.h>
118#include <pc98/pc98/pc98_machdep.h>
122#else
119#else
123#include <i386/isa/isa.h>
124#include <i386/isa/isa_device.h>
125#include <i386/isa/rtc.h>
126#endif
127#include <machine/random.h>
128
129extern void init386 __P((int first));
130extern int ptrace_set_pc __P((struct proc *p, unsigned int addr));
131extern int ptrace_single_step __P((struct proc *p));
132extern int ptrace_write_u __P((struct proc *p, vm_offset_t off, int data));
133extern void dblfault_handler __P((void));
134
120#include <i386/isa/isa_device.h>
121#include <i386/isa/rtc.h>
122#endif
123#include <machine/random.h>
124
125extern void init386 __P((int first));
126extern int ptrace_set_pc __P((struct proc *p, unsigned int addr));
127extern int ptrace_single_step __P((struct proc *p));
128extern int ptrace_write_u __P((struct proc *p, vm_offset_t off, int data));
129extern void dblfault_handler __P((void));
130
135extern void i486_bzero __P((void *, size_t));
136extern void i586_bzero __P((void *, size_t));
137extern void i686_bzero __P((void *, size_t));
131extern void identifycpu(void); /* XXX header file */
132extern void earlysetcpuclass(void); /* same header file */
138
139static void cpu_startup __P((void *));
140SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
141
133
134static void cpu_startup __P((void *));
135SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
136
142static void identifycpu(void);
143
137
144char machine[] = "i386";
145SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "");
146
147static char cpu_model[128];
148SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, cpu_model, 0, "");
149
150struct kern_devconf kdc_cpu0 = {
151 0, 0, 0, /* filled in by dev_attach */
152 "cpu", 0, { MDDT_CPU },
153 0, 0, 0, CPU_EXTERNALLEN,
154 0, /* CPU has no parent */
155 0, /* no parentdata */
156 DC_BUSY, /* the CPU is always busy */
157 cpu_model, /* no sense in duplication */
158 DC_CLS_CPU /* class */
159};
160
161#ifndef PANIC_REBOOT_WAIT_TIME
162#define PANIC_REBOOT_WAIT_TIME 15 /* default to 15 seconds */
163#endif
164
165#ifdef BOUNCE_BUFFERS
166extern char *bouncememory;
167extern int maxbkva;
168#ifdef BOUNCEPAGES

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201
202SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
203 0, 0, sysctl_hw_usermem, "I", "");
204
205int boothowto = 0, bootverbose = 0, Maxmem = 0;
206static int badpages = 0;
207#ifdef PC98
208int Maxmem_under16M = 0;
138#ifndef PANIC_REBOOT_WAIT_TIME
139#define PANIC_REBOOT_WAIT_TIME 15 /* default to 15 seconds */
140#endif
141
142#ifdef BOUNCE_BUFFERS
143extern char *bouncememory;
144extern int maxbkva;
145#ifdef BOUNCEPAGES

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178
179SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
180 0, 0, sysctl_hw_usermem, "I", "");
181
182int boothowto = 0, bootverbose = 0, Maxmem = 0;
183static int badpages = 0;
184#ifdef PC98
185int Maxmem_under16M = 0;
209extern pt_entry_t *panic_kwin_pte;
210extern caddr_t panic_kwin;
211#endif
212long dumplo;
213extern int bootdev;
214
215vm_offset_t phys_avail[10];
216
217/* must be 2 less so 0 0 can signal end of chunks */
218#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(vm_offset_t)) - 2)
219
186#endif
187long dumplo;
188extern int bootdev;
189
190vm_offset_t phys_avail[10];
191
192/* must be 2 less so 0 0 can signal end of chunks */
193#define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(vm_offset_t)) - 2)
194
220int cpu_class = CPUCLASS_386; /* smallest common denominator */
221
222static void dumpsys __P((void));
223static void setup_netisrs __P((struct linker_set *)); /* XXX declare elsewhere */
224
225static vm_offset_t buffer_sva, buffer_eva;
226vm_offset_t clean_sva, clean_eva;
227static vm_offset_t pager_sva, pager_eva;
228extern struct linker_set netisr_set;
229

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253 avail_end + i * PAGE_SIZE,
254 VM_PROT_ALL, TRUE);
255 msgbufmapped = 1;
256
257 /*
258 * Good {morning,afternoon,evening,night}.
259 */
260 printf(version);
195static void dumpsys __P((void));
196static void setup_netisrs __P((struct linker_set *)); /* XXX declare elsewhere */
197
198static vm_offset_t buffer_sva, buffer_eva;
199vm_offset_t clean_sva, clean_eva;
200static vm_offset_t pager_sva, pager_eva;
201extern struct linker_set netisr_set;
202

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226 avail_end + i * PAGE_SIZE,
227 VM_PROT_ALL, TRUE);
228 msgbufmapped = 1;
229
230 /*
231 * Good {morning,afternoon,evening,night}.
232 */
233 printf(version);
261 cpu_class = i386_cpus[cpu].cpu_class;
234 earlysetcpuclass();
262 startrtclock();
263 identifycpu();
235 startrtclock();
236 identifycpu();
237#ifdef PERFMON
238 perfmon_init();
239#endif
264 printf("real memory = %d (%dK bytes)\n", ptoa(Maxmem), ptoa(Maxmem) / 1024);
265 /*
266 * Display any holes after the first chunk of extended memory.
267 */
268 if (badpages != 0) {
269 int indx = 1;
270
271 /*

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494 const struct netisrtab *nit;
495
496 for(i = 0; ls->ls_items[i]; i++) {
497 nit = (const struct netisrtab *)ls->ls_items[i];
498 register_netisr(nit->nit_num, nit->nit_isr);
499 }
500}
501
240 printf("real memory = %d (%dK bytes)\n", ptoa(Maxmem), ptoa(Maxmem) / 1024);
241 /*
242 * Display any holes after the first chunk of extended memory.
243 */
244 if (badpages != 0) {
245 int indx = 1;
246
247 /*

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470 const struct netisrtab *nit;
471
472 for(i = 0; ls->ls_items[i]; i++) {
473 nit = (const struct netisrtab *)ls->ls_items[i];
474 register_netisr(nit->nit_num, nit->nit_isr);
475 }
476}
477
502static struct cpu_nameclass i386_cpus[] = {
503 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
504 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
505 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
506 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
507 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
508 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
509 { "Cy486DLC", CPUCLASS_486 }, /* CPU_486DLC */
510 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
511};
512
513static void
514identifycpu()
515{
516 printf("CPU: ");
517 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof cpu_model);
518
519#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
520 if (!strcmp(cpu_vendor,"GenuineIntel")) {
521 if ((cpu_id & 0xf00) > 3) {
522 cpu_model[0] = '\0';
523
524 switch (cpu_id & 0x3000) {
525 case 0x1000:
526 strcpy(cpu_model, "Overdrive ");
527 break;
528 case 0x2000:
529 strcpy(cpu_model, "Dual ");
530 break;
531 }
532
533 switch (cpu_id & 0xf00) {
534 case 0x400:
535 strcat(cpu_model, "i486 ");
536 break;
537 case 0x500:
538 strcat(cpu_model, "Pentium"); /* nb no space */
539 break;
540 case 0x600:
541 strcat(cpu_model, "Pentium Pro");
542 break;
543 default:
544 strcat(cpu_model, "unknown");
545 break;
546 }
547
548 switch (cpu_id & 0xff0) {
549 case 0x400:
550 strcat(cpu_model, "DX"); break;
551 case 0x410:
552 strcat(cpu_model, "DX"); break;
553 case 0x420:
554 strcat(cpu_model, "SX"); break;
555 case 0x430:
556 strcat(cpu_model, "DX2"); break;
557 case 0x440:
558 strcat(cpu_model, "SL"); break;
559 case 0x450:
560 strcat(cpu_model, "SX2"); break;
561 case 0x470:
562 strcat(cpu_model, "DX2 Write-Back Enhanced");
563 break;
564 case 0x480:
565 strcat(cpu_model, "DX4"); break;
566 break;
567 }
568 }
569 }
570#endif
571 printf("%s (", cpu_model);
572 switch(cpu_class) {
573 case CPUCLASS_286:
574 printf("286");
575 break;
576#if defined(I386_CPU)
577 case CPUCLASS_386:
578 printf("386");
579 break;
580#endif
581#if defined(I486_CPU)
582 case CPUCLASS_486:
583 printf("486");
584 bzero = i486_bzero;
585 break;
586#endif
587#if defined(I586_CPU)
588 case CPUCLASS_586:
589 printf("%d.%02d-MHz ",
590 ((100 * i586_ctr_rate) >> I586_CTR_RATE_SHIFT) / 100,
591 ((100 * i586_ctr_rate) >> I586_CTR_RATE_SHIFT) % 100);
592 printf("586");
593 break;
594#endif
595#if defined(I686_CPU)
596 case CPUCLASS_686:
597 printf("%d.%02d-MHz ",
598 ((100 * i586_ctr_rate) >> I586_CTR_RATE_SHIFT) / 100,
599 ((100 * i586_ctr_rate) >> I586_CTR_RATE_SHIFT) % 100);
600 printf("686");
601 break;
602#endif
603 default:
604 printf("unknown"); /* will panic below... */
605 }
606 printf("-class CPU)\n");
607#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
608 if(*cpu_vendor)
609 printf(" Origin = \"%s\"",cpu_vendor);
610 if(cpu_id)
611 printf(" Id = 0x%lx",cpu_id);
612
613 if (!strcmp(cpu_vendor, "GenuineIntel")) {
614 printf(" Stepping=%ld", cpu_id & 0xf);
615 if (cpu_high > 0) {
616 printf("\n Features=0x%b", cpu_feature,
617 "\020"
618 "\001FPU"
619 "\002VME"
620 "\003DE"
621 "\004PSE"
622 "\005TSC"
623 "\006MSR"
624 "\007PAE"
625 "\010MCE"
626 "\011CX8"
627 "\012APIC"
628 "\013<b10>"
629 "\014<b11>"
630 "\015MTRR"
631 "\016PGE"
632 "\017MCA"
633 "\020CMOV"
634 );
635 }
636 }
637 /* Avoid ugly blank lines: only print newline when we have to. */
638 if (*cpu_vendor || cpu_id)
639 printf("\n");
640#endif
641 /*
642 * Now that we have told the user what they have,
643 * let them know if that machine type isn't configured.
644 */
645 switch (cpu_class) {
646 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
647#if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
648#error This kernel is not configured for one of the supported CPUs
649#endif
650#if !defined(I386_CPU)
651 case CPUCLASS_386:
652#endif
653#if !defined(I486_CPU)
654 case CPUCLASS_486:
655#endif
656#if !defined(I586_CPU)
657 case CPUCLASS_586:
658#endif
659#if !defined(I686_CPU)
660 case CPUCLASS_686:
661#endif
662 panic("CPU class not configured");
663 default:
664 break;
665 }
666#ifdef PERFMON
667 perfmon_init();
668#endif
669 dev_attach(&kdc_cpu0);
670}
671
672/*
673 * Send an interrupt to process.
674 *
675 * Stack is set up to allow sigcode stored
676 * at top to call routine, followed by kcall
677 * to sigreturn routine below. After sigreturn
678 * resets the signal mask, the stack, and the
679 * frame pointer, it returns to the user

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879 (sigmask(SIGKILL)|sigmask(SIGCONT)|sigmask(SIGSTOP));
880 regs[tEBP] = scp->sc_fp;
881 regs[tESP] = scp->sc_sp;
882 regs[tEIP] = scp->sc_pc;
883 regs[tEFLAGS] = eflags;
884 return(EJUSTRETURN);
885}
886
478/*
479 * Send an interrupt to process.
480 *
481 * Stack is set up to allow sigcode stored
482 * at top to call routine, followed by kcall
483 * to sigreturn routine below. After sigreturn
484 * resets the signal mask, the stack, and the
485 * frame pointer, it returns to the user

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685 (sigmask(SIGKILL)|sigmask(SIGCONT)|sigmask(SIGSTOP));
686 regs[tEBP] = scp->sc_fp;
687 regs[tESP] = scp->sc_sp;
688 regs[tEIP] = scp->sc_pc;
689 regs[tEFLAGS] = eflags;
690 return(EJUSTRETURN);
691}
692
887#ifdef PC98
888/*
889 * disable screen saver
890 */
891extern int scrn_blanked;
892extern void (*current_saver)(int blank);
893
894static void pc98_disable_screen_saver(void)
895{
896 if (scrn_blanked)
897 (*current_saver)(FALSE);
898}
899
900
901/*
902 * change ralay on video card
903 */
904static void pc98_change_relay(void)
905{
906 /* mode register 2 */
907 outb(0x6a, 0x07); /* enable to change FF */
908 outb(0x6a, 0x8e);
909 outb(0x6a, 0x06); /* disable to change FF */
910 outb(0x7c, 0);
911 outb(0x68, 0x0f); /* display */
912
913 /* PWLB */
914 *(int *)panic_kwin_pte = (0xf0c00000 & PG_FRAME) | PG_V | PG_RW ;
915 pmap_update();
916 *(long *)panic_kwin = 0;
917 /* PowerWindow(C-Bus) */
918 outb(0x0dc | 0x600, 0); /* XXX */
919 /* PCHKB & PCSKB4 */
920 outb(0x6e68, 0);
921 /* PCSKB */
922 outb(0x6ee8, 0);
923 /* NEC-S3, Cirrus (local bus) */
924 outb(0xfaa, 3);
925 outb(0xfab, 1);
926 outb(0xfaa, 6);
927 outb(0xfab, 0xff);
928 outb(0xfaa, 7);
929 outb(0xfab, 0);
930 /* NEC-S3 (C-bus) */
931 outb(0xfa2, 3);
932 outb(0xfa3, 0);
933 /* GA-NB */
934 outb(0x40e1, 0xc2);
935 /* WAB-S & WAP */
936 outb(0x40e1, 0xfa);
937
938 /* stop G-GDC */
939 outb(0xa2, 0x0c);
940 /* XXX start T-GDC (which is true?)*/
941 outb(0x62, 0x69);
942 outb(0x62, 0x0d);
943}
944#endif
945
946
947static int waittime = -1;
948struct pcb dumppcb;
949
950__dead void
951boot(howto)
952 int howto;
953{
954 if (!cold && (howto & RB_NOSYNC) == 0 && waittime < 0) {
955 register struct buf *bp;
956 int iter, nbusy;
957
693static int waittime = -1;
694struct pcb dumppcb;
695
696__dead void
697boot(howto)
698 int howto;
699{
700 if (!cold && (howto & RB_NOSYNC) == 0 && waittime < 0) {
701 register struct buf *bp;
702 int iter, nbusy;
703
958#ifdef PC98
959 pc98_change_relay();
960 pc98_disable_screen_saver();
961#endif
962 waittime = 0;
963 printf("\nsyncing disks... ");
964
965 sync(&proc0, NULL, NULL);
966
967 for (iter = 0; iter < 20; iter++) {
968 nbusy = 0;
969 for (bp = &buf[nbuf]; --bp >= buf; ) {

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1046}
1047
1048/*
1049 * Magic number for savecore
1050 *
1051 * exported (symorder) and used at least by savecore(8)
1052 *
1053 */
704 waittime = 0;
705 printf("\nsyncing disks... ");
706
707 sync(&proc0, NULL, NULL);
708
709 for (iter = 0; iter < 20; iter++) {
710 nbusy = 0;
711 for (bp = &buf[nbuf]; --bp >= buf; ) {

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788}
789
790/*
791 * Magic number for savecore
792 *
793 * exported (symorder) and used at least by savecore(8)
794 *
795 */
1054u_long dumpmag = 0x8fca0101UL;
796static u_long const dumpmag = 0x8fca0101UL;
1055
1056static int dumpsize = 0; /* also for savecore */
1057
1058static int dodump = 1;
1059SYSCTL_INT(_machdep, OID_AUTO, do_dump, CTLFLAG_RW, &dodump, 0, "");
1060
1061/*
1062 * Doadump comes here after turning off memory management and

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1401
1402 atdevbase = ISA_HOLE_START + KERNBASE;
1403
1404 /*
1405 * Initialize the console before we print anything out.
1406 */
1407 cninit();
1408
797
798static int dumpsize = 0; /* also for savecore */
799
800static int dodump = 1;
801SYSCTL_INT(_machdep, OID_AUTO, do_dump, CTLFLAG_RW, &dodump, 0, "");
802
803/*
804 * Doadump comes here after turning off memory management and

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1143
1144 atdevbase = ISA_HOLE_START + KERNBASE;
1145
1146 /*
1147 * Initialize the console before we print anything out.
1148 */
1149 cninit();
1150
1151#ifdef PC98
1409 /*
1152 /*
1153 * Initialize DMAC
1154 */
1155 init_pc98_dmac();
1156#endif
1157
1158 /*
1410 * make gdt memory segments, the code segment goes up to end of the
1411 * page with etext in it, the data segment goes to the end of
1412 * the address space
1413 */
1414 /*
1415 * XXX text protection is temporarily (?) disabled. The limit was
1416 * i386_btop(round_page(etext)) - 1.
1417 */

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1502#ifdef DDB
1503 kdb_init();
1504 if (boothowto & RB_KDB)
1505 Debugger("Boot flags requested debugger");
1506#endif
1507
1508#ifdef PC98
1509#ifdef EPSON_MEMWIN
1159 * make gdt memory segments, the code segment goes up to end of the
1160 * page with etext in it, the data segment goes to the end of
1161 * the address space
1162 */
1163 /*
1164 * XXX text protection is temporarily (?) disabled. The limit was
1165 * i386_btop(round_page(etext)) - 1.
1166 */

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1251#ifdef DDB
1252 kdb_init();
1253 if (boothowto & RB_KDB)
1254 Debugger("Boot flags requested debugger");
1255#endif
1256
1257#ifdef PC98
1258#ifdef EPSON_MEMWIN
1510 if (pc98_machine_type & M_EPSON_PC98) {
1511 if (Maxmem > 3840) {
1512 if (Maxmem == Maxmem_under16M) {
1513 Maxmem = 3840;
1514 Maxmem_under16M = 3840;
1515 } else if (Maxmem_under16M > 3840) {
1516 Maxmem_under16M = 3840;
1517 }
1518 }
1519
1520 /* Disable 15MB-16MB caching */
1521 switch (epson_machine_id) {
1522 case 0x34: /* PC486HX */
1523 case 0x35: /* PC486HG */
1524 case 0x3B: /* PC486HA */
1525 /* Cache control start */
1526 outb(0x43f, 0x42);
1527 outw(0xc40, 0x0033);
1528
1529 /* Disable 0xF00000-0xFFFFFF */
1530 outb(0xc48, 0x49); outb(0xc4c, 0x00);
1531 outb(0xc48, 0x48); outb(0xc4c, 0xf0);
1532 outb(0xc48, 0x4d); outb(0xc4c, 0x00);
1533 outb(0xc48, 0x4c); outb(0xc4c, 0xff);
1534 outb(0xc48, 0x4f); outb(0xc4c, 0x00);
1535
1536 /* Cache control end */
1537 outb(0x43f, 0x40);
1538 break;
1539
1540 case 0x2B: /* PC486GR/GF */
1541 case 0x30: /* PC486P */
1542 case 0x31: /* PC486GRSuper */
1543 case 0x32: /* PC486GR+ */
1544 case 0x37: /* PC486SE */
1545 case 0x38: /* PC486SR */
1546 /* Disable 0xF00000-0xFFFFFF */
1547 outb(0x43f, 0x42);
1548 outb(0x467, 0xe0);
1549 outb(0x567, 0xd8);
1550
1551 outb(0x43f, 0x40);
1552 outb(0x467, 0xe0);
1553 outb(0x567, 0xe0);
1554 break;
1555 }
1556
1557 /* Disable 15MB-16MB RAM and enable memory window */
1558 outb(0x43b, inb(0x43b) & 0xfd); /* clear bit1 */
1559 }
1259 init_epson_memwin();
1560#endif
1561 biosbasemem = 640; /* 640KB */
1562 biosextmem = (Maxmem * PAGE_SIZE - 0x100000)/1024; /* extent memory */
1563#else /* IBM-PC */
1564 /* Use BIOS values stored in RTC CMOS RAM, since probing
1565 * breaks certain 386 AT relics.
1566 */
1567 biosbasemem = rtcin(RTC_BASELO)+ (rtcin(RTC_BASEHI)<<8);

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1618 * chop it to 15MB.
1619 */
1620 if ((pagesinext > 3840) && (pagesinext < 4096))
1621 pagesinext = 3840;
1622#endif
1623
1624 /*
1625 * Maxmem isn't the "maximum memory", it's one larger than the
1260#endif
1261 biosbasemem = 640; /* 640KB */
1262 biosextmem = (Maxmem * PAGE_SIZE - 0x100000)/1024; /* extent memory */
1263#else /* IBM-PC */
1264 /* Use BIOS values stored in RTC CMOS RAM, since probing
1265 * breaks certain 386 AT relics.
1266 */
1267 biosbasemem = rtcin(RTC_BASELO)+ (rtcin(RTC_BASEHI)<<8);

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1318 * chop it to 15MB.
1319 */
1320 if ((pagesinext > 3840) && (pagesinext < 4096))
1321 pagesinext = 3840;
1322#endif
1323
1324 /*
1325 * Maxmem isn't the "maximum memory", it's one larger than the
1626 * highest page of of the physical address space. It
1326 * highest page of the physical address space. It should be
1327 * called something like "Maxphyspage".
1627 */
1628 Maxmem = pagesinext + 0x100000/PAGE_SIZE;
1629
1630#ifdef MAXMEM
1631 Maxmem = MAXMEM/4;
1632#endif
1633
1634 /* call pmap initialization to make new kernel address space */

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1649 phys_avail[pa_indx] = ptoa(pagesinbase);/* memory up to the ISA hole */
1650 physmem = pagesinbase - 1;
1651 } else {
1652 /* point at first chunk end */
1653 pa_indx++;
1654 }
1655
1656#ifdef PC98
1328 */
1329 Maxmem = pagesinext + 0x100000/PAGE_SIZE;
1330
1331#ifdef MAXMEM
1332 Maxmem = MAXMEM/4;
1333#endif
1334
1335 /* call pmap initialization to make new kernel address space */

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1350 phys_avail[pa_indx] = ptoa(pagesinbase);/* memory up to the ISA hole */
1351 physmem = pagesinbase - 1;
1352 } else {
1353 /* point at first chunk end */
1354 pa_indx++;
1355 }
1356
1357#ifdef PC98
1657 /*
1658 * Certain 'CPU accelerator' supports over 16MB memory on
1659 * the machines whose BIOS doesn't store true size.
1660 * To support this, we don't trust BIOS values if Maxmem < 4096.
1661 */
1662 if (Maxmem < 4096) {
1663 for (target_page = ptoa(4096); /* 16MB */
1664 target_page < ptoa(32768); /* 128MB */
1665 target_page += 256 * PAGE_SIZE /* 1MB step */) {
1666 int tmp, page_bad = FALSE, OrigMaxmem = Maxmem;
1667
1668 *(int *)CMAP1 = PG_V | PG_RW | PG_N | target_page;
1669 pmap_update();
1670
1671 tmp = *(int *)CADDR1;
1672 /*
1673 * Test for alternating 1's and 0's
1674 */
1675 *(volatile int *)CADDR1 = 0xaaaaaaaa;
1676 if (*(volatile int *)CADDR1 != 0xaaaaaaaa) {
1677 page_bad = TRUE;
1678 }
1679 /*
1680 * Test for alternating 0's and 1's
1681 */
1682 *(volatile int *)CADDR1 = 0x55555555;
1683 if (*(volatile int *)CADDR1 != 0x55555555) {
1684 page_bad = TRUE;
1685 }
1686 /*
1687 * Test for all 1's
1688 */
1689 *(volatile int *)CADDR1 = 0xffffffff;
1690 if (*(volatile int *)CADDR1 != 0xffffffff) {
1691 page_bad = TRUE;
1692 }
1693 /*
1694 * Test for all 0's
1695 */
1696 *(volatile int *)CADDR1 = 0x0;
1697 if (*(volatile int *)CADDR1 != 0x0) {
1698 /*
1699 * test of page failed
1700 */
1701 page_bad = TRUE;
1702 }
1703 /*
1704 * Restore original value.
1705 */
1706 *(int *)CADDR1 = tmp;
1707 if (page_bad == TRUE) {
1708 if (target_page > ptoa(4096))
1709 Maxmem = atop(target_page);
1710 else
1711 Maxmem = OrigMaxmem;
1712
1713 break;
1714 }
1715 }
1716 *(int *)CMAP1 = 0;
1717 pmap_update();
1718
1719 /* XXX */
1720 if (Maxmem > 3840) {
1721 Maxmem_under16M = 3840;
1722 if (Maxmem < 4096) {
1723 Maxmem = 3840;
1724 }
1725 }
1726 }
1358#ifdef notyet
1359 init_cpu_accel_mem();
1727#endif
1360#endif
1361#endif
1728
1729 for (target_page = avail_start; target_page < ptoa(Maxmem); target_page += PAGE_SIZE) {
1730 int tmp, page_bad = FALSE;
1731
1732#ifdef PC98
1733 /* skip system area */
1734 if (target_page>=ptoa(Maxmem_under16M) &&
1735 target_page < ptoa(4096))

--- 333 unchanged lines hidden --- 		1362
1363 for (target_page = avail_start; target_page < ptoa(Maxmem); target_page += PAGE_SIZE) {
1364 int tmp, page_bad = FALSE;
1365
1366#ifdef PC98
1367 /* skip system area */
1368 if (target_page>=ptoa(Maxmem_under16M) &&
1369 target_page < ptoa(4096))

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