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sio.c (59493) sio.c (60472)
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 16 unchanged lines hidden (view full) ---

25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 16 unchanged lines hidden (view full) ---

25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/pc98/cbus/sio.c 59493 2000-04-22 15:12:52Z nyan $
33 * $FreeBSD: head/sys/pc98/cbus/sio.c 60472 2000-05-12 12:38:25Z nyan $
34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
35 * from: i386/isa sio.c,v 1.234
36 */
37
38#include "opt_comconsole.h"
39#include "opt_compat.h"
40#include "opt_ddb.h"
41#include "opt_sio.h"

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229#define COM_C_NOPROBE (0x40000)
230#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
231#define COM_C_IIR_TXRDYBUG (0x80000)
232#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
233#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
234
235#ifdef PC98
236#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
35 * from: i386/isa sio.c,v 1.234
36 */
37
38#include "opt_comconsole.h"
39#include "opt_compat.h"
40#include "opt_ddb.h"
41#include "opt_sio.h"

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229#define COM_C_NOPROBE (0x40000)
230#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
231#define COM_C_IIR_TXRDYBUG (0x80000)
232#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
233#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
234
235#ifdef PC98
236#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
237#else
238#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
239#endif
237#endif
238#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
240
239
240#define sio_getreg(com, off) \
241 (bus_space_read_1((com)->bst, (com)->bsh, (off)))
242#define sio_setreg(com, off, value) \
243 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value)))
244
241/*
242 * com state bits.
243 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
244 * than the other bits so that they can be tested as a group without masking
245 * off the low bits.
246 *
247 * The following com and tty flags correspond closely:
248 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and

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331 u_char *ihighwater; /* threshold in input buffer */
332 u_char *iptr; /* next free spot in input buffer */
333 int ibufsize; /* size of ibuf (not include error bytes) */
334 int ierroff; /* offset of error bytes in ibuf */
335
336 struct lbq obufq; /* head of queue of output buffers */
337 struct lbq obufs[2]; /* output buffers */
338
245/*
246 * com state bits.
247 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
248 * than the other bits so that they can be tested as a group without masking
249 * off the low bits.
250 *
251 * The following com and tty flags correspond closely:
252 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and

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335 u_char *ihighwater; /* threshold in input buffer */
336 u_char *iptr; /* next free spot in input buffer */
337 int ibufsize; /* size of ibuf (not include error bytes) */
338 int ierroff; /* offset of error bytes in ibuf */
339
340 struct lbq obufq; /* head of queue of output buffers */
341 struct lbq obufs[2]; /* output buffers */
342
343 bus_space_tag_t bst;
344 bus_space_handle_t bsh;
345
339#ifdef PC98
340 Port_t cmd_port;
341 Port_t sts_port;
342 Port_t in_modem_port;
343 Port_t intr_ctrl_port;
346#ifdef PC98
347 Port_t cmd_port;
348 Port_t sts_port;
349 Port_t in_modem_port;
350 Port_t intr_ctrl_port;
351 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */
344 int intr_enable;
345 int pc98_prev_modem_status;
346 int pc98_modem_delta;
347 int modem_car_chg_timer;
348 int pc98_prev_siocmd;
349 int pc98_prev_siomod;
350 int modem_checking;
351 int pc98_if_type;
352
353 bool_t pc98_8251fifo;
354 bool_t pc98_8251fifo_enable;
355#endif /* PC98 */
356 Port_t data_port; /* i/o ports */
357#ifdef COM_ESP
358 Port_t esp_port;
359#endif
360 Port_t int_id_port;
352 int intr_enable;
353 int pc98_prev_modem_status;
354 int pc98_modem_delta;
355 int modem_car_chg_timer;
356 int pc98_prev_siocmd;
357 int pc98_prev_siomod;
358 int modem_checking;
359 int pc98_if_type;
360
361 bool_t pc98_8251fifo;
362 bool_t pc98_8251fifo_enable;
363#endif /* PC98 */
364 Port_t data_port; /* i/o ports */
365#ifdef COM_ESP
366 Port_t esp_port;
367#endif
368 Port_t int_id_port;
361 Port_t iobase;
362#ifdef PC98
363 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */
364#endif
365 Port_t modem_ctl_port;
366 Port_t line_status_port;
367 Port_t modem_status_port;
368 Port_t intr_ctl_port; /* Ports of IIR register */
369
370 struct tty *tp; /* cross reference */
371
372 /* Initial state. */

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550#define COM_INT_ENABLE splx(previpri);}
551#define IEN_TxFLAG IEN_Tx
552
553#define COM_CARRIER_DETECT_EMULATE 0
554#define PC98_CHECK_MODEM_INTERVAL (hz/10)
555#define DCD_OFF_TOLERANCE 2
556#define DCD_ON_RECOGNITION 2
557#define GET_IFTYPE(flags) ((flags >> 24) & 0x1f)
369 Port_t modem_ctl_port;
370 Port_t line_status_port;
371 Port_t modem_status_port;
372 Port_t intr_ctl_port; /* Ports of IIR register */
373
374 struct tty *tp; /* cross reference */
375
376 /* Initial state. */

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554#define COM_INT_ENABLE splx(previpri);}
555#define IEN_TxFLAG IEN_Tx
556
557#define COM_CARRIER_DETECT_EMULATE 0
558#define PC98_CHECK_MODEM_INTERVAL (hz/10)
559#define DCD_OFF_TOLERANCE 2
560#define DCD_ON_RECOGNITION 2
561#define GET_IFTYPE(flags) ((flags >> 24) & 0x1f)
562#define SET_IFTYPE(type) (type << 24)
558#define IS_8251(if_type) (!(if_type & 0x10))
559#define COM1_EXT_CLOCK 0x40000
560
561static void commint __P((dev_t dev));
562static void com_tiocm_set __P((struct com_s *com, int msr));
563static void com_tiocm_bis __P((struct com_s *com, int msr));
564static void com_tiocm_bic __P((struct com_s *com, int msr));
565static int com_tiocm_get __P((struct com_s *com));

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579static void pc98_i8251_set_cmd __P((struct com_s *com, int x));
580static void pc98_i8251_or_cmd __P((struct com_s *com, int x));
581static void pc98_i8251_clear_cmd __P((struct com_s *com, int x));
582static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x));
583static int pc98_check_if_type __P((device_t dev, struct siodev *iod));
584static int pc98_check_8251vfast __P((void));
585static int pc98_check_8251fifo __P((void));
586static void pc98_check_sysclock __P((void));
563#define IS_8251(if_type) (!(if_type & 0x10))
564#define COM1_EXT_CLOCK 0x40000
565
566static void commint __P((dev_t dev));
567static void com_tiocm_set __P((struct com_s *com, int msr));
568static void com_tiocm_bis __P((struct com_s *com, int msr));
569static void com_tiocm_bic __P((struct com_s *com, int msr));
570static int com_tiocm_get __P((struct com_s *com));

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584static void pc98_i8251_set_cmd __P((struct com_s *com, int x));
585static void pc98_i8251_or_cmd __P((struct com_s *com, int x));
586static void pc98_i8251_clear_cmd __P((struct com_s *com, int x));
587static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x));
588static int pc98_check_if_type __P((device_t dev, struct siodev *iod));
589static int pc98_check_8251vfast __P((void));
590static int pc98_check_8251fifo __P((void));
591static void pc98_check_sysclock __P((void));
587static int pc98_set_ioport __P((struct com_s *com));
592static void pc98_set_ioport __P((struct com_s *com));
588
589#define com_int_Tx_disable(com) \
590 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
591#define com_int_Tx_enable(com) \
592 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
593#define com_int_Rx_disable(com) \
594 pc98_disable_i8251_interrupt(com,IEN_Rx)
595#define com_int_Rx_enable(com) \

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791#define I8251F_data 0x130
792#define I8251F_lsr 0x132
793#define I8251F_msr 0x134
794#define I8251F_iir 0x136
795#define I8251F_fcr 0x138
796#define I8251F_div 0x13a
797
798
593
594#define com_int_Tx_disable(com) \
595 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
596#define com_int_Tx_enable(com) \
597 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
598#define com_int_Rx_disable(com) \
599 pc98_disable_i8251_interrupt(com,IEN_Rx)
600#define com_int_Rx_enable(com) \

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796#define I8251F_data 0x130
797#define I8251F_lsr 0x132
798#define I8251F_msr 0x134
799#define I8251F_iir 0x136
800#define I8251F_fcr 0x138
801#define I8251F_div 0x13a
802
803
804static bus_addr_t port_table_0[] =
805 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007};
806static bus_addr_t port_table_1[] =
807 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e};
808static bus_addr_t port_table_8[] =
809 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700};
810static bus_addr_t port_table_rsa[] =
811 {0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f};
812
799struct {
813struct {
800 char *name;
801 short irr_read;
802 short irr_write;
803 short port_shift;
804 short io_size;
814 char *name;
815 short irr_read;
816 short irr_write;
817 bus_addr_t *port_table;
805 struct speedtab *speedtab;
806} if_16550a_type[] = {
807 /* COM_IF_RSA98 */
818 struct speedtab *speedtab;
819} if_16550a_type[] = {
820 /* COM_IF_RSA98 */
808 { " (RSA-98)", -1, -1, 0, IO_COMSIZE, comspeedtab },
821 { " (RSA-98)", -1, -1, port_table_0, comspeedtab },
809 /* COM_IF_NS16550 */
822 /* COM_IF_NS16550 */
810 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
823 { "", -1, -1, port_table_0, comspeedtab },
811 /* COM_IF_SECOND_CCU */
824 /* COM_IF_SECOND_CCU */
812 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
825 { "", -1, -1, port_table_0, comspeedtab },
813 /* COM_IF_MC16550II */
826 /* COM_IF_MC16550II */
814 { " (MC16550II)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
827 { " (MC16550II)", -1, 0x1000, port_table_8, comspeedtab_mc16550 },
815 /* COM_IF_MCRS98 */
828 /* COM_IF_MCRS98 */
816 { " (MC-RS98)", -1, 0x1000, 8, 1, comspeedtab_mc16550 },
829 { " (MC-RS98)", -1, 0x1000, port_table_8, comspeedtab_mc16550 },
817 /* COM_IF_RSB3000 */
830 /* COM_IF_RSB3000 */
818 { " (RSB-3000)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
831 { " (RSB-3000)", 0xbf, -1, port_table_1, comspeedtab_rsb384 },
819 /* COM_IF_RSB384 */
832 /* COM_IF_RSB384 */
820 { " (RSB-384)", 0xbf, -1, 1, 1, comspeedtab_rsb384 },
833 { " (RSB-384)", 0xbf, -1, port_table_1, comspeedtab_rsb384 },
821 /* COM_IF_MODEM_CARD */
834 /* COM_IF_MODEM_CARD */
822 { "", -1, -1, 0, IO_COMSIZE, comspeedtab },
835 { "", -1, -1, port_table_0, comspeedtab },
823 /* COM_IF_RSA98III */
836 /* COM_IF_RSA98III */
824 { " (RSA-98III)", -1, -1, 0, 16, comspeedtab_rsa },
837 { " (RSA-98III)", -1, -1, port_table_rsa, comspeedtab_rsa },
825 /* COM_IF_ESP98 */
838 /* COM_IF_ESP98 */
826 { " (ESP98)", -1, -1, 1, 1, comspeedtab_mc16550 },
839 { " (ESP98)", -1, -1, port_table_1, comspeedtab_mc16550 },
827};
828#endif /* PC98 */
829
830#ifdef COM_ESP
831#ifdef PC98
832
833/* XXX configure this properly. */
834static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };

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945{
946 struct com_s *com;
947
948 com = (struct com_s *) device_get_softc(dev);
949 if (com == NULL) {
950 device_printf(dev, "NULL com in siounload\n");
951 return (0);
952 }
840};
841#endif /* PC98 */
842
843#ifdef COM_ESP
844#ifdef PC98
845
846/* XXX configure this properly. */
847static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };

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958{
959 struct com_s *com;
960
961 com = (struct com_s *) device_get_softc(dev);
962 if (com == NULL) {
963 device_printf(dev, "NULL com in siounload\n");
964 return (0);
965 }
953 if (com->iobase == 0) {
954 device_printf(dev, "already unloaded!\n");
955 return (0);
956 }
957 com->gone = 1;
958 if (com->irqres) {
959 bus_teardown_intr(dev, com->irqres, com->cookie);
960 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres);
961 }
962 if (com->ioportres)
963 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres);
964 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {

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1130 int logical_id;
1131#endif
1132 /* Check isapnp ids */
1133 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO)
1134 return (ENXIO);
1135#ifdef PC98
1136 logical_id = isa_get_logicalid(dev);
1137 if (logical_id == 0x0100e4a5) /* RSA-98III */
966 com->gone = 1;
967 if (com->irqres) {
968 bus_teardown_intr(dev, com->irqres, com->cookie);
969 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres);
970 }
971 if (com->ioportres)
972 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres);
973 if (com->tp && (com->tp->t_state & TS_ISOPEN)) {

--- 165 unchanged lines hidden (view full) ---

1139 int logical_id;
1140#endif
1141 /* Check isapnp ids */
1142 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO)
1143 return (ENXIO);
1144#ifdef PC98
1145 logical_id = isa_get_logicalid(dev);
1146 if (logical_id == 0x0100e4a5) /* RSA-98III */
1138 device_set_flags(dev, COM_IF_RSA98III << 24);
1147 device_set_flags(dev, SET_IFTYPE(COM_IF_RSA98III));
1139#endif
1140 return (sioprobe(dev, 0));
1141}
1142
1143static int
1144sioprobe(dev, xrid)
1145 device_t dev;
1146 int xrid;
1147{
1148#if 0
1149 static bool_t already_init;
1150 device_t xdev;
1151#endif
1148#endif
1149 return (sioprobe(dev, 0));
1150}
1151
1152static int
1153sioprobe(dev, xrid)
1154 device_t dev;
1155 int xrid;
1156{
1157#if 0
1158 static bool_t already_init;
1159 device_t xdev;
1160#endif
1161 struct com_s *com;
1152 bool_t failures[10];
1153 int fn;
1154 device_t idev;
1155 Port_t iobase;
1156 intrmask_t irqmap[4];
1157 intrmask_t irqs;
1158 u_char mcr_image;
1159 int result;
1160 u_long xirq;
1161 u_int flags = device_get_flags(dev);
1162 int rid;
1163 struct resource *port;
1164#ifdef PC98
1162 bool_t failures[10];
1163 int fn;
1164 device_t idev;
1165 Port_t iobase;
1166 intrmask_t irqmap[4];
1167 intrmask_t irqs;
1168 u_char mcr_image;
1169 int result;
1170 u_long xirq;
1171 u_int flags = device_get_flags(dev);
1172 int rid;
1173 struct resource *port;
1174#ifdef PC98
1165 int irqout=0;
1166 int tmp;
1175 int tmp;
1167 int port_shift = 0;
1168 struct siodev iod;
1176 struct siodev iod;
1169 Port_t rsabase;
1170#endif
1171
1177#endif
1178
1179#ifdef PC98
1180 iod.if_type = GET_IFTYPE(flags);
1181 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) &&
1182 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2))
1183 return ENXIO;
1184#endif
1185
1172 rid = xrid;
1173#ifdef PC98
1186 rid = xrid;
1187#ifdef PC98
1174 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1175 0, ~0, 1, RF_ACTIVE); /* XXX */
1188 if (IS_8251(iod.if_type)) {
1189 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1190 0, ~0, 1, RF_ACTIVE);
1191 } else if (isa_get_vendorid(dev)) {
1192 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1193 0, ~0, IO_COMSIZE, RF_ACTIVE);
1194 } else {
1195 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid,
1196 if_16550a_type[iod.if_type & 0x0f].port_table,
1197 IO_COMSIZE, RF_ACTIVE);
1198 }
1176#else
1177 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1178 0, ~0, IO_COMSIZE, RF_ACTIVE);
1179#endif
1180 if (!port)
1181 return (ENXIO);
1199#else
1200 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1201 0, ~0, IO_COMSIZE, RF_ACTIVE);
1202#endif
1203 if (!port)
1204 return (ENXIO);
1205#ifdef PC98
1206 if (!IS_8251(iod.if_type)) {
1207 if (isa_load_resourcev(port,
1208 if_16550a_type[iod.if_type & 0x0f].port_table,
1209 IO_COMSIZE) != 0) {
1210 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1211 return ENXIO;
1212 }
1213 }
1214#endif
1182
1215
1216 com = device_get_softc(dev);
1217 com->bst = rman_get_bustag(port);
1218 com->bsh = rman_get_bushandle(port);
1219
1183#if 0
1184 /*
1185 * XXX this is broken - when we are first called, there are no
1186 * previously configured IO ports. We could hard code
1187 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
1188 * This code has been doing nothing since the conversion since
1189 * "count" is zero the first time around.
1190 */

--- 13 unchanged lines hidden (view full) ---

1204 devclass_get_devices(sio_devclass, &devs, &count);
1205#ifdef PC98
1206 for (i = 0; i < count; i++) {
1207 xdev = devs[i];
1208 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0);
1209 xiftype = GET_IFTYPE(device_get_flags(xdev));
1210 if (device_is_enabled(xdev) && xioport > 0) {
1211 if (IS_8251(xiftype))
1220#if 0
1221 /*
1222 * XXX this is broken - when we are first called, there are no
1223 * previously configured IO ports. We could hard code
1224 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
1225 * This code has been doing nothing since the conversion since
1226 * "count" is zero the first time around.
1227 */

--- 13 unchanged lines hidden (view full) ---

1241 devclass_get_devices(sio_devclass, &devs, &count);
1242#ifdef PC98
1243 for (i = 0; i < count; i++) {
1244 xdev = devs[i];
1245 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0);
1246 xiftype = GET_IFTYPE(device_get_flags(xdev));
1247 if (device_is_enabled(xdev) && xioport > 0) {
1248 if (IS_8251(xiftype))
1212 outb(xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2);
1213 else {
1214 if (xiftype == COM_IF_RSA98III)
1215 xioport += 8;
1216 outb(xioport + (com_mcr << if_16550a_type[xiftype & 0x0f].port_shift), 0);
1217 }
1249 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2);
1250 else
1251 outb(xioport + if_16550a_type[xiftype & 0x0f].port_table[com_mcr], 0);
1218 }
1219 }
1220#else
1221 for (i = 0; i < count; i++) {
1222 xdev = devs[i];
1223 if (device_is_enabled(xdev) &&
1224 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
1225 NULL) == 0)

--- 69 unchanged lines hidden (view full) ---

1295 * Otherwise, prepare to set MCR_IENABLE in the mcr.
1296 * Point idev to the device struct giving the correct id_irq.
1297 * This is the struct for the master device if there is one.
1298 */
1299 idev = dev;
1300 mcr_image = MCR_IENABLE;
1301#ifdef COM_MULTIPORT
1302 if (COM_ISMULTIPORT(flags)) {
1252 }
1253 }
1254#else
1255 for (i = 0; i < count; i++) {
1256 xdev = devs[i];
1257 if (device_is_enabled(xdev) &&
1258 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
1259 NULL) == 0)

--- 69 unchanged lines hidden (view full) ---

1329 * Otherwise, prepare to set MCR_IENABLE in the mcr.
1330 * Point idev to the device struct giving the correct id_irq.
1331 * This is the struct for the master device if there is one.
1332 */
1333 idev = dev;
1334 mcr_image = MCR_IENABLE;
1335#ifdef COM_MULTIPORT
1336 if (COM_ISMULTIPORT(flags)) {
1337#ifndef PC98
1303 Port_t xiobase;
1304 u_long io;
1338 Port_t xiobase;
1339 u_long io;
1340#endif
1305
1306 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
1307 if (idev == NULL) {
1308 printf("sio%d: master device %d not configured\n",
1309 device_get_unit(dev), COM_MPMASTER(flags));
1310 idev = dev;
1311 }
1312#ifndef PC98

--- 17 unchanged lines hidden (view full) ---

1330
1331 bzero(failures, sizeof failures);
1332 iobase = rman_get_start(port);
1333
1334#ifdef PC98
1335 if (iod.if_type == COM_IF_RSA98III) {
1336 mcr_image = 0;
1337
1341
1342 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
1343 if (idev == NULL) {
1344 printf("sio%d: master device %d not configured\n",
1345 device_get_unit(dev), COM_MPMASTER(flags));
1346 idev = dev;
1347 }
1348#ifndef PC98

--- 17 unchanged lines hidden (view full) ---

1366
1367 bzero(failures, sizeof failures);
1368 iobase = rman_get_start(port);
1369
1370#ifdef PC98
1371 if (iod.if_type == COM_IF_RSA98III) {
1372 mcr_image = 0;
1373
1338 rsabase = iobase & 0xfff0;
1339 if (rsabase != iobase) {
1374 outb(iobase + rsa_msr, 0x04);
1375 outb(iobase + rsa_frr, 0x00);
1376 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) {
1340 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1341 return (ENXIO);
1342 }
1377 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1378 return (ENXIO);
1379 }
1343 iobase += 8;
1344
1345 outb(rsabase + rsa_msr, 0x04);
1346 outb(rsabase + rsa_frr, 0x00);
1347 if ((inb(rsabase + rsa_srr) & 0x36) != 0x36) {
1348 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1349 return (ENXIO);
1350 }
1351 outb(rsabase + rsa_ier, 0x00);
1352 outb(rsabase + rsa_frr, 0x00);
1353 outb(rsabase + rsa_tivsr, 0x00);
1354 outb(rsabase + rsa_tcr, 0x00);
1380 outb(iobase + rsa_ier, 0x00);
1381 outb(iobase + rsa_frr, 0x00);
1382 outb(iobase + rsa_tivsr, 0x00);
1383 outb(iobase + rsa_tcr, 0x00);
1355 }
1356
1357 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1358 if (tmp != -1) {
1359 /* MC16550II */
1384 }
1385
1386 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1387 if (tmp != -1) {
1388 /* MC16550II */
1389 int irqout;
1360 switch (isa_get_irq(idev)) {
1361 case 3: irqout = 4; break;
1362 case 5: irqout = 5; break;
1363 case 6: irqout = 6; break;
1364 case 12: irqout = 7; break;
1365 default:
1366 printf("sio%d: irq configuration error\n",
1367 device_get_unit(dev));
1368 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1369 return (ENXIO);
1370 }
1390 switch (isa_get_irq(idev)) {
1391 case 3: irqout = 4; break;
1392 case 5: irqout = 5; break;
1393 case 6: irqout = 6; break;
1394 case 12: irqout = 7; break;
1395 default:
1396 printf("sio%d: irq configuration error\n",
1397 device_get_unit(dev));
1398 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1399 return (ENXIO);
1400 }
1371 outb((isa_get_port(dev) & 0x00ff) | tmp, irqout);
1401 outb((iobase & 0x00ff) | tmp, irqout);
1372 }
1402 }
1373 port_shift = if_16550a_type[iod.if_type & 0x0f].port_shift;
1374#endif
1375
1376 /*
1377 * We don't want to get actual interrupts, just masked ones.
1378 * Interrupts from this line should already be masked in the ICU,
1379 * but mask them in the processor as well in case there are some
1380 * (misconfigured) shared interrupts.
1381 */

--- 11 unchanged lines hidden (view full) ---

1393 * We don't want to to wait long enough to drain at 2 bps.
1394 */
1395 if (iobase == siocniobase)
1396 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
1397 else {
1398#ifdef PC98
1399 tmp = ttspeedtab(SIO_TEST_SPEED,
1400 if_16550a_type[iod.if_type & 0x0f].speedtab);
1403#endif
1404
1405 /*
1406 * We don't want to get actual interrupts, just masked ones.
1407 * Interrupts from this line should already be masked in the ICU,
1408 * but mask them in the processor as well in case there are some
1409 * (misconfigured) shared interrupts.
1410 */

--- 11 unchanged lines hidden (view full) ---

1422 * We don't want to to wait long enough to drain at 2 bps.
1423 */
1424 if (iobase == siocniobase)
1425 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
1426 else {
1427#ifdef PC98
1428 tmp = ttspeedtab(SIO_TEST_SPEED,
1429 if_16550a_type[iod.if_type & 0x0f].speedtab);
1401 outb(iobase + (com_cfcr << port_shift), CFCR_DLAB|CFCR_8BITS);
1402 outb(iobase + (com_dlbl << port_shift), tmp & 0xff);
1403 outb(iobase + (com_dlbh << port_shift), (tmp >> 8) & 0xff);
1404 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1430 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
1431 sio_setreg(com, com_dlbl, tmp & 0xff);
1432 sio_setreg(com, com_dlbh, (tmp >> 8) & 0xff);
1433 sio_setreg(com, com_cfcr, CFCR_8BITS);
1405#else
1434#else
1406 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
1407 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
1408 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
1409 outb(iobase + com_cfcr, CFCR_8BITS);
1435 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
1436 sio_setreg(com, com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff);
1437 sio_setreg(com, com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8);
1438 sio_setreg(com, com_cfcr, CFCR_8BITS);
1410#endif
1411 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
1412 }
1413
1414 /*
1415 * Enable the interrupt gate and disable device interupts. This
1416 * should leave the device driving the interrupt line low and
1417 * guarantee an edge trigger if an interrupt can be generated.
1418 */
1419/* EXTRA DELAY? */
1439#endif
1440 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
1441 }
1442
1443 /*
1444 * Enable the interrupt gate and disable device interupts. This
1445 * should leave the device driving the interrupt line low and
1446 * guarantee an edge trigger if an interrupt can be generated.
1447 */
1448/* EXTRA DELAY? */
1420#ifdef PC98
1421 outb(iobase + (com_mcr << port_shift), mcr_image);
1422 outb(iobase + (com_ier << port_shift), 0);
1423#else
1424 outb(iobase + com_mcr, mcr_image);
1425 outb(iobase + com_ier, 0);
1426#endif
1449 sio_setreg(com, com_mcr, mcr_image);
1450 sio_setreg(com, com_ier, 0);
1427 DELAY(1000); /* XXX */
1428 irqmap[0] = isa_irq_pending();
1429
1430 /*
1431 * Attempt to set loopback mode so that we can send a null byte
1432 * without annoying any external device.
1433 */
1434/* EXTRA DELAY? */
1451 DELAY(1000); /* XXX */
1452 irqmap[0] = isa_irq_pending();
1453
1454 /*
1455 * Attempt to set loopback mode so that we can send a null byte
1456 * without annoying any external device.
1457 */
1458/* EXTRA DELAY? */
1435#ifdef PC98
1436 outb(iobase + (com_mcr << port_shift), mcr_image | MCR_LOOPBACK);
1437#else
1438 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK);
1439#endif
1459 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK);
1440
1441 /*
1442 * Attempt to generate an output interrupt. On 8250's, setting
1443 * IER_ETXRDY generates an interrupt independent of the current
1444 * setting and independent of whether the THR is empty. On 16450's,
1445 * setting IER_ETXRDY generates an interrupt independent of the
1446 * current setting. On 16550A's, setting IER_ETXRDY only
1447 * generates an interrupt when IER_ETXRDY is not already set.
1448 */
1460
1461 /*
1462 * Attempt to generate an output interrupt. On 8250's, setting
1463 * IER_ETXRDY generates an interrupt independent of the current
1464 * setting and independent of whether the THR is empty. On 16450's,
1465 * setting IER_ETXRDY generates an interrupt independent of the
1466 * current setting. On 16550A's, setting IER_ETXRDY only
1467 * generates an interrupt when IER_ETXRDY is not already set.
1468 */
1469 sio_setreg(com, com_ier, IER_ETXRDY);
1449#ifdef PC98
1470#ifdef PC98
1450 outb(iobase + (com_ier << port_shift), IER_ETXRDY);
1451 if (iod.if_type == COM_IF_RSA98III)
1471 if (iod.if_type == COM_IF_RSA98III)
1452 outb(rsabase + rsa_ier, 0x04);
1453#else
1454 outb(iobase + com_ier, IER_ETXRDY);
1455#endif /* PC98 */
1472 outb(iobase + rsa_ier, 0x04);
1473#endif
1456
1457 /*
1458 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1459 * an interrupt. They'd better generate one for actually doing
1460 * output. Loopback may be broken on the same incompatibles but
1461 * it's unlikely to do more than allow the null byte out.
1462 */
1474
1475 /*
1476 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1477 * an interrupt. They'd better generate one for actually doing
1478 * output. Loopback may be broken on the same incompatibles but
1479 * it's unlikely to do more than allow the null byte out.
1480 */
1463#ifdef PC98
1464 outb(iobase + (com_data << port_shift), 0);
1465#else
1466 outb(iobase + com_data, 0);
1467#endif
1481 sio_setreg(com, com_data, 0);
1468 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1469
1470 /*
1471 * Turn off loopback mode so that the interrupt gate works again
1472 * (MCR_IENABLE was hidden). This should leave the device driving
1473 * an interrupt line high. It doesn't matter if the interrupt
1474 * line oscillates while we are not looking at it, since interrupts
1475 * are disabled.
1476 */
1477/* EXTRA DELAY? */
1482 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1483
1484 /*
1485 * Turn off loopback mode so that the interrupt gate works again
1486 * (MCR_IENABLE was hidden). This should leave the device driving
1487 * an interrupt line high. It doesn't matter if the interrupt
1488 * line oscillates while we are not looking at it, since interrupts
1489 * are disabled.
1490 */
1491/* EXTRA DELAY? */
1478#ifdef PC98
1479 outb(iobase + (com_mcr << port_shift), mcr_image);
1480#else
1481 outb(iobase + com_mcr, mcr_image);
1482#endif /* PC98 */
1492 sio_setreg(com, com_mcr, mcr_image);
1483
1484 /*
1485 * Some pcmcia cards have the "TXRDY bug", so we check everyone
1486 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1487 */
1488 if (COM_NOPROBE(flags)) {
1489 /* Reading IIR register twice */
1490 for (fn = 0; fn < 2; fn ++) {
1491 DELAY(10000);
1493
1494 /*
1495 * Some pcmcia cards have the "TXRDY bug", so we check everyone
1496 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1497 */
1498 if (COM_NOPROBE(flags)) {
1499 /* Reading IIR register twice */
1500 for (fn = 0; fn < 2; fn ++) {
1501 DELAY(10000);
1492#ifdef PC98
1493 failures[6] = inb(iobase + (com_iir << port_shift));
1494#else
1495 failures[6] = inb(iobase + com_iir);
1496#endif
1502 failures[6] = sio_getreg(com, com_iir);
1497 }
1498 /* Check IIR_TXRDY clear ? */
1499 result = 0;
1500 if (failures[6] & IIR_TXRDY) {
1501 /* Nop, Double check with clearing IER */
1503 }
1504 /* Check IIR_TXRDY clear ? */
1505 result = 0;
1506 if (failures[6] & IIR_TXRDY) {
1507 /* Nop, Double check with clearing IER */
1502#ifdef PC98
1503 outb(iobase + (com_ier << port_shift), 0);
1504 if (inb(iobase + (com_iir << port_shift))
1505 & IIR_NOPEND) {
1506#else
1507 outb(iobase + com_ier, 0);
1508 if (inb(iobase + com_iir) & IIR_NOPEND) {
1509#endif
1508 sio_setreg(com, com_ier, 0);
1509 if (sio_getreg(com, com_iir) & IIR_NOPEND) {
1510 /* Ok. we're familia this gang */
1511 SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
1512 } else {
1513 /* Unknown, Just omit this chip.. XXX */
1514 result = ENXIO;
1515 }
1516 } else {
1517 /* OK. this is well-known guys */
1518 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
1519 }
1510 /* Ok. we're familia this gang */
1511 SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
1512 } else {
1513 /* Unknown, Just omit this chip.. XXX */
1514 result = ENXIO;
1515 }
1516 } else {
1517 /* OK. this is well-known guys */
1518 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
1519 }
1520#ifdef PC98
1521 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1522#else
1523 outb(iobase + com_cfcr, CFCR_8BITS);
1524#endif
1520 sio_setreg(com, com_cfcr, CFCR_8BITS);
1525 enable_intr();
1526 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1527 return (iobase == siocniobase ? 0 : result);
1528 }
1529
1530 /*
1531 * Check that
1532 * o the CFCR, IER and MCR in UART hold the values written to them
1533 * (the values happen to be all distinct - this is good for
1534 * avoiding false positive tests from bus echoes).
1535 * o an output interrupt is generated and its vector is correct.
1536 * o the interrupt goes away when the IIR in the UART is read.
1537 */
1538/* EXTRA DELAY? */
1521 enable_intr();
1522 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1523 return (iobase == siocniobase ? 0 : result);
1524 }
1525
1526 /*
1527 * Check that
1528 * o the CFCR, IER and MCR in UART hold the values written to them
1529 * (the values happen to be all distinct - this is good for
1530 * avoiding false positive tests from bus echoes).
1531 * o an output interrupt is generated and its vector is correct.
1532 * o the interrupt goes away when the IIR in the UART is read.
1533 */
1534/* EXTRA DELAY? */
1539#ifdef PC98
1540 failures[0] = inb(iobase + (com_cfcr << port_shift)) - CFCR_8BITS;
1541 failures[1] = inb(iobase + (com_ier << port_shift)) - IER_ETXRDY;
1542 failures[2] = inb(iobase + (com_mcr << port_shift)) - mcr_image;
1543#else
1544 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS;
1545 failures[1] = inb(iobase + com_ier) - IER_ETXRDY;
1546 failures[2] = inb(iobase + com_mcr) - mcr_image;
1547#endif
1535 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS;
1536 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY;
1537 failures[2] = sio_getreg(com, com_mcr) - mcr_image;
1548 DELAY(10000); /* Some internal modems need this time */
1549 irqmap[1] = isa_irq_pending();
1538 DELAY(10000); /* Some internal modems need this time */
1539 irqmap[1] = isa_irq_pending();
1540 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY;
1550#ifdef PC98
1541#ifdef PC98
1551 failures[4] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1552 - IIR_TXRDY;
1553 if (iod.if_type == COM_IF_RSA98III)
1542 if (iod.if_type == COM_IF_RSA98III)
1554 inb(rsabase + rsa_srr);
1555#else
1556 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY;
1543 inb(iobase + rsa_srr);
1557#endif
1558 DELAY(1000); /* XXX */
1559 irqmap[2] = isa_irq_pending();
1544#endif
1545 DELAY(1000); /* XXX */
1546 irqmap[2] = isa_irq_pending();
1547 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1560#ifdef PC98
1548#ifdef PC98
1561 failures[6] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1562 - IIR_NOPEND;
1563 if (iod.if_type == COM_IF_RSA98III)
1549 if (iod.if_type == COM_IF_RSA98III)
1564 inb(rsabase + rsa_srr);
1565#else
1566 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1550 inb(iobase + rsa_srr);
1567#endif
1568
1569 /*
1570 * Turn off all device interrupts and check that they go off properly.
1571 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1572 * the OUT2 output of the UART to
1573 * the ICU input. Closing the gate would give a floating ICU input
1574 * (unless there is another device driving it) and spurious interrupts.
1575 * (On the system that this was first tested on, the input floats high
1576 * and gives a (masked) interrupt as soon as the gate is closed.)
1577 */
1551#endif
1552
1553 /*
1554 * Turn off all device interrupts and check that they go off properly.
1555 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1556 * the OUT2 output of the UART to
1557 * the ICU input. Closing the gate would give a floating ICU input
1558 * (unless there is another device driving it) and spurious interrupts.
1559 * (On the system that this was first tested on, the input floats high
1560 * and gives a (masked) interrupt as soon as the gate is closed.)
1561 */
1562 sio_setreg(com, com_ier, 0);
1563 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1564 failures[7] = sio_getreg(com, com_ier);
1578#ifdef PC98
1565#ifdef PC98
1579 outb(iobase + (com_ier << port_shift), 0);
1580 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1581 failures[7] = inb(iobase + (com_ier << port_shift));
1582 if (iod.if_type == COM_IF_RSA98III)
1566 if (iod.if_type == COM_IF_RSA98III)
1583 outb(rsabase + rsa_ier, 0x00);
1584#else
1585 outb(iobase + com_ier, 0);
1586 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1587 failures[7] = inb(iobase + com_ier);
1567 outb(iobase + rsa_ier, 0x00);
1588#endif
1589 DELAY(1000); /* XXX */
1590 irqmap[3] = isa_irq_pending();
1568#endif
1569 DELAY(1000); /* XXX */
1570 irqmap[3] = isa_irq_pending();
1571 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1591#ifdef PC98
1572#ifdef PC98
1592 failures[9] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1593 - IIR_NOPEND;
1594 if (iod.if_type == COM_IF_RSA98III) {
1573 if (iod.if_type == COM_IF_RSA98III) {
1595 inb(rsabase + rsa_srr);
1596 outb(rsabase + rsa_frr, 0x00);
1574 inb(iobase + rsa_srr);
1575 outb(iobase + rsa_frr, 0x00);
1597 }
1576 }
1598#else
1599 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1600#endif
1601
1602 enable_intr();
1603
1604 irqs = irqmap[1] & ~irqmap[0];
1605 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
1606 ((1 << xirq) & irqs) == 0)
1607 printf(
1608 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
1609 device_get_unit(dev), xirq, irqs);
1610 if (bootverbose)
1611 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1612 device_get_unit(dev),
1613 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1614
1615 result = 0;
1616 for (fn = 0; fn < sizeof failures; ++fn)
1617 if (failures[fn]) {
1577#endif
1578
1579 enable_intr();
1580
1581 irqs = irqmap[1] & ~irqmap[0];
1582 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
1583 ((1 << xirq) & irqs) == 0)
1584 printf(
1585 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
1586 device_get_unit(dev), xirq, irqs);
1587 if (bootverbose)
1588 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1589 device_get_unit(dev),
1590 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1591
1592 result = 0;
1593 for (fn = 0; fn < sizeof failures; ++fn)
1594 if (failures[fn]) {
1618#ifdef PC98
1619 outb(iobase + (com_mcr << port_shift), 0);
1620#else
1621 outb(iobase + com_mcr, 0);
1622#endif
1595 sio_setreg(com, com_mcr, 0);
1623 result = ENXIO;
1624 if (bootverbose) {
1625 printf("sio%d: probe failed test(s):",
1626 device_get_unit(dev));
1627 for (fn = 0; fn < sizeof failures; ++fn)
1628 if (failures[fn])
1629 printf(" %d", fn);
1630 printf("\n");

--- 35 unchanged lines hidden (view full) ---

1666 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1667 dips = inb(esp_port + ESP_STATUS1);
1668#endif
1669
1670 /*
1671 * Bits 0,1 of dips say which COM port we are.
1672 */
1673#ifdef PC98
1596 result = ENXIO;
1597 if (bootverbose) {
1598 printf("sio%d: probe failed test(s):",
1599 device_get_unit(dev));
1600 for (fn = 0; fn < sizeof failures; ++fn)
1601 if (failures[fn])
1602 printf(" %d", fn);
1603 printf("\n");

--- 35 unchanged lines hidden (view full) ---

1639 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1640 dips = inb(esp_port + ESP_STATUS1);
1641#endif
1642
1643 /*
1644 * Bits 0,1 of dips say which COM port we are.
1645 */
1646#ifdef PC98
1674 if ((com->iobase & 0xff) == likely_com_ports[dips & 0x03])
1647 if ((rman_get_start(com->ioportres) & 0xff) ==
1648 likely_com_ports[dips & 0x03])
1675#else
1649#else
1676 if (com->iobase == likely_com_ports[dips & 0x03])
1650 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03])
1677#endif
1678 printf(" : ESP");
1679 else {
1680 printf(" esp_port has com %d\n", dips & 0x03);
1681 return (0);
1682 }
1683
1684 /*

--- 48 unchanged lines hidden (view full) ---

1733#endif
1734 Port_t iobase;
1735 int unit;
1736 u_int flags;
1737 int rid;
1738 struct resource *port;
1739 int ret;
1740#ifdef PC98
1651#endif
1652 printf(" : ESP");
1653 else {
1654 printf(" esp_port has com %d\n", dips & 0x03);
1655 return (0);
1656 }
1657
1658 /*

--- 48 unchanged lines hidden (view full) ---

1707#endif
1708 Port_t iobase;
1709 int unit;
1710 u_int flags;
1711 int rid;
1712 struct resource *port;
1713 int ret;
1714#ifdef PC98
1741 int port_shift = 0;
1742 u_char *obuf;
1743 u_long obufsize;
1715 u_char *obuf;
1716 u_long obufsize;
1717 int if_type = GET_IFTYPE(device_get_flags(dev));
1744#endif
1745
1746 rid = xrid;
1747#ifdef PC98
1718#endif
1719
1720 rid = xrid;
1721#ifdef PC98
1748 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1749 0, ~0, 1, RF_ACTIVE); /* XXX */
1722 if (IS_8251(if_type)) {
1723 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1724 0, ~0, 1, RF_ACTIVE);
1725 } else if (isa_get_vendorid(dev)) {
1726 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1727 0, ~0, IO_COMSIZE, RF_ACTIVE);
1728 } else {
1729 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid,
1730 if_16550a_type[if_type & 0x0f].port_table,
1731 IO_COMSIZE, RF_ACTIVE);
1732 }
1750#else
1751 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1752 0, ~0, IO_COMSIZE, RF_ACTIVE);
1753#endif
1754 if (!port)
1755 return (ENXIO);
1733#else
1734 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1735 0, ~0, IO_COMSIZE, RF_ACTIVE);
1736#endif
1737 if (!port)
1738 return (ENXIO);
1739#ifdef PC98
1740 if (!IS_8251(if_type)) {
1741 if (isa_load_resourcev(port,
1742 if_16550a_type[if_type & 0x0f].port_table,
1743 IO_COMSIZE) != 0) {
1744 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1745 return ENXIO;
1746 }
1747 }
1748#endif
1756
1757 iobase = rman_get_start(port);
1758 unit = device_get_unit(dev);
1759 com = device_get_softc(dev);
1760 flags = device_get_flags(dev);
1761
1762 if (unit >= sio_numunits)
1763 sio_numunits = unit + 1;
1764
1765#ifdef PC98
1766 obufsize = 256;
1749
1750 iobase = rman_get_start(port);
1751 unit = device_get_unit(dev);
1752 com = device_get_softc(dev);
1753 flags = device_get_flags(dev);
1754
1755 if (unit >= sio_numunits)
1756 sio_numunits = unit + 1;
1757
1758#ifdef PC98
1759 obufsize = 256;
1767 if (GET_IFTYPE(flags) == COM_IF_RSA98III) {
1768 iobase += 8;
1760 if (if_type == COM_IF_RSA98III)
1769 obufsize = 2048;
1761 obufsize = 2048;
1770 }
1771 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) {
1772 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1773 return ENXIO;
1774 }
1775 bzero(obuf, obufsize * 2);
1776#endif
1777
1778 /*

--- 4 unchanged lines hidden (view full) ---

1783 * o ier = 0.
1784 * Interrupts are only enabled when the line is open.
1785 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1786 * interrupt control register or the config specifies no irq.
1787 * Keeping MCR_DTR and MCR_RTS off might stop the external
1788 * device from sending before we are ready.
1789 */
1790 bzero(com, sizeof *com);
1762 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) {
1763 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1764 return ENXIO;
1765 }
1766 bzero(obuf, obufsize * 2);
1767#endif
1768
1769 /*

--- 4 unchanged lines hidden (view full) ---

1774 * o ier = 0.
1775 * Interrupts are only enabled when the line is open.
1776 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1777 * interrupt control register or the config specifies no irq.
1778 * Keeping MCR_DTR and MCR_RTS off might stop the external
1779 * device from sending before we are ready.
1780 */
1781 bzero(com, sizeof *com);
1791#ifdef PC98
1792 com->obufsize = obufsize;
1793 com->obuf1 = obuf;
1794 com->obuf2 = obuf + obufsize;
1795#endif
1796 com->unit = unit;
1797 com->ioportres = port;
1782 com->unit = unit;
1783 com->ioportres = port;
1784 com->bst = rman_get_bustag(port);
1785 com->bsh = rman_get_bushandle(port);
1798 com->cfcr_image = CFCR_8BITS;
1799 com->dtr_wait = 3 * hz;
1800 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1801 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
1802 com->tx_fifo_size = 1;
1786 com->cfcr_image = CFCR_8BITS;
1787 com->dtr_wait = 3 * hz;
1788 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1789 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
1790 com->tx_fifo_size = 1;
1791#ifdef PC98
1792 com->obufsize = obufsize;
1793 com->obuf1 = obuf;
1794 com->obuf2 = obuf + obufsize;
1795#endif
1803 com->obufs[0].l_head = com->obuf1;
1804 com->obufs[1].l_head = com->obuf2;
1805
1796 com->obufs[0].l_head = com->obuf1;
1797 com->obufs[1].l_head = com->obuf2;
1798
1806 com->iobase = iobase;
1807#ifdef PC98
1799#ifdef PC98
1808 com->pc98_if_type = GET_IFTYPE(flags);
1800 com->pc98_if_type = if_type;
1809
1801
1810 if (pc98_set_ioport(com) == -1) {
1811 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1802 if (IS_8251(if_type)) {
1803 pc98_set_ioport(com);
1812
1804
1813 com->data_port = iobase + (com_data << port_shift);
1814 com->int_id_port = iobase + (com_iir << port_shift);
1815 com->modem_ctl_port = iobase + (com_mcr << port_shift);
1805 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) {
1806 com->pc98_8251fifo = 1;
1807 com->pc98_8251fifo_enable = 0;
1808 }
1809 } else {
1810 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].port_table;
1811
1812 com->data_port = iobase + iat[com_data];
1813 com->int_id_port = iobase + iat[com_iir];
1814 com->modem_ctl_port = iobase + iat[com_mcr];
1816 com->mcr_image = inb(com->modem_ctl_port);
1815 com->mcr_image = inb(com->modem_ctl_port);
1817 com->line_status_port = iobase + (com_lsr << port_shift);
1818 com->modem_status_port = iobase + (com_msr << port_shift);
1819 com->intr_ctl_port = iobase + (com_ier << port_shift);
1816 com->line_status_port = iobase + iat[com_lsr];
1817 com->modem_status_port = iobase + iat[com_msr];
1818 com->intr_ctl_port = iobase + iat[com_ier];
1820 }
1819 }
1821 if (com->pc98_if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) {
1822 com->pc98_8251fifo = 1;
1823 com->pc98_8251fifo_enable = 0;
1824 }
1825#else /* not PC98 */
1826 com->data_port = iobase + com_data;
1827 com->int_id_port = iobase + com_iir;
1828 com->modem_ctl_port = iobase + com_mcr;
1829 com->mcr_image = inb(com->modem_ctl_port);
1830 com->line_status_port = iobase + com_lsr;
1831 com->modem_status_port = iobase + com_msr;
1832 com->intr_ctl_port = iobase + com_ier;

--- 48 unchanged lines hidden (view full) ---

1881#else
1882 if (!COM_IIR_TXRDYBUG(flags))
1883#endif
1884 {
1885 u_char scr;
1886 u_char scr1;
1887 u_char scr2;
1888
1820#else /* not PC98 */
1821 com->data_port = iobase + com_data;
1822 com->int_id_port = iobase + com_iir;
1823 com->modem_ctl_port = iobase + com_mcr;
1824 com->mcr_image = inb(com->modem_ctl_port);
1825 com->line_status_port = iobase + com_lsr;
1826 com->modem_status_port = iobase + com_msr;
1827 com->intr_ctl_port = iobase + com_ier;

--- 48 unchanged lines hidden (view full) ---

1876#else
1877 if (!COM_IIR_TXRDYBUG(flags))
1878#endif
1879 {
1880 u_char scr;
1881 u_char scr1;
1882 u_char scr2;
1883
1889 scr = inb(iobase + com_scr);
1890 outb(iobase + com_scr, 0xa5);
1891 scr1 = inb(iobase + com_scr);
1892 outb(iobase + com_scr, 0x5a);
1893 scr2 = inb(iobase + com_scr);
1894 outb(iobase + com_scr, scr);
1884 scr = sio_getreg(com, com_scr);
1885 sio_setreg(com, com_scr, 0xa5);
1886 scr1 = sio_getreg(com, com_scr);
1887 sio_setreg(com, com_scr, 0x5a);
1888 scr2 = sio_getreg(com, com_scr);
1889 sio_setreg(com, com_scr, scr);
1895 if (scr1 != 0xa5 || scr2 != 0x5a) {
1896 printf(" 8250");
1897 goto determined_type;
1898 }
1899 }
1900#endif /* !PC98 */
1901#ifdef PC98
1902 if (IS_8251(com->pc98_if_type)) {

--- 8 unchanged lines hidden (view full) ---

1911 printf(" (internal%s%s)",
1912 com->pc98_8251fifo ? " fifo" : "",
1913 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ?
1914 " v-fast" : "");
1915 } else {
1916 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
1917 }
1918 } else {
1890 if (scr1 != 0xa5 || scr2 != 0x5a) {
1891 printf(" 8250");
1892 goto determined_type;
1893 }
1894 }
1895#endif /* !PC98 */
1896#ifdef PC98
1897 if (IS_8251(com->pc98_if_type)) {

--- 8 unchanged lines hidden (view full) ---

1906 printf(" (internal%s%s)",
1907 com->pc98_8251fifo ? " fifo" : "",
1908 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ?
1909 " v-fast" : "");
1910 } else {
1911 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
1912 }
1913 } else {
1919 outb(iobase + (com_fifo << port_shift), FIFO_ENABLE | FIFO_RX_HIGH);
1920#else
1921 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1922#endif /* PC98 */
1914#endif /* PC98 */
1915 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1923 DELAY(100);
1924 com->st16650a = 0;
1925 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1926 case FIFO_RX_LOW:
1927 printf(" 16450");
1928 break;
1929 case FIFO_RX_MEDL:
1930 printf(" 16450?");

--- 18 unchanged lines hidden (view full) ---

1949 com->tx_fifo_size = COM_FIFOSIZE(flags);
1950 printf(" 16550A");
1951 }
1952#endif
1953 }
1954#ifdef PC98
1955 if (com->pc98_if_type == COM_IF_RSA98III) {
1956 com->tx_fifo_size = 2048;
1916 DELAY(100);
1917 com->st16650a = 0;
1918 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1919 case FIFO_RX_LOW:
1920 printf(" 16450");
1921 break;
1922 case FIFO_RX_MEDL:
1923 printf(" 16450?");

--- 18 unchanged lines hidden (view full) ---

1942 com->tx_fifo_size = COM_FIFOSIZE(flags);
1943 printf(" 16550A");
1944 }
1945#endif
1946 }
1947#ifdef PC98
1948 if (com->pc98_if_type == COM_IF_RSA98III) {
1949 com->tx_fifo_size = 2048;
1957 com->rsabase = isa_get_port(dev);
1950 com->rsabase = iobase;
1958 outb(com->rsabase + rsa_ier, 0x00);
1959 outb(com->rsabase + rsa_frr, 0x00);
1960 }
1961#endif
1962
1963#ifdef COM_ESP
1964#ifdef PC98
1965 if (com->pc98_if_type == COM_IF_ESP98)

--- 14 unchanged lines hidden (view full) ---

1980
1981 break;
1982 }
1983
1984#ifdef PC98
1985 if (com->pc98_if_type == COM_IF_RSB3000) {
1986 /* Set RSB-2000/3000 Extended Buffer mode. */
1987 u_char lcr;
1951 outb(com->rsabase + rsa_ier, 0x00);
1952 outb(com->rsabase + rsa_frr, 0x00);
1953 }
1954#endif
1955
1956#ifdef COM_ESP
1957#ifdef PC98
1958 if (com->pc98_if_type == COM_IF_ESP98)

--- 14 unchanged lines hidden (view full) ---

1973
1974 break;
1975 }
1976
1977#ifdef PC98
1978 if (com->pc98_if_type == COM_IF_RSB3000) {
1979 /* Set RSB-2000/3000 Extended Buffer mode. */
1980 u_char lcr;
1988 lcr = inb(iobase + (com_cfcr << port_shift));
1989 outb(iobase + (com_cfcr << port_shift), lcr | CFCR_DLAB);
1990 outb(iobase + (com_emr << port_shift), EMR_EXBUFF | EMR_EFMODE);
1991 outb(iobase + (com_cfcr << port_shift), lcr);
1981 lcr = sio_getreg(com, com_cfcr);
1982 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB);
1983 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE);
1984 sio_setreg(com, com_cfcr, lcr);
1992 }
1993#endif
1994
1995#ifdef COM_ESP
1996 if (com->esp) {
1997 /*
1998 * Set 16550 compatibility mode.
1999 * We don't use the ESP_MODE_SCALE bit to increase the

--- 37 unchanged lines hidden (view full) ---

2037
2038#ifdef PC98
2039 /* Set UART clock prescaler. */
2040 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
2041 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
2042#endif
2043 }
2044#endif /* COM_ESP */
1985 }
1986#endif
1987
1988#ifdef COM_ESP
1989 if (com->esp) {
1990 /*
1991 * Set 16550 compatibility mode.
1992 * We don't use the ESP_MODE_SCALE bit to increase the

--- 37 unchanged lines hidden (view full) ---

2030
2031#ifdef PC98
2032 /* Set UART clock prescaler. */
2033 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
2034 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
2035#endif
2036 }
2037#endif /* COM_ESP */
2038 sio_setreg(com, com_fifo, 0);
2045#ifdef PC98
2046 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
2039#ifdef PC98
2040 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
2047 outb(iobase + (com_fifo << port_shift), 0);
2048#else
2041#else
2049 outb(iobase + com_fifo, 0);
2050determined_type: ;
2051#endif
2052
2053#ifdef COM_MULTIPORT
2054 if (COM_ISMULTIPORT(flags)) {
2055 device_t masterdev;
2056
2057 com->multiport = TRUE;

--- 61 unchanged lines hidden (view full) ---

2119sioopen(dev, flag, mode, p)
2120 dev_t dev;
2121 int flag;
2122 int mode;
2123 struct proc *p;
2124{
2125 struct com_s *com;
2126 int error;
2042determined_type: ;
2043#endif
2044
2045#ifdef COM_MULTIPORT
2046 if (COM_ISMULTIPORT(flags)) {
2047 device_t masterdev;
2048
2049 com->multiport = TRUE;

--- 61 unchanged lines hidden (view full) ---

2111sioopen(dev, flag, mode, p)
2112 dev_t dev;
2113 int flag;
2114 int mode;
2115 struct proc *p;
2116{
2117 struct com_s *com;
2118 int error;
2127 Port_t iobase;
2128 int mynor;
2129 int s;
2130 struct tty *tp;
2131 int unit;
2119 int mynor;
2120 int s;
2121 struct tty *tp;
2122 int unit;
2132#ifdef PC98
2133 int port_shift = 0;
2134#endif
2135
2136 mynor = minor(dev);
2137 unit = MINOR_TO_UNIT(mynor);
2138 com = com_addr(unit);
2139 if (com == NULL)
2140 return (ENXIO);
2141 if (com->gone)
2142 return (ENXIO);
2143 if (mynor & CONTROL_MASK)
2144 return (0);
2145 tp = dev->si_tty = com->tp = ttymalloc(com->tp);
2146 s = spltty();
2123
2124 mynor = minor(dev);
2125 unit = MINOR_TO_UNIT(mynor);
2126 com = com_addr(unit);
2127 if (com == NULL)
2128 return (ENXIO);
2129 if (com->gone)
2130 return (ENXIO);
2131 if (mynor & CONTROL_MASK)
2132 return (0);
2133 tp = dev->si_tty = com->tp = ttymalloc(com->tp);
2134 s = spltty();
2147
2148#ifdef PC98
2149 if (!IS_8251(com->pc98_if_type))
2150 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2151#endif
2152 /*
2153 * We jump to this label after all non-interrupted sleeps to pick
2154 * up any changes of the device state.
2155 */
2156open_top:
2157 while (com->state & CS_DTR_OFF) {
2158 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
2159 if (com_addr(unit) == NULL)

--- 64 unchanged lines hidden (view full) ---

2224 outb(I8251F_fcr, CTRL8251F_ENABLE |
2225 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
2226 }
2227 }
2228#endif
2229 /*
2230 * XXX we should goto open_top if comparam() slept.
2231 */
2135 /*
2136 * We jump to this label after all non-interrupted sleeps to pick
2137 * up any changes of the device state.
2138 */
2139open_top:
2140 while (com->state & CS_DTR_OFF) {
2141 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0);
2142 if (com_addr(unit) == NULL)

--- 64 unchanged lines hidden (view full) ---

2207 outb(I8251F_fcr, CTRL8251F_ENABLE |
2208 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
2209 }
2210 }
2211#endif
2212 /*
2213 * XXX we should goto open_top if comparam() slept.
2214 */
2232 iobase = com->iobase;
2233 if (com->hasfifo) {
2234 /*
2235 * (Re)enable and drain fifos.
2236 *
2237 * Certain SMC chips cause problems if the fifos
2238 * are enabled while input is ready. Turn off the
2239 * fifo if necessary to clear the input. We test
2240 * the input ready bit after enabling the fifos
2241 * since we've already enabled them in comparam()
2242 * and to handle races between enabling and fresh
2243 * input.
2244 */
2245 while (TRUE) {
2215 if (com->hasfifo) {
2216 /*
2217 * (Re)enable and drain fifos.
2218 *
2219 * Certain SMC chips cause problems if the fifos
2220 * are enabled while input is ready. Turn off the
2221 * fifo if necessary to clear the input. We test
2222 * the input ready bit after enabling the fifos
2223 * since we've already enabled them in comparam()
2224 * and to handle races between enabling and fresh
2225 * input.
2226 */
2227 while (TRUE) {
2228 sio_setreg(com, com_fifo,
2229 FIFO_RCV_RST | FIFO_XMT_RST
2230 | com->fifo_image);
2246#ifdef PC98
2231#ifdef PC98
2247 outb(iobase + (com_fifo << port_shift),
2248 FIFO_RCV_RST | FIFO_XMT_RST
2249 | com->fifo_image);
2250 if (com->pc98_if_type == COM_IF_RSA98III)
2232 if (com->pc98_if_type == COM_IF_RSA98III)
2251 outb(com->rsabase + rsa_frr , 0x00);
2252#else
2253 outb(iobase + com_fifo,
2254 FIFO_RCV_RST | FIFO_XMT_RST
2255 | com->fifo_image);
2233 outb(com->rsabase + rsa_frr , 0x00);
2256#endif
2257 /*
2258 * XXX the delays are for superstitious
2259 * historical reasons. It must be less than
2260 * the character time at the maximum
2261 * supported speed (87 usec at 115200 bps
2262 * 8N1). Otherwise we might loop endlessly
2263 * if data is streaming in. We used to use
2264 * delays of 100. That usually worked
2265 * because DELAY(100) used to usually delay
2266 * for about 85 usec instead of 100.
2267 */
2268 DELAY(50);
2234#endif
2235 /*
2236 * XXX the delays are for superstitious
2237 * historical reasons. It must be less than
2238 * the character time at the maximum
2239 * supported speed (87 usec at 115200 bps
2240 * 8N1). Otherwise we might loop endlessly
2241 * if data is streaming in. We used to use
2242 * delays of 100. That usually worked
2243 * because DELAY(100) used to usually delay
2244 * for about 85 usec instead of 100.
2245 */
2246 DELAY(50);
2269#ifndef PC98
2270 if (!(inb(com->line_status_port) & LSR_RXRDY))
2271#else
2272 if (com->pc98_if_type == COM_IF_RSA98III
2273 ? !(inb(com->rsabase + rsa_srr) & 0x08)
2274 : !(inb(com->line_status_port) & LSR_RXRDY))
2275#endif
2276 break;
2277#ifdef PC98
2247#ifdef PC98
2278 outb(iobase + (com_fifo << port_shift), 0);
2248 if (com->pc98_if_type == COM_IF_RSA98III ?
2249 !(inb(com->rsabase + rsa_srr) & 0x08) :
2250 !(inb(com->line_status_port) & LSR_RXRDY))
2251 break;
2279#else
2252#else
2280 outb(iobase + com_fifo, 0);
2253 if (!(inb(com->line_status_port) & LSR_RXRDY))
2254 break;
2281#endif
2255#endif
2256 sio_setreg(com, com_fifo, 0);
2282 DELAY(50);
2283 (void) inb(com->data_port);
2284 }
2285 }
2286
2287 disable_intr();
2288#ifdef PC98
2289 if (IS_8251(com->pc98_if_type)) {

--- 37 unchanged lines hidden (view full) ---

2327 * the true carrier.
2328 */
2329#ifdef PC98
2330 if ((IS_8251(com->pc98_if_type) &&
2331 (pc98_get_modem_status(com) & TIOCM_CAR)) ||
2332 (!IS_8251(com->pc98_if_type) &&
2333 (com->prev_modem_status & MSR_DCD)) ||
2334 mynor & CALLOUT_MASK)
2257 DELAY(50);
2258 (void) inb(com->data_port);
2259 }
2260 }
2261
2262 disable_intr();
2263#ifdef PC98
2264 if (IS_8251(com->pc98_if_type)) {

--- 37 unchanged lines hidden (view full) ---

2302 * the true carrier.
2303 */
2304#ifdef PC98
2305 if ((IS_8251(com->pc98_if_type) &&
2306 (pc98_get_modem_status(com) & TIOCM_CAR)) ||
2307 (!IS_8251(com->pc98_if_type) &&
2308 (com->prev_modem_status & MSR_DCD)) ||
2309 mynor & CALLOUT_MASK)
2310 (*linesw[tp->t_line].l_modem)(tp, 1);
2335#else
2336 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
2311#else
2312 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK)
2337#endif
2338 (*linesw[tp->t_line].l_modem)(tp, 1);
2313 (*linesw[tp->t_line].l_modem)(tp, 1);
2314#endif
2339 }
2340 /*
2341 * Wait for DCD if necessary.
2342 */
2343 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
2344 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
2345 ++com->wopeners;
2346 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);

--- 56 unchanged lines hidden (view full) ---

2403 }
2404 return (0);
2405}
2406
2407static void
2408comhardclose(com)
2409 struct com_s *com;
2410{
2315 }
2316 /*
2317 * Wait for DCD if necessary.
2318 */
2319 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK)
2320 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
2321 ++com->wopeners;
2322 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0);

--- 56 unchanged lines hidden (view full) ---

2379 }
2380 return (0);
2381}
2382
2383static void
2384comhardclose(com)
2385 struct com_s *com;
2386{
2411 Port_t iobase;
2412 int s;
2413 struct tty *tp;
2414 int unit;
2387 int s;
2388 struct tty *tp;
2389 int unit;
2415#ifdef PC98
2416 int port_shift = 0;
2417#endif
2418
2419 unit = com->unit;
2390
2391 unit = com->unit;
2420 iobase = com->iobase;
2421 s = spltty();
2422 com->poll = FALSE;
2423 com->poll_output = FALSE;
2424 com->do_timestamp = FALSE;
2425 com->do_dcd_timestamp = FALSE;
2426 com->pps.ppsparam.mode = 0;
2427#ifdef PC98
2428 if (IS_8251(com->pc98_if_type))
2392 s = spltty();
2393 com->poll = FALSE;
2394 com->poll_output = FALSE;
2395 com->do_timestamp = FALSE;
2396 com->do_dcd_timestamp = FALSE;
2397 com->pps.ppsparam.mode = 0;
2398#ifdef PC98
2399 if (IS_8251(com->pc98_if_type))
2429 com_send_break_off(com);
2430 else {
2431 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
2432 outb(iobase + (com_cfcr << port_shift),
2433 com->cfcr_image &= ~CFCR_SBREAK);
2434 }
2435#else
2436 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2400 com_send_break_off(com);
2401 else
2437#endif
2402#endif
2403 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2438 {
2439#ifdef PC98
2440 int tmp;
2441 if (IS_8251(com->pc98_if_type))
2442 com_int_TxRx_disable(com);
2443 else
2404 {
2405#ifdef PC98
2406 int tmp;
2407 if (IS_8251(com->pc98_if_type))
2408 com_int_TxRx_disable(com);
2409 else
2444 outb(iobase + (com_ier << port_shift), 0);
2445 if (com->pc98_if_type == COM_IF_RSA98III) {
2410 sio_setreg(com, com_ier, 0);
2411 if (com->pc98_if_type == COM_IF_RSA98III)
2446 outb(com->rsabase + rsa_ier, 0x00);
2412 outb(com->rsabase + rsa_ier, 0x00);
2447 }
2448#else
2413#else
2449 outb(iobase + com_ier, 0);
2414 sio_setreg(com, com_ier, 0);
2450#endif
2451 tp = com->tp;
2452#ifdef PC98
2453 if (IS_8251(com->pc98_if_type))
2454 tmp = pc98_get_modem_status(com) & TIOCM_CAR;
2455 else
2456 tmp = com->prev_modem_status & MSR_DCD;
2457#endif
2458 if (tp->t_cflag & HUPCL
2459 /*
2460 * XXX we will miss any carrier drop between here and the
2461 * next open. Perhaps we should watch DCD even when the
2462 * port is closed; it is not sufficient to check it at
2463 * the next open because it might go up and down while
2464 * we're not watching.
2465 */
2466 || (!com->active_out
2467#ifdef PC98
2415#endif
2416 tp = com->tp;
2417#ifdef PC98
2418 if (IS_8251(com->pc98_if_type))
2419 tmp = pc98_get_modem_status(com) & TIOCM_CAR;
2420 else
2421 tmp = com->prev_modem_status & MSR_DCD;
2422#endif
2423 if (tp->t_cflag & HUPCL
2424 /*
2425 * XXX we will miss any carrier drop between here and the
2426 * next open. Perhaps we should watch DCD even when the
2427 * port is closed; it is not sufficient to check it at
2428 * the next open because it might go up and down while
2429 * we're not watching.
2430 */
2431 || (!com->active_out
2432#ifdef PC98
2468 && !(tmp)
2433 && !(tmp)
2469#else
2470 && !(com->prev_modem_status & MSR_DCD)
2471#endif
2472 && !(com->it_in.c_cflag & CLOCAL))
2473 || !(tp->t_state & TS_ISOPEN)) {
2474#ifdef PC98
2475 if (IS_8251(com->pc98_if_type))
2476 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2477 else
2478#endif
2479 (void)commctl(com, TIOCM_DTR, DMBIC);
2480 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
2481 timeout(siodtrwakeup, com, com->dtr_wait);
2482 com->state |= CS_DTR_OFF;
2483 }
2484 }
2485#ifdef PC98
2486 else {
2487 if (IS_8251(com->pc98_if_type))
2434#else
2435 && !(com->prev_modem_status & MSR_DCD)
2436#endif
2437 && !(com->it_in.c_cflag & CLOCAL))
2438 || !(tp->t_state & TS_ISOPEN)) {
2439#ifdef PC98
2440 if (IS_8251(com->pc98_if_type))
2441 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2442 else
2443#endif
2444 (void)commctl(com, TIOCM_DTR, DMBIC);
2445 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) {
2446 timeout(siodtrwakeup, com, com->dtr_wait);
2447 com->state |= CS_DTR_OFF;
2448 }
2449 }
2450#ifdef PC98
2451 else {
2452 if (IS_8251(com->pc98_if_type))
2488 com_tiocm_bic(com, TIOCM_LE );
2453 com_tiocm_bic(com, TIOCM_LE);
2489 }
2490#endif
2491 }
2492#ifdef PC98
2493 if (com->pc98_8251fifo) {
2494 if (com->pc98_8251fifo_enable)
2495 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
2496 com->pc98_8251fifo_enable = 0;
2497 }
2498#endif
2499 if (com->hasfifo) {
2500 /*
2501 * Disable fifos so that they are off after controlled
2502 * reboots. Some BIOSes fail to detect 16550s when the
2503 * fifos are enabled.
2504 */
2454 }
2455#endif
2456 }
2457#ifdef PC98
2458 if (com->pc98_8251fifo) {
2459 if (com->pc98_8251fifo_enable)
2460 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST);
2461 com->pc98_8251fifo_enable = 0;
2462 }
2463#endif
2464 if (com->hasfifo) {
2465 /*
2466 * Disable fifos so that they are off after controlled
2467 * reboots. Some BIOSes fail to detect 16550s when the
2468 * fifos are enabled.
2469 */
2505#ifdef PC98
2506 outb(iobase + (com_fifo << port_shift), 0);
2507#else
2508 outb(iobase + com_fifo, 0);
2509#endif
2470 sio_setreg(com, com_fifo, 0);
2510 }
2511 com->active_out = FALSE;
2512 wakeup(&com->active_out);
2513 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
2514 splx(s);
2515}
2516
2517static int

--- 222 unchanged lines hidden (view full) ---

2740 com = com_addr(unit);
2741 /*
2742 * XXX COM_LOCK();
2743 * would it work here, or be counter-productive?
2744 */
2745#ifdef PC98
2746 if (com != NULL
2747 && !com->gone
2471 }
2472 com->active_out = FALSE;
2473 wakeup(&com->active_out);
2474 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
2475 splx(s);
2476}
2477
2478static int

--- 222 unchanged lines hidden (view full) ---

2701 com = com_addr(unit);
2702 /*
2703 * XXX COM_LOCK();
2704 * would it work here, or be counter-productive?
2705 */
2706#ifdef PC98
2707 if (com != NULL
2708 && !com->gone
2748 && IS_8251(com->pc98_if_type)){
2709 && IS_8251(com->pc98_if_type)) {
2749 siointr1(com);
2710 siointr1(com);
2750 } else
2751#endif /* PC98 */
2752#ifdef PC98
2753 if (com != NULL
2711 } else if (com != NULL
2754 && !com->gone
2755 && com->pc98_if_type == COM_IF_RSA98III) {
2712 && !com->gone
2713 && com->pc98_if_type == COM_IF_RSA98III) {
2756 rsa_buf_status = inb(com->rsabase + rsa_srr) & 0xc9;
2757 if ((rsa_buf_status & 0xc8)
2758 || !(rsa_buf_status & 0x01)) {
2759 siointr1(com);
2760 if(rsa_buf_status
2761 != (inb(com->rsabase + rsa_srr) & 0xc9))
2762 possibly_more_intrs = TRUE;
2763 }
2714 rsa_buf_status =
2715 inb(com->rsabase + rsa_srr) & 0xc9;
2716 if ((rsa_buf_status & 0xc8)
2717 || !(rsa_buf_status & 0x01)) {
2718 siointr1(com);
2719 if (rsa_buf_status !=
2720 (inb(com->rsabase + rsa_srr) & 0xc9))
2721 possibly_more_intrs = TRUE;
2722 }
2764 } else
2765#endif
2766 if (com != NULL
2767 && !com->gone
2768 && (inb(com->int_id_port) & IIR_IMASK)
2769 != IIR_NOPEND) {
2770 siointr1(com);
2771 possibly_more_intrs = TRUE;

--- 14 unchanged lines hidden (view full) ---

2786 u_char *ioptr;
2787 u_char recv_data;
2788 u_char int_ctl;
2789 u_char int_ctl_new;
2790 struct timecounter *tc;
2791 u_int count;
2792
2793#ifdef PC98
2723 } else
2724#endif
2725 if (com != NULL
2726 && !com->gone
2727 && (inb(com->int_id_port) & IIR_IMASK)
2728 != IIR_NOPEND) {
2729 siointr1(com);
2730 possibly_more_intrs = TRUE;

--- 14 unchanged lines hidden (view full) ---

2745 u_char *ioptr;
2746 u_char recv_data;
2747 u_char int_ctl;
2748 u_char int_ctl_new;
2749 struct timecounter *tc;
2750 u_int count;
2751
2752#ifdef PC98
2794 u_char tmp=0;
2753 u_char tmp = 0;
2795 u_char rsa_buf_status = 0;
2754 u_char rsa_buf_status = 0;
2796 int rsa_tx_fifo_size=0;
2797 recv_data=0;
2755 int rsa_tx_fifo_size = 0;
2798#endif /* PC98 */
2799
2800 int_ctl = inb(com->intr_ctl_port);
2801 int_ctl_new = int_ctl;
2802
2803 while (!com->gone) {
2804#ifdef PC98
2805status_read:;

--- 60 unchanged lines hidden (view full) ---

2866 } else {
2867 recv_data = inb(com->data_port);
2868 if (tmp & (STS8251_PE | STS8251_OE |
2869 STS8251_FE | STS8251_BD_SD)) {
2870 pc98_i8251_or_cmd(com, CMD8251_ER);
2871 recv_data = 0;
2872 }
2873 }
2756#endif /* PC98 */
2757
2758 int_ctl = inb(com->intr_ctl_port);
2759 int_ctl_new = int_ctl;
2760
2761 while (!com->gone) {
2762#ifdef PC98
2763status_read:;

--- 60 unchanged lines hidden (view full) ---

2824 } else {
2825 recv_data = inb(com->data_port);
2826 if (tmp & (STS8251_PE | STS8251_OE |
2827 STS8251_FE | STS8251_BD_SD)) {
2828 pc98_i8251_or_cmd(com, CMD8251_ER);
2829 recv_data = 0;
2830 }
2831 }
2874 } else {
2875#endif /* PC98 */
2876#ifdef PC98
2877 if (com->pc98_if_type == COM_IF_RSA98III) {
2832 } else if (com->pc98_if_type == COM_IF_RSA98III) {
2878 if (!(rsa_buf_status & 0x08))
2879 recv_data = 0;
2880 else
2881 recv_data = inb(com->data_port);
2882 } else
2883#endif
2884 if (!(line_status & LSR_RXRDY))
2885 recv_data = 0;
2886 else
2887 recv_data = inb(com->data_port);
2833 if (!(rsa_buf_status & 0x08))
2834 recv_data = 0;
2835 else
2836 recv_data = inb(com->data_port);
2837 } else
2838#endif
2839 if (!(line_status & LSR_RXRDY))
2840 recv_data = 0;
2841 else
2842 recv_data = inb(com->data_port);
2888#ifdef PC98
2889 }
2890#endif
2891 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2892 /*
2893 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2894 * Otherwise, push the work to a higher level
2895 * (to handle PARMRK) if we're bypassing.
2896 * Otherwise, convert BI/FE and PE+INPCK to 0.
2897 *
2898 * This makes bypassing work right in the

--- 155 unchanged lines hidden (view full) ---

3054#else
3055 outb(com->data_port, *ioptr++);
3056#endif
3057 ++com->bytes_out;
3058 }
3059#ifdef PC98
3060 if (IS_8251(com->pc98_if_type))
3061 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
2843 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2844 /*
2845 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2846 * Otherwise, push the work to a higher level
2847 * (to handle PARMRK) if we're bypassing.
2848 * Otherwise, convert BI/FE and PE+INPCK to 0.
2849 *
2850 * This makes bypassing work right in the

--- 155 unchanged lines hidden (view full) ---

3006#else
3007 outb(com->data_port, *ioptr++);
3008#endif
3009 ++com->bytes_out;
3010 }
3011#ifdef PC98
3012 if (IS_8251(com->pc98_if_type))
3013 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
3062 com_int_Tx_enable(com);
3014 com_int_Tx_enable(com);
3063#endif
3064 com->obufq.l_head = ioptr;
3065 if (COM_IIR_TXRDYBUG(com->flags)) {
3066 int_ctl_new = int_ctl | IER_ETXRDY;
3067 }
3068 if (ioptr >= com->obufq.l_tail) {
3069 struct lbq *qp;
3070

--- 6 unchanged lines hidden (view full) ---

3077 com->obufq.l_next = qp;
3078 } else {
3079 /* output just completed */
3080 if (COM_IIR_TXRDYBUG(com->flags)) {
3081 int_ctl_new = int_ctl & ~IER_ETXRDY;
3082 }
3083 com->state &= ~CS_BUSY;
3084#if defined(PC98)
3015#endif
3016 com->obufq.l_head = ioptr;
3017 if (COM_IIR_TXRDYBUG(com->flags)) {
3018 int_ctl_new = int_ctl | IER_ETXRDY;
3019 }
3020 if (ioptr >= com->obufq.l_tail) {
3021 struct lbq *qp;
3022

--- 6 unchanged lines hidden (view full) ---

3029 com->obufq.l_next = qp;
3030 } else {
3031 /* output just completed */
3032 if (COM_IIR_TXRDYBUG(com->flags)) {
3033 int_ctl_new = int_ctl & ~IER_ETXRDY;
3034 }
3035 com->state &= ~CS_BUSY;
3036#if defined(PC98)
3085 if (IS_8251(com->pc98_if_type))
3086 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
3037 if (IS_8251(com->pc98_if_type) &&
3038 pc98_check_i8251_interrupt(com) & IEN_TxFLAG)
3087 com_int_Tx_disable(com);
3088#endif
3089 }
3090 if (!(com->state & CS_ODONE)) {
3091 com_events += LOTS_OF_EVENTS;
3092 com->state |= CS_ODONE;
3093 setsofttty(); /* handle at high level ASAP */
3094 }

--- 7 unchanged lines hidden (view full) ---

3102 } else
3103#endif
3104 outb(com->intr_ctl_port, int_ctl_new);
3105 }
3106 }
3107#ifdef PC98
3108 else if (line_status & LSR_TXRDY) {
3109 if (IS_8251(com->pc98_if_type))
3039 com_int_Tx_disable(com);
3040#endif
3041 }
3042 if (!(com->state & CS_ODONE)) {
3043 com_events += LOTS_OF_EVENTS;
3044 com->state |= CS_ODONE;
3045 setsofttty(); /* handle at high level ASAP */
3046 }

--- 7 unchanged lines hidden (view full) ---

3054 } else
3055#endif
3056 outb(com->intr_ctl_port, int_ctl_new);
3057 }
3058 }
3059#ifdef PC98
3060 else if (line_status & LSR_TXRDY) {
3061 if (IS_8251(com->pc98_if_type))
3110 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
3062 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG)
3111 com_int_Tx_disable(com);
3112 }
3113 if (IS_8251(com->pc98_if_type)) {
3114 if (com->pc98_8251fifo_enable) {
3115 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY)
3116 goto more_intr;
3117 } else {
3118 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)

--- 19 unchanged lines hidden (view full) ---

3138 dev_t dev;
3139 u_long cmd;
3140 caddr_t data;
3141 int flag;
3142 struct proc *p;
3143{
3144 struct com_s *com;
3145 int error;
3063 com_int_Tx_disable(com);
3064 }
3065 if (IS_8251(com->pc98_if_type)) {
3066 if (com->pc98_8251fifo_enable) {
3067 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY)
3068 goto more_intr;
3069 } else {
3070 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)

--- 19 unchanged lines hidden (view full) ---

3090 dev_t dev;
3091 u_long cmd;
3092 caddr_t data;
3093 int flag;
3094 struct proc *p;
3095{
3096 struct com_s *com;
3097 int error;
3146 Port_t iobase;
3147 int mynor;
3148 int s;
3149 struct tty *tp;
3150#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
3151 u_long oldcmd;
3152 struct termios term;
3153#endif
3154
3155 mynor = minor(dev);
3156 com = com_addr(MINOR_TO_UNIT(mynor));
3157 if (com == NULL || com->gone)
3158 return (ENODEV);
3098 int mynor;
3099 int s;
3100 struct tty *tp;
3101#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
3102 u_long oldcmd;
3103 struct termios term;
3104#endif
3105
3106 mynor = minor(dev);
3107 com = com_addr(MINOR_TO_UNIT(mynor));
3108 if (com == NULL || com->gone)
3109 return (ENODEV);
3159 iobase = com->iobase;
3160 if (mynor & CONTROL_MASK) {
3161 struct termios *ct;
3162
3163 switch (mynor & CONTROL_MASK) {
3164 case CONTROL_INIT_STATE:
3165 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
3166 break;
3167 case CONTROL_LOCK_STATE:

--- 63 unchanged lines hidden (view full) ---

3231 if (error != ENOIOCTL) {
3232 splx(s);
3233 return (error);
3234 }
3235#ifdef PC98
3236 if (IS_8251(com->pc98_if_type)) {
3237 switch (cmd) {
3238 case TIOCSBRK:
3110 if (mynor & CONTROL_MASK) {
3111 struct termios *ct;
3112
3113 switch (mynor & CONTROL_MASK) {
3114 case CONTROL_INIT_STATE:
3115 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in;
3116 break;
3117 case CONTROL_LOCK_STATE:

--- 63 unchanged lines hidden (view full) ---

3181 if (error != ENOIOCTL) {
3182 splx(s);
3183 return (error);
3184 }
3185#ifdef PC98
3186 if (IS_8251(com->pc98_if_type)) {
3187 switch (cmd) {
3188 case TIOCSBRK:
3239 com_send_break_on( com );
3189 com_send_break_on(com);
3240 break;
3241 case TIOCCBRK:
3190 break;
3191 case TIOCCBRK:
3242 com_send_break_off( com );
3192 com_send_break_off(com);
3243 break;
3244 case TIOCSDTR:
3193 break;
3194 case TIOCSDTR:
3245 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS );
3195 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS);
3246 break;
3247 case TIOCCDTR:
3248 com_tiocm_bic(com, TIOCM_DTR);
3249 break;
3250 /*
3251 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
3252 * changes get undone on the next call to comparam().
3253 */
3254 case TIOCMSET:
3196 break;
3197 case TIOCCDTR:
3198 com_tiocm_bic(com, TIOCM_DTR);
3199 break;
3200 /*
3201 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The
3202 * changes get undone on the next call to comparam().
3203 */
3204 case TIOCMSET:
3255 com_tiocm_set( com, *(int *)data );
3205 com_tiocm_set(com, *(int *)data);
3256 break;
3257 case TIOCMBIS:
3206 break;
3207 case TIOCMBIS:
3258 com_tiocm_bis( com, *(int *)data );
3208 com_tiocm_bis(com, *(int *)data);
3259 break;
3260 case TIOCMBIC:
3209 break;
3210 case TIOCMBIC:
3261 com_tiocm_bic( com, *(int *)data );
3211 com_tiocm_bic(com, *(int *)data);
3262 break;
3263 case TIOCMGET:
3264 *(int *)data = com_tiocm_get(com);
3265 break;
3266 case TIOCMSDTRWAIT:
3267 /* must be root since the wait applies to following logins */
3268 error = suser(p);
3269 if (error != 0) {

--- 10 unchanged lines hidden (view full) ---

3280 *(struct timeval *)data = com->timestamp;
3281 break;
3282 case TIOCDCDTIMESTAMP:
3283 com->do_dcd_timestamp = TRUE;
3284 *(struct timeval *)data = com->dcd_timestamp;
3285 break;
3286 default:
3287 splx(s);
3212 break;
3213 case TIOCMGET:
3214 *(int *)data = com_tiocm_get(com);
3215 break;
3216 case TIOCMSDTRWAIT:
3217 /* must be root since the wait applies to following logins */
3218 error = suser(p);
3219 if (error != 0) {

--- 10 unchanged lines hidden (view full) ---

3230 *(struct timeval *)data = com->timestamp;
3231 break;
3232 case TIOCDCDTIMESTAMP:
3233 com->do_dcd_timestamp = TRUE;
3234 *(struct timeval *)data = com->dcd_timestamp;
3235 break;
3236 default:
3237 splx(s);
3288 return (ENOTTY);
3238 error = pps_ioctl(cmd, data, &com->pps);
3239 if (error == ENODEV)
3240 error = ENOTTY;
3241 return (error);
3289 }
3290 } else {
3242 }
3243 } else {
3291 int port_shift;
3292 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3293#endif
3294 switch (cmd) {
3295 case TIOCSBRK:
3244#endif
3245 switch (cmd) {
3246 case TIOCSBRK:
3296#ifdef PC98
3297 outb(iobase + (com_cfcr << port_shift),
3298 com->cfcr_image |= CFCR_SBREAK);
3299#else
3300 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK);
3301#endif
3247 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK);
3302 break;
3303 case TIOCCBRK:
3248 break;
3249 case TIOCCBRK:
3304#ifdef PC98
3305 outb(iobase + (com_cfcr << port_shift),
3306 com->cfcr_image &= ~CFCR_SBREAK);
3307#else
3308 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
3309#endif
3250 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
3310 break;
3311 case TIOCSDTR:
3312 (void)commctl(com, TIOCM_DTR, DMBIS);
3313 break;
3314 case TIOCCDTR:
3315 (void)commctl(com, TIOCM_DTR, DMBIC);
3316 break;
3317 /*

--- 129 unchanged lines hidden (view full) ---

3447 struct termios *t;
3448{
3449 u_int cfcr;
3450 int cflag;
3451 struct com_s *com;
3452 int divisor;
3453 u_char dlbh;
3454 u_char dlbl;
3251 break;
3252 case TIOCSDTR:
3253 (void)commctl(com, TIOCM_DTR, DMBIS);
3254 break;
3255 case TIOCCDTR:
3256 (void)commctl(com, TIOCM_DTR, DMBIC);
3257 break;
3258 /*

--- 129 unchanged lines hidden (view full) ---

3388 struct termios *t;
3389{
3390 u_int cfcr;
3391 int cflag;
3392 struct com_s *com;
3393 int divisor;
3394 u_char dlbh;
3395 u_char dlbl;
3455 Port_t iobase;
3456 int s;
3457 int unit;
3458#ifdef PC98
3396 int s;
3397 int unit;
3398#ifdef PC98
3459 int port_shift = 0;
3460 u_char param = 0;
3461#endif
3462
3463#ifdef PC98
3399 u_char param = 0;
3400#endif
3401
3402#ifdef PC98
3464 cfcr = 0;
3465 unit = DEV_TO_UNIT(tp->t_dev);
3466 com = com_addr(unit);
3403 unit = DEV_TO_UNIT(tp->t_dev);
3404 com = com_addr(unit);
3467 iobase = com->iobase;
3405
3406 cfcr = 0;
3468 if (IS_8251(com->pc98_if_type)) {
3469 divisor = pc98_ttspeedtab(com, t->c_ospeed);
3470 } else {
3407 if (IS_8251(com->pc98_if_type)) {
3408 divisor = pc98_ttspeedtab(com, t->c_ospeed);
3409 } else {
3471 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3472
3473 /* do historical conversions */
3474 if (t->c_ispeed == 0)
3475 t->c_ispeed = t->c_ospeed;
3476
3477 /* check requested parameters */
3478 divisor = ttspeedtab(t->c_ospeed,
3479 if_16550a_type[com->pc98_if_type & 0x0f].speedtab);
3480 }
3481#else
3482 /* do historical conversions */
3483 if (t->c_ispeed == 0)
3484 t->c_ispeed = t->c_ospeed;
3485
3486 /* check requested parameters */
3487 divisor = ttspeedtab(t->c_ospeed, comspeedtab);
3488#endif
3489 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed))
3490 return (EINVAL);
3491
3410 /* do historical conversions */
3411 if (t->c_ispeed == 0)
3412 t->c_ispeed = t->c_ospeed;
3413
3414 /* check requested parameters */
3415 divisor = ttspeedtab(t->c_ospeed,
3416 if_16550a_type[com->pc98_if_type & 0x0f].speedtab);
3417 }
3418#else
3419 /* do historical conversions */
3420 if (t->c_ispeed == 0)
3421 t->c_ispeed = t->c_ospeed;
3422
3423 /* check requested parameters */
3424 divisor = ttspeedtab(t->c_ospeed, comspeedtab);
3425#endif
3426 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed))
3427 return (EINVAL);
3428
3492 /* parameters are OK, convert them to the com struct and the device */
3493#ifndef PC98
3429#ifndef PC98
3430 /* parameters are OK, convert them to the com struct and the device */
3494 unit = DEV_TO_UNIT(tp->t_dev);
3495 com = com_addr(unit);
3496 if (com == NULL)
3497 return (ENODEV);
3431 unit = DEV_TO_UNIT(tp->t_dev);
3432 com = com_addr(unit);
3433 if (com == NULL)
3434 return (ENODEV);
3498 iobase = com->iobase;
3499#endif
3500 s = spltty();
3501#ifdef PC98
3502 if (IS_8251(com->pc98_if_type)) {
3503 if (divisor == 0)
3435#endif
3436 s = spltty();
3437#ifdef PC98
3438 if (IS_8251(com->pc98_if_type)) {
3439 if (divisor == 0)
3504 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3440 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
3505 else
3441 else
3506 com_tiocm_bis( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
3507 } else {
3442 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
3443 } else
3508#endif
3509 if (divisor == 0)
3510 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
3511 else
3512 (void)commctl(com, TIOCM_DTR, DMBIS);
3444#endif
3445 if (divisor == 0)
3446 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */
3447 else
3448 (void)commctl(com, TIOCM_DTR, DMBIS);
3513#ifdef PC98
3514 }
3515#endif
3516 cflag = t->c_cflag;
3517#ifdef PC98
3518 if (!IS_8251(com->pc98_if_type)) {
3519#endif
3520 switch (cflag & CSIZE) {
3521 case CS5:
3522 cfcr = CFCR_5BITS;
3523 break;

--- 30 unchanged lines hidden (view full) ---

3554 /*
3555 * The Hayes ESP card needs the fifo DMA mode bit set
3556 * in compatibility mode. If not, it will interrupt
3557 * for each character received.
3558 */
3559 if (com->esp)
3560 com->fifo_image |= FIFO_DMA_MODE;
3561#endif
3449 cflag = t->c_cflag;
3450#ifdef PC98
3451 if (!IS_8251(com->pc98_if_type)) {
3452#endif
3453 switch (cflag & CSIZE) {
3454 case CS5:
3455 cfcr = CFCR_5BITS;
3456 break;

--- 30 unchanged lines hidden (view full) ---

3487 /*
3488 * The Hayes ESP card needs the fifo DMA mode bit set
3489 * in compatibility mode. If not, it will interrupt
3490 * for each character received.
3491 */
3492 if (com->esp)
3493 com->fifo_image |= FIFO_DMA_MODE;
3494#endif
3562#ifdef PC98
3563 outb(iobase + (com_fifo << port_shift), com->fifo_image);
3564#else
3565 outb(iobase + com_fifo, com->fifo_image);
3566#endif
3495 sio_setreg(com, com_fifo, com->fifo_image);
3567 }
3568#ifdef PC98
3569 }
3570#endif
3571
3572 /*
3573 * This returns with interrupts disabled so that we can complete
3574 * the speed change atomically. Keeping interrupts disabled is
3575 * especially important while com_data is hidden.
3576 */
3577 (void) siosetwater(com, t->c_ispeed);
3578
3579#ifdef PC98
3580 if (IS_8251(com->pc98_if_type))
3496 }
3497#ifdef PC98
3498 }
3499#endif
3500
3501 /*
3502 * This returns with interrupts disabled so that we can complete
3503 * the speed change atomically. Keeping interrupts disabled is
3504 * especially important while com_data is hidden.
3505 */
3506 (void) siosetwater(com, t->c_ispeed);
3507
3508#ifdef PC98
3509 if (IS_8251(com->pc98_if_type))
3581 com_cflag_and_speed_set(com, cflag, t->c_ospeed);
3510 com_cflag_and_speed_set(com, cflag, t->c_ospeed);
3582 else {
3583#endif
3584 if (divisor != 0) {
3511 else {
3512#endif
3513 if (divisor != 0) {
3585#ifdef PC98
3586 outb(iobase + (com_cfcr << port_shift), cfcr | CFCR_DLAB);
3587#else
3588 outb(iobase + com_cfcr, cfcr | CFCR_DLAB);
3589#endif
3514 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB);
3590 /*
3591 * Only set the divisor registers if they would change,
3592 * since on some 16550 incompatibles (UMC8669F), setting
3593 * them while input is arriving them loses sync until
3594 * data stops arriving.
3595 */
3596 dlbl = divisor & 0xFF;
3515 /*
3516 * Only set the divisor registers if they would change,
3517 * since on some 16550 incompatibles (UMC8669F), setting
3518 * them while input is arriving them loses sync until
3519 * data stops arriving.
3520 */
3521 dlbl = divisor & 0xFF;
3597#ifdef PC98
3598 if (inb(iobase + (com_dlbl << port_shift)) != dlbl)
3599 outb(iobase + (com_dlbl << port_shift), dlbl);
3522 if (sio_getreg(com, com_dlbl) != dlbl)
3523 sio_setreg(com, com_dlbl, dlbl);
3600 dlbh = (u_int) divisor >> 8;
3524 dlbh = (u_int) divisor >> 8;
3601 if (inb(iobase + (com_dlbh << port_shift)) != dlbh)
3602 outb(iobase + (com_dlbh << port_shift), dlbh);
3603#else
3604 if (inb(iobase + com_dlbl) != dlbl)
3605 outb(iobase + com_dlbl, dlbl);
3606 dlbh = (u_int) divisor >> 8;
3607 if (inb(iobase + com_dlbh) != dlbh)
3608 outb(iobase + com_dlbh, dlbh);
3609#endif
3525 if (sio_getreg(com, com_dlbh) != dlbh)
3526 sio_setreg(com, com_dlbh, dlbh);
3610 }
3611
3527 }
3528
3612
3529 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
3613#ifdef PC98
3614 }
3530#ifdef PC98
3531 }
3615 outb(iobase + (com_cfcr << port_shift), com->cfcr_image = cfcr);
3616#else
3617 outb(iobase + com_cfcr, com->cfcr_image = cfcr);
3618#endif
3619
3620 if (!(tp->t_state & TS_TTSTOP))
3621 com->state |= CS_TTGO;
3622
3623 if (cflag & CRTS_IFLOW) {
3532#endif
3533
3534 if (!(tp->t_state & TS_TTSTOP))
3535 com->state |= CS_TTGO;
3536
3537 if (cflag & CRTS_IFLOW) {
3538#ifndef PC98
3624 if (com->st16650a) {
3539 if (com->st16650a) {
3625 outb(iobase + com_cfcr, 0xbf);
3626 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40);
3540 sio_setreg(com, com_cfcr, 0xbf);
3541 sio_setreg(com, com_fifo,
3542 sio_getreg(com, com_fifo) | 0x40);
3627 }
3543 }
3544#endif
3628 com->state |= CS_RTS_IFLOW;
3629 /*
3630 * If CS_RTS_IFLOW just changed from off to on, the change
3631 * needs to be propagated to MCR_RTS. This isn't urgent,
3632 * so do it later by calling comstart() instead of repeating
3633 * a lot of code from comstart() here.
3634 */
3635 } else if (com->state & CS_RTS_IFLOW) {
3636 com->state &= ~CS_RTS_IFLOW;
3637 /*
3638 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
3639 * on here, since comstart() won't do it later.
3640 */
3641#ifdef PC98
3642 if (IS_8251(com->pc98_if_type))
3643 com_tiocm_bis(com, TIOCM_RTS);
3644 else
3545 com->state |= CS_RTS_IFLOW;
3546 /*
3547 * If CS_RTS_IFLOW just changed from off to on, the change
3548 * needs to be propagated to MCR_RTS. This isn't urgent,
3549 * so do it later by calling comstart() instead of repeating
3550 * a lot of code from comstart() here.
3551 */
3552 } else if (com->state & CS_RTS_IFLOW) {
3553 com->state &= ~CS_RTS_IFLOW;
3554 /*
3555 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
3556 * on here, since comstart() won't do it later.
3557 */
3558#ifdef PC98
3559 if (IS_8251(com->pc98_if_type))
3560 com_tiocm_bis(com, TIOCM_RTS);
3561 else
3645#endif
3562 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3563#else
3646 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3647 if (com->st16650a) {
3564 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3565 if (com->st16650a) {
3648 outb(iobase + com_cfcr, 0xbf);
3649 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40);
3566 sio_setreg(com, com_cfcr, 0xbf);
3567 sio_setreg(com, com_fifo,
3568 sio_getreg(com, com_fifo) & ~0x40);
3650 }
3569 }
3570#endif
3651 }
3652
3653
3654 /*
3655 * Set up state to handle output flow control.
3656 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
3657 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
3658 */

--- 7 unchanged lines hidden (view full) ---

3666#endif
3667 if (cflag & CCTS_OFLOW) {
3668 com->state |= CS_CTS_OFLOW;
3669#ifdef PC98
3670 if (IS_8251(com->pc98_if_type)) {
3671 if (!(pc98_get_modem_status(com) & TIOCM_CTS))
3672 com->state &= ~CS_ODEVREADY;
3673 } else {
3571 }
3572
3573
3574 /*
3575 * Set up state to handle output flow control.
3576 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
3577 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
3578 */

--- 7 unchanged lines hidden (view full) ---

3586#endif
3587 if (cflag & CCTS_OFLOW) {
3588 com->state |= CS_CTS_OFLOW;
3589#ifdef PC98
3590 if (IS_8251(com->pc98_if_type)) {
3591 if (!(pc98_get_modem_status(com) & TIOCM_CTS))
3592 com->state &= ~CS_ODEVREADY;
3593 } else {
3594 if (com->pc98_if_type == COM_IF_RSA98III) {
3595 /* Set automatic flow control mode */
3596 outb(com->rsabase + rsa_msr, param | 0x08);
3597 } else
3674#endif
3598#endif
3675#ifdef PC98
3676 if (com->pc98_if_type == COM_IF_RSA98III) {
3677 /* Set automatic flow control mode */
3678 outb(com->rsabase + rsa_msr, param | 0x08);
3679 } else
3680#endif
3681 if (!(com->last_modem_status & MSR_CTS))
3682 com->state &= ~CS_ODEVREADY;
3599 if (!(com->last_modem_status & MSR_CTS))
3600 com->state &= ~CS_ODEVREADY;
3683 if (com->st16650a) {
3684 outb(iobase + com_cfcr, 0xbf);
3685 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80);
3686 }
3687#ifdef PC98
3688 }
3601#ifdef PC98
3602 }
3689#endif
3603#else
3604 if (com->st16650a) {
3605 sio_setreg(com, com_cfcr, 0xbf);
3606 sio_setreg(com, com_fifo,
3607 sio_getreg(com, com_fifo) | 0x80);
3608 }
3690 } else {
3691 if (com->st16650a) {
3609 } else {
3610 if (com->st16650a) {
3692 outb(iobase + com_cfcr, 0xbf);
3693 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80);
3611 sio_setreg(com, com_cfcr, 0xbf);
3612 sio_setreg(com, com_fifo,
3613 sio_getreg(com, com_fifo) & ~0x80);
3694 }
3614 }
3615#endif
3695 }
3696
3616 }
3617
3697
3698#ifdef PC98
3618#ifdef PC98
3699 outb(iobase + (com_cfcr << port_shift), com->cfcr_image);
3700#else
3701 outb(iobase + com_cfcr, com->cfcr_image);
3619 if (!IS_8251(com->pc98_if_type))
3702#endif
3620#endif
3621 sio_setreg(com, com_cfcr, com->cfcr_image);
3703
3622
3704
3705 /* XXX shouldn't call functions while intrs are disabled. */
3706 disc_optim(tp, t, com);
3707 /*
3708 * Recover from fiddling with CS_TTGO. We used to call siointr1()
3709 * unconditionally, but that defeated the careful discarding of
3710 * stale input in sioopen().
3711 */
3712 if (com->state >= (CS_BUSY | CS_TTGO))

--- 133 unchanged lines hidden (view full) ---

3846 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
3847 && com->state & CS_RTS_IFLOW)
3848 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3849#endif
3850 }
3851 enable_intr();
3852 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
3853 ttwwakeup(tp);
3623 /* XXX shouldn't call functions while intrs are disabled. */
3624 disc_optim(tp, t, com);
3625 /*
3626 * Recover from fiddling with CS_TTGO. We used to call siointr1()
3627 * unconditionally, but that defeated the careful discarding of
3628 * stale input in sioopen().
3629 */
3630 if (com->state >= (CS_BUSY | CS_TTGO))

--- 133 unchanged lines hidden (view full) ---

3764 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
3765 && com->state & CS_RTS_IFLOW)
3766 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3767#endif
3768 }
3769 enable_intr();
3770 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
3771 ttwwakeup(tp);
3854#ifdef PC98
3855/* if(IS_8251(com->pc98_if_type))
3856 com_int_Tx_enable(com); */
3857#endif
3858 splx(s);
3859 return;
3860 }
3861 if (tp->t_outq.c_cc != 0) {
3862 struct lbq *qp;
3863 struct lbq *next;
3864
3865 if (!com->obufs[0].l_queued) {
3866 com->obufs[0].l_tail
3867 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
3772 splx(s);
3773 return;
3774 }
3775 if (tp->t_outq.c_cc != 0) {
3776 struct lbq *qp;
3777 struct lbq *next;
3778
3779 if (!com->obufs[0].l_queued) {
3780 com->obufs[0].l_tail
3781 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
3868#ifndef PC98
3869 sizeof com->obuf1);
3870#else
3782#ifdef PC98
3871 com->obufsize);
3783 com->obufsize);
3784#else
3785 sizeof com->obuf1);
3872#endif
3873 com->obufs[0].l_next = NULL;
3874 com->obufs[0].l_queued = TRUE;
3875 disable_intr();
3876 if (com->state & CS_BUSY) {
3877 qp = com->obufq.l_next;
3878 while ((next = qp->l_next) != NULL)
3879 qp = next;

--- 4 unchanged lines hidden (view full) ---

3884 com->obufq.l_next = &com->obufs[0];
3885 com->state |= CS_BUSY;
3886 }
3887 enable_intr();
3888 }
3889 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
3890 com->obufs[1].l_tail
3891 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
3786#endif
3787 com->obufs[0].l_next = NULL;
3788 com->obufs[0].l_queued = TRUE;
3789 disable_intr();
3790 if (com->state & CS_BUSY) {
3791 qp = com->obufq.l_next;
3792 while ((next = qp->l_next) != NULL)
3793 qp = next;

--- 4 unchanged lines hidden (view full) ---

3798 com->obufq.l_next = &com->obufs[0];
3799 com->state |= CS_BUSY;
3800 }
3801 enable_intr();
3802 }
3803 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
3804 com->obufs[1].l_tail
3805 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
3892#ifndef PC98
3893 sizeof com->obuf2);
3894#else
3806#ifdef PC98
3895 com->obufsize);
3807 com->obufsize);
3808#else
3809 sizeof com->obuf2);
3896#endif
3897 com->obufs[1].l_next = NULL;
3898 com->obufs[1].l_queued = TRUE;
3899 disable_intr();
3900 if (com->state & CS_BUSY) {
3901 qp = com->obufq.l_next;
3902 while ((next = qp->l_next) != NULL)
3903 qp = next;

--- 7 unchanged lines hidden (view full) ---

3911 enable_intr();
3912 }
3913 tp->t_state |= TS_BUSY;
3914 }
3915 disable_intr();
3916 if (com->state >= (CS_BUSY | CS_TTGO))
3917 siointr1(com); /* fake interrupt to start output */
3918 enable_intr();
3810#endif
3811 com->obufs[1].l_next = NULL;
3812 com->obufs[1].l_queued = TRUE;
3813 disable_intr();
3814 if (com->state & CS_BUSY) {
3815 qp = com->obufq.l_next;
3816 while ((next = qp->l_next) != NULL)
3817 qp = next;

--- 7 unchanged lines hidden (view full) ---

3825 enable_intr();
3826 }
3827 tp->t_state |= TS_BUSY;
3828 }
3829 disable_intr();
3830 if (com->state >= (CS_BUSY | CS_TTGO))
3831 siointr1(com); /* fake interrupt to start output */
3832 enable_intr();
3919#ifdef PC98
3920/* if(IS_8251(com->pc98_if_type))
3921 com_int_Tx_enable(com); */
3922#endif
3923 ttwwakeup(tp);
3924 splx(s);
3925}
3926
3927static void
3928comstop(tp, rw)
3929 struct tty *tp;
3930 int rw;
3931{
3932 struct com_s *com;
3933#ifdef PC98
3833 ttwwakeup(tp);
3834 splx(s);
3835}
3836
3837static void
3838comstop(tp, rw)
3839 struct tty *tp;
3840 int rw;
3841{
3842 struct com_s *com;
3843#ifdef PC98
3934 int port_shift = 0;
3935 int rsa98_tmp = 0;
3936#endif
3937
3938 com = com_addr(DEV_TO_UNIT(tp->t_dev));
3939 if (com == NULL || com->gone)
3940 return;
3844 int rsa98_tmp = 0;
3845#endif
3846
3847 com = com_addr(DEV_TO_UNIT(tp->t_dev));
3848 if (com == NULL || com->gone)
3849 return;
3941#ifdef PC98
3942 if (!IS_8251(com->pc98_if_type))
3943 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
3944#endif
3945 disable_intr();
3946 if (rw & FWRITE) {
3850 disable_intr();
3851 if (rw & FWRITE) {
3852#ifdef PC98
3853 if (!IS_8251(com->pc98_if_type)) {
3854#endif
3947 if (com->hasfifo)
3948#ifdef COM_ESP
3949 /* XXX avoid h/w bug. */
3950 if (!com->esp)
3951#endif
3855 if (com->hasfifo)
3856#ifdef COM_ESP
3857 /* XXX avoid h/w bug. */
3858 if (!com->esp)
3859#endif
3860 sio_setreg(com, com_fifo,
3861 FIFO_XMT_RST | com->fifo_image);
3952#ifdef PC98
3862#ifdef PC98
3953 outb(com->iobase + (com_fifo << port_shift),
3954 FIFO_XMT_RST | com->fifo_image);
3955 if (com->pc98_if_type == COM_IF_RSA98III)
3956 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3957 outb(com->iobase + (com_fifo << port_shift),
3958 FIFO_XMT_RST | com->fifo_image);
3959#else
3960 outb(com->iobase + com_fifo,
3961 FIFO_XMT_RST | com->fifo_image);
3863 if (com->pc98_if_type == COM_IF_RSA98III)
3864 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3865 sio_setreg(com, com_fifo,
3866 FIFO_XMT_RST | com->fifo_image);
3867 }
3962#endif
3963 com->obufs[0].l_queued = FALSE;
3964 com->obufs[1].l_queued = FALSE;
3965 if (com->state & CS_ODONE)
3966 com_events -= LOTS_OF_EVENTS;
3967 com->state &= ~(CS_ODONE | CS_BUSY);
3968 com->tp->t_state &= ~TS_BUSY;
3969 }
3970 if (rw & FREAD) {
3868#endif
3869 com->obufs[0].l_queued = FALSE;
3870 com->obufs[1].l_queued = FALSE;
3871 if (com->state & CS_ODONE)
3872 com_events -= LOTS_OF_EVENTS;
3873 com->state &= ~(CS_ODONE | CS_BUSY);
3874 com->tp->t_state &= ~TS_BUSY;
3875 }
3876 if (rw & FREAD) {
3877#ifdef PC98
3878 if (!IS_8251(com->pc98_if_type)) {
3879 if (com->pc98_if_type == COM_IF_RSA98III)
3880 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3881 sio_getreg(com, com_data);
3882#endif
3971 if (com->hasfifo)
3972#ifdef COM_ESP
3973 /* XXX avoid h/w bug. */
3974 if (!com->esp)
3975#endif
3883 if (com->hasfifo)
3884#ifdef COM_ESP
3885 /* XXX avoid h/w bug. */
3886 if (!com->esp)
3887#endif
3888 sio_setreg(com, com_fifo,
3889 FIFO_RCV_RST | com->fifo_image);
3976#ifdef PC98
3890#ifdef PC98
3977 if (com->pc98_if_type == COM_IF_RSA98III) {
3978 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3979 inb(com->data_port);
3980 }
3981 outb(com->iobase + (com_fifo << port_shift),
3982 FIFO_RCV_RST | com->fifo_image);
3983#else
3984 outb(com->iobase + com_fifo,
3985 FIFO_RCV_RST | com->fifo_image);
3891 }
3986#endif
3987 com_events -= (com->iptr - com->ibuf);
3988 com->iptr = com->ibuf;
3989 }
3990 enable_intr();
3991 comstart(tp);
3992}
3993

--- 1105 unchanged lines hidden (view full) ---

5099}
5100
5101static void
5102pc98_set_baud_rate( struct com_s *com, int count )
5103{
5104 int if_type, io, s;
5105
5106 if_type = com->pc98_if_type & 0x0f;
3892#endif
3893 com_events -= (com->iptr - com->ibuf);
3894 com->iptr = com->ibuf;
3895 }
3896 enable_intr();
3897 comstart(tp);
3898}
3899

--- 1105 unchanged lines hidden (view full) ---

5005}
5006
5007static void
5008pc98_set_baud_rate( struct com_s *com, int count )
5009{
5010 int if_type, io, s;
5011
5012 if_type = com->pc98_if_type & 0x0f;
5107 io = com->iobase & 0xff00;
5013 io = rman_get_start(com->ioportres) & 0xff00;
5108
5109 switch (com->pc98_if_type) {
5110 case COM_IF_INTERNAL:
5111 if (PC98SIO_baud_rate_port(if_type) != -1) {
5112 if (count & COM1_EXT_CLOCK) {
5113 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
5114 break;
5115 } else {

--- 48 unchanged lines hidden (view full) ---

5164pc98_check_if_type(device_t dev, struct siodev *iod)
5165{
5166 int irr, io, if_type, tmp;
5167 static short irq_tab[2][8] = {
5168 { 3, 5, 6, 9, 10, 12, 13, -1},
5169 { 3, 10, 12, 13, 5, 6, 9, -1}
5170 };
5171
5014
5015 switch (com->pc98_if_type) {
5016 case COM_IF_INTERNAL:
5017 if (PC98SIO_baud_rate_port(if_type) != -1) {
5018 if (count & COM1_EXT_CLOCK) {
5019 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
5020 break;
5021 } else {

--- 48 unchanged lines hidden (view full) ---

5070pc98_check_if_type(device_t dev, struct siodev *iod)
5071{
5072 int irr, io, if_type, tmp;
5073 static short irq_tab[2][8] = {
5074 { 3, 5, 6, 9, 10, 12, 13, -1},
5075 { 3, 10, 12, 13, 5, 6, 9, -1}
5076 };
5077
5172 iod->if_type = if_type = GET_IFTYPE(device_get_flags(dev));
5173 if ((if_type < 0 || if_type > COM_IF_END1) &&
5174 (if_type < 0x10 || if_type > COM_IF_END2))
5175 return(-1);
5176 if_type &= 0x0f;
5078 if_type = iod->if_type & 0x0f;
5177 iod->irq = 0;
5178 io = isa_get_port(dev) & 0xff00;
5179
5180 if (IS_8251(iod->if_type)) {
5181 if (PC98SIO_func_port(if_type) != -1) {
5182 outb(io | PC98SIO_func_port(if_type), 0xf2);
5183 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
5184 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)

--- 32 unchanged lines hidden (view full) ---

5217 else
5218 iod->irq = irq_tab[0][tmp & 0x07];
5219 }
5220 }
5221 if ( iod->irq == -1 ) return -1;
5222
5223 return 0;
5224}
5079 iod->irq = 0;
5080 io = isa_get_port(dev) & 0xff00;
5081
5082 if (IS_8251(iod->if_type)) {
5083 if (PC98SIO_func_port(if_type) != -1) {
5084 outb(io | PC98SIO_func_port(if_type), 0xf2);
5085 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
5086 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)

--- 32 unchanged lines hidden (view full) ---

5119 else
5120 iod->irq = irq_tab[0][tmp & 0x07];
5121 }
5122 }
5123 if ( iod->irq == -1 ) return -1;
5124
5125 return 0;
5126}
5225static int
5127static void
5226pc98_set_ioport(struct com_s *com)
5227{
5228 int if_type = com->pc98_if_type & 0x0f;
5128pc98_set_ioport(struct com_s *com)
5129{
5130 int if_type = com->pc98_if_type & 0x0f;
5229 int io = com->iobase & 0xff00;
5131 Port_t io = rman_get_start(com->ioportres) & 0xff00;
5230
5132
5231 if (IS_8251(com->pc98_if_type)) {
5232 pc98_check_sysclock();
5233 com->data_port = io | PC98SIO_data_port(if_type);
5234 com->cmd_port = io | PC98SIO_cmd_port(if_type);
5235 com->sts_port = io | PC98SIO_sts_port(if_type);
5236 com->in_modem_port = io | PC98SIO_in_modem_port(if_type);
5237 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type);
5238
5239 return 0;
5240 }
5241
5242 return -1;
5133 pc98_check_sysclock();
5134 com->data_port = io | PC98SIO_data_port(if_type);
5135 com->cmd_port = io | PC98SIO_cmd_port(if_type);
5136 com->sts_port = io | PC98SIO_sts_port(if_type);
5137 com->in_modem_port = io | PC98SIO_in_modem_port(if_type);
5138 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type);
5243}
5244static int
5245pc98_check_8251vfast(void)
5246{
5247 int i;
5248
5249 outb(I8251F_div, 0x8c);
5250 DELAY(10);

--- 31 unchanged lines hidden --- 		5139}
5140static int
5141pc98_check_8251vfast(void)
5142{
5143 int i;
5144
5145 outb(I8251F_div, 0x8c);
5146 DELAY(10);

--- 31 unchanged lines hidden ---