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sio.c (45267) sio.c (45783)
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 17 unchanged lines hidden (view full) ---

26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 17 unchanged lines hidden (view full) ---

26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
34 * $Id: sio.c,v 1.84 1999/04/01 13:44:15 kato Exp $
34 * $Id: sio.c,v 1.85 1999/04/03 15:51:14 kato Exp $
35 */
36
37#include "opt_comconsole.h"
38#include "opt_compat.h"
39#include "opt_ddb.h"
40#include "opt_devfs.h"
35 */
36
37#include "opt_comconsole.h"
38#include "opt_compat.h"
39#include "opt_ddb.h"
40#include "opt_devfs.h"
41#include "opt_sio.h"
41/* #include "opt_sio.h" */
42#include "sio.h"
42#include "sio.h"
43#include "pnp.h"
43/* #include "pnp.h" */
44#define NPNP 0
44
45/*
46 * Serial driver, based on 386BSD-0.1 com driver.
47 * Mostly rewritten to use pseudo-DMA.
48 * Works for National Semiconductor NS8250-NS16550AF UARTs.
49 * COM driver, based on HP dca driver.
50 *
51 * Changes for PC-Card integration:

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136#endif /* PC98 */
137
138#include <sys/param.h>
139#include <sys/systm.h>
140#include <sys/reboot.h>
141#include <sys/malloc.h>
142#include <sys/tty.h>
143#include <sys/proc.h>
45
46/*
47 * Serial driver, based on 386BSD-0.1 com driver.
48 * Mostly rewritten to use pseudo-DMA.
49 * Works for National Semiconductor NS8250-NS16550AF UARTs.
50 * COM driver, based on HP dca driver.
51 *
52 * Changes for PC-Card integration:

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137#endif /* PC98 */
138
139#include <sys/param.h>
140#include <sys/systm.h>
141#include <sys/reboot.h>
142#include <sys/malloc.h>
143#include <sys/tty.h>
144#include <sys/proc.h>
145#include <sys/module.h>
144#include <sys/conf.h>
145#include <sys/dkstat.h>
146#include <sys/fcntl.h>
147#include <sys/interrupt.h>
148#include <sys/kernel.h>
149#include <sys/syslog.h>
150#include <sys/sysctl.h>
146#include <sys/conf.h>
147#include <sys/dkstat.h>
148#include <sys/fcntl.h>
149#include <sys/interrupt.h>
150#include <sys/kernel.h>
151#include <sys/syslog.h>
152#include <sys/sysctl.h>
153#include <sys/bus.h>
154#include <machine/bus.h>
155#include <sys/rman.h>
151#ifdef DEVFS
152#include <sys/devfsext.h>
153#endif
154#include <sys/timepps.h>
155
156#ifdef DEVFS
157#include <sys/devfsext.h>
158#endif
159#include <sys/timepps.h>
160
156#include <machine/clock.h>
157#include <machine/ipl.h>
158#ifndef SMP
159#include <machine/lock.h>
160#endif
161
162#ifdef PC98
163#include <pc98/pc98/pc98.h>
164#include <pc98/pc98/pc98_machdep.h>
161#ifdef PC98
162#include <pc98/pc98/pc98.h>
163#include <pc98/pc98/pc98_machdep.h>
165#include <i386/isa/icu.h>
166#include <i386/isa/ic/i8251.h>
167#else
164#include <i386/isa/ic/i8251.h>
165#else
168#include <i386/isa/isa.h>
166#include <isa/isareg.h>
169#endif
167#endif
170#include <i386/isa/isa_device.h>
171#include <i386/isa/sioreg.h>
172#include <i386/isa/intr_machdep.h>
168#include <isa/isavar.h>
169#include <machine/lock.h>
173
170
171#include <machine/clock.h>
172#include <machine/ipl.h>
173#ifndef SMP
174#include <machine/lock.h>
175#endif
176#include <machine/resource.h>
177
178#include <isa/sioreg.h>
179
174#ifdef COM_ESP
175#include <i386/isa/ic/esp.h>
176#endif
177#include <i386/isa/ic/ns16550.h>
178#ifdef PC98
179#include <i386/isa/ic/rsa.h>
180#endif
181
180#ifdef COM_ESP
181#include <i386/isa/ic/esp.h>
182#endif
183#include <i386/isa/ic/ns16550.h>
184#ifdef PC98
185#include <i386/isa/ic/rsa.h>
186#endif
187
188#if 0
189
182#include "card.h"
183#if NCARD > 0
184#include <sys/module.h>
185#include <pccard/cardinfo.h>
186#include <pccard/slot.h>
187#endif
188
189#if NPNP > 0
190#include <i386/isa/pnp.h>
191#endif
192
190#include "card.h"
191#if NCARD > 0
192#include <sys/module.h>
193#include <pccard/cardinfo.h>
194#include <pccard/slot.h>
195#endif
196
197#if NPNP > 0
198#include <i386/isa/pnp.h>
199#endif
200
201#endif
202
203#ifndef __i386__
204#define disable_intr() 0
205#define enable_intr() 0
206#endif
207
193#ifdef SMP
194#define disable_intr() COM_DISABLE_INTR()
195#define enable_intr() COM_ENABLE_INTR()
196#endif /* SMP */
197
198#ifndef EXTRA_SIO
199#if NPNP > 0
200#define EXTRA_SIO MAX_PNP_CARDS

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214#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
215#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK)
216#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK)
217
218#ifdef COM_MULTIPORT
219/* checks in flags for multiport and which is multiport "master chip"
220 * for a given card
221 */
208#ifdef SMP
209#define disable_intr() COM_DISABLE_INTR()
210#define enable_intr() COM_ENABLE_INTR()
211#endif /* SMP */
212
213#ifndef EXTRA_SIO
214#if NPNP > 0
215#define EXTRA_SIO MAX_PNP_CARDS

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229#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev)))
230#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK)
231#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK)
232
233#ifdef COM_MULTIPORT
234/* checks in flags for multiport and which is multiport "master chip"
235 * for a given card
236 */
222#define COM_ISMULTIPORT(dev) ((dev)->id_flags & 0x01)
223#define COM_MPMASTER(dev) (((dev)->id_flags >> 8) & 0x0ff)
224#define COM_NOTAST4(dev) ((dev)->id_flags & 0x04)
237#define COM_ISMULTIPORT(flags) ((flags) & 0x01)
238#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
239#define COM_NOTAST4(flags) ((flags) & 0x04)
225#endif /* COM_MULTIPORT */
226
240#endif /* COM_MULTIPORT */
241
227#define COM_CONSOLE(dev) ((dev)->id_flags & 0x10)
228#define COM_FORCECONSOLE(dev) ((dev)->id_flags & 0x20)
229#define COM_LLCONSOLE(dev) ((dev)->id_flags & 0x40)
230#define COM_LOSESOUTINTS(dev) ((dev)->id_flags & 0x08)
231#define COM_NOFIFO(dev) ((dev)->id_flags & 0x02)
232#define COM_ST16650A(dev) ((dev)->id_flags & 0x20000)
233#define COM_C_NOPROBE (0x40000)
234#define COM_NOPROBE(dev) ((dev)->id_flags & COM_C_NOPROBE)
235#define COM_C_IIR_TXRDYBUG (0x80000)
236#define COM_IIR_TXRDYBUG(dev) ((dev)->id_flags & COM_C_IIR_TXRDYBUG)
237#define COM_FIFOSIZE(dev) (((dev)->id_flags & 0xff000000) >> 24)
242#define COM_CONSOLE(flags) ((flags) & 0x10)
243#define COM_FORCECONSOLE(flags) ((flags) & 0x20)
244#define COM_LLCONSOLE(flags) ((flags) & 0x40)
245#define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
246#define COM_NOFIFO(flags) ((flags) & 0x02)
247#define COM_ST16650A(flags) ((flags) & 0x20000)
248#define COM_C_NOPROBE (0x40000)
249#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE)
250#define COM_C_IIR_TXRDYBUG (0x80000)
251#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
252#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
238
239#ifdef PC98
240#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
241#else
242#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
243#endif
244
245/*

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289 u_char *l_head; /* next char to process */
290 u_char *l_tail; /* one past the last char to process */
291 struct lbq *l_next; /* next in queue */
292 bool_t l_queued; /* nonzero if queued */
293};
294
295/* com device structure */
296struct com_s {
253
254#ifdef PC98
255#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */
256#else
257#define com_scr 7 /* scratch register for 16450-16550 (R/W) */
258#endif
259
260/*

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304 u_char *l_head; /* next char to process */
305 u_char *l_tail; /* one past the last char to process */
306 struct lbq *l_next; /* next in queue */
307 bool_t l_queued; /* nonzero if queued */
308};
309
310/* com device structure */
311struct com_s {
297 u_int id_flags; /* Copy isa device falgas */
312 u_int flags; /* Copy isa device flags */
298 u_char state; /* miscellaneous flag bits */
299 bool_t active_out; /* nonzero if the callout device is open */
300 u_char cfcr_image; /* copy of value written to CFCR */
301#ifdef COM_ESP
302 bool_t esp; /* is this unit a hayes esp board? */
303#endif
304 u_char extra_state; /* more flag bits, separate for order trick */
305 u_char fifo_image; /* copy of value written to FIFO */

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410 void *devfs_token_cuai;
411#endif
412};
413
414#ifdef COM_ESP
415static int espattach __P((struct isa_device *isdp, struct com_s *com,
416 Port_t esp_port));
417#endif
313 u_char state; /* miscellaneous flag bits */
314 bool_t active_out; /* nonzero if the callout device is open */
315 u_char cfcr_image; /* copy of value written to CFCR */
316#ifdef COM_ESP
317 bool_t esp; /* is this unit a hayes esp board? */
318#endif
319 u_char extra_state; /* more flag bits, separate for order trick */
320 u_char fifo_image; /* copy of value written to FIFO */

--- 104 unchanged lines hidden (view full) ---

425 void *devfs_token_cuai;
426#endif
427};
428
429#ifdef COM_ESP
430static int espattach __P((struct isa_device *isdp, struct com_s *com,
431 Port_t esp_port));
432#endif
418static int sioattach __P((struct isa_device *dev));
433static int sioattach __P((device_t dev));
434
419static timeout_t siobusycheck;
420static timeout_t siodtrwakeup;
421static void comhardclose __P((struct com_s *com));
422static void sioinput __P((struct com_s *com));
435static timeout_t siobusycheck;
436static timeout_t siodtrwakeup;
437static void comhardclose __P((struct com_s *com));
438static void sioinput __P((struct com_s *com));
423static ointhand2_t siointr;
424static void siointr1 __P((struct com_s *com));
439static void siointr1 __P((struct com_s *com));
440static void siointr __P((void *arg));
425static int commctl __P((struct com_s *com, int bits, int how));
426static int comparam __P((struct tty *tp, struct termios *t));
427static swihand_t siopoll;
441static int commctl __P((struct com_s *com, int bits, int how));
442static int comparam __P((struct tty *tp, struct termios *t));
443static swihand_t siopoll;
428static int sioprobe __P((struct isa_device *dev));
444static int sioprobe __P((device_t dev));
429static void siosettimeout __P((void));
430static int siosetwater __P((struct com_s *com, speed_t speed));
431static void comstart __P((struct tty *tp));
432static timeout_t comwakeup;
433static void disc_optim __P((struct tty *tp, struct termios *t,
434 struct com_s *com));
435
436
437static char driver_name[] = "sio";
438
439/* table and macro for fast conversion from a unit number to its com struct */
445static void siosettimeout __P((void));
446static int siosetwater __P((struct com_s *com, speed_t speed));
447static void comstart __P((struct tty *tp));
448static timeout_t comwakeup;
449static void disc_optim __P((struct tty *tp, struct termios *t,
450 struct com_s *com));
451
452
453static char driver_name[] = "sio";
454
455/* table and macro for fast conversion from a unit number to its com struct */
440static struct com_s *p_com_addr[NSIOTOT];
441#define com_addr(unit) (p_com_addr[unit])
456static devclass_t sio_devclass;
457#define com_addr(unit) ((struct com_s *) \
458 devclass_get_softc(sio_devclass, unit))
442
459
443struct isa_driver siodriver = {
444 sioprobe, sioattach, driver_name
460static device_method_t sio_methods[] = {
461 /* Device interface */
462 DEVMETHOD(device_probe, sioprobe),
463 DEVMETHOD(device_attach, sioattach),
464
465 { 0, 0 }
445};
446
466};
467
468static driver_t sio_driver = {
469 driver_name,
470 sio_methods,
471 DRIVER_TYPE_TTY,
472 sizeof(struct com_s),
473};
474
447static d_open_t sioopen;
448static d_close_t sioclose;
449static d_read_t sioread;
450static d_write_t siowrite;
451static d_ioctl_t sioioctl;
452static d_stop_t siostop;
453static d_devtotty_t siodevtotty;
454
455#define CDEV_MAJOR 28
456static struct cdevsw sio_cdevsw = {
457 sioopen, sioclose, sioread, siowrite,
458 sioioctl, siostop, noreset, siodevtotty,
459 ttpoll, nommap, NULL, driver_name,
460 NULL, -1, nodump, nopsize,
461 D_TTY,
462};
463
475static d_open_t sioopen;
476static d_close_t sioclose;
477static d_read_t sioread;
478static d_write_t siowrite;
479static d_ioctl_t sioioctl;
480static d_stop_t siostop;
481static d_devtotty_t siodevtotty;
482
483#define CDEV_MAJOR 28
484static struct cdevsw sio_cdevsw = {
485 sioopen, sioclose, sioread, siowrite,
486 sioioctl, siostop, noreset, siodevtotty,
487 ttpoll, nommap, NULL, driver_name,
488 NULL, -1, nodump, nopsize,
489 D_TTY,
490};
491
464static int comconsole = -1;
492int comconsole = -1;
465static volatile speed_t comdefaultrate = CONSPEED;
493static volatile speed_t comdefaultrate = CONSPEED;
494static volatile speed_t gdbdefaultrate = CONSPEED;
466static u_int com_events; /* input chars + weighted output completions */
467static Port_t siocniobase;
495static u_int com_events; /* input chars + weighted output completions */
496static Port_t siocniobase;
497static Port_t siogdbiobase;
468static bool_t sio_registered;
469static int sio_timeout;
470static int sio_timeouts_until_log;
471static struct callout_handle sio_timeout_handle
472 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
473#if 0 /* XXX */
474static struct tty *sio_tty[NSIOTOT];
475#else

--- 37 unchanged lines hidden (view full) ---

513static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod));
514static int pc98_check_i8251_interrupt __P((struct com_s *com));
515static int pc98_i8251_get_cmd __P((struct com_s *com));
516static int pc98_i8251_get_mod __P((struct com_s *com));
517static void pc98_i8251_set_cmd __P((struct com_s *com, int x));
518static void pc98_i8251_or_cmd __P((struct com_s *com, int x));
519static void pc98_i8251_clear_cmd __P((struct com_s *com, int x));
520static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x));
498static bool_t sio_registered;
499static int sio_timeout;
500static int sio_timeouts_until_log;
501static struct callout_handle sio_timeout_handle
502 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
503#if 0 /* XXX */
504static struct tty *sio_tty[NSIOTOT];
505#else

--- 37 unchanged lines hidden (view full) ---

543static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod));
544static int pc98_check_i8251_interrupt __P((struct com_s *com));
545static int pc98_i8251_get_cmd __P((struct com_s *com));
546static int pc98_i8251_get_mod __P((struct com_s *com));
547static void pc98_i8251_set_cmd __P((struct com_s *com, int x));
548static void pc98_i8251_or_cmd __P((struct com_s *com, int x));
549static void pc98_i8251_clear_cmd __P((struct com_s *com, int x));
550static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x));
521static int pc98_check_if_type __P((struct isa_device *dev, struct siodev *iod));
551static int pc98_check_if_type __P((device_t dev, struct siodev *iod));
522static void pc98_check_sysclock __P((void));
523static int pc98_set_ioport __P((struct com_s *com, int id_flags));
524
525#define com_int_Tx_disable(com) \
526 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
527#define com_int_Tx_enable(com) \
528 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
529#define com_int_Rx_disable(com) \

--- 401 unchanged lines hidden (view full) ---

931 com = com_addr(devi->isahd.id_unit);
932 if (com && !com->gone)
933 siointr1(com_addr(devi->isahd.id_unit));
934 COM_UNLOCK();
935 return(1);
936}
937#endif /* NCARD > 0 */
938
552static void pc98_check_sysclock __P((void));
553static int pc98_set_ioport __P((struct com_s *com, int id_flags));
554
555#define com_int_Tx_disable(com) \
556 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
557#define com_int_Tx_enable(com) \
558 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
559#define com_int_Rx_disable(com) \

--- 401 unchanged lines hidden (view full) ---

961 com = com_addr(devi->isahd.id_unit);
962 if (com && !com->gone)
963 siointr1(com_addr(devi->isahd.id_unit));
964 COM_UNLOCK();
965 return(1);
966}
967#endif /* NCARD > 0 */
968
969#define SET_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) | (bit))
970#define CLR_FLAG(dev, bit) isa_set_flags(dev, isa_get_flags(dev) & ~(bit))
971
939static int
940sioprobe(dev)
972static int
973sioprobe(dev)
941 struct isa_device *dev;
974 device_t dev;
942{
943 static bool_t already_init;
944 bool_t failures[10];
945 int fn;
975{
976 static bool_t already_init;
977 bool_t failures[10];
978 int fn;
946 struct isa_device *idev;
979 device_t idev;
947 Port_t iobase;
948 intrmask_t irqmap[4];
949 intrmask_t irqs;
950 u_char mcr_image;
951 int result;
980 Port_t iobase;
981 intrmask_t irqmap[4];
982 intrmask_t irqs;
983 u_char mcr_image;
984 int result;
952 struct isa_device *xdev;
985 device_t xdev;
986 u_int flags = isa_get_flags(dev);
953#ifdef PC98
954 int irqout=0;
955 int ret = 0;
956 int tmp;
957 int port_shift = 0;
958 struct siodev iod;
959 Port_t rsabase = NULL;
960#endif
961
962 if (!already_init) {
963 /*
964 * Turn off MCR_IENABLE for all likely serial ports. An unused
965 * port with its MCR_IENABLE gate open will inhibit interrupts
966 * from any used port that shares the interrupt vector.
967 * XXX the gate enable is elsewhere for some multiports.
968 */
987#ifdef PC98
988 int irqout=0;
989 int ret = 0;
990 int tmp;
991 int port_shift = 0;
992 struct siodev iod;
993 Port_t rsabase = NULL;
994#endif
995
996 if (!already_init) {
997 /*
998 * Turn off MCR_IENABLE for all likely serial ports. An unused
999 * port with its MCR_IENABLE gate open will inhibit interrupts
1000 * from any used port that shares the interrupt vector.
1001 * XXX the gate enable is elsewhere for some multiports.
1002 */
969 for (xdev = isa_devtab_tty; xdev->id_driver != NULL; xdev++)
1003 device_t *devs;
1004 int count, i;
1005
1006 devclass_get_devices(sio_devclass, &devs, &count);
970#ifdef PC98
1007#ifdef PC98
971 if (xdev->id_driver == &siodriver && xdev->id_enabled) {
972 tmp = (xdev->id_flags >> 24) & 0xff;
1008 for (i = 0; i < count; i++) {
1009 xdev = devs[i];
1010 tmp = (flags >> 24) & 0xff;
973 if (IS_8251(tmp))
1011 if (IS_8251(tmp))
974 outb((xdev->id_iobase & 0xff00) | PC98SIO_cmd_port(tmp & 0x0f), 0xf2);
1012 outb((isa_get_port(xdev) & 0xff00) | PC98SIO_cmd_port(tmp & 0x0f), 0xf2);
975 else
976 if (tmp == COM_IF_RSA98III) {
1013 else
1014 if (tmp == COM_IF_RSA98III) {
977 rsabase = xdev->id_iobase & 0xfff0;
978#if 0
979 if (rsabase != xdev->id_iobase)
980 return(0);
981#endif
982 outb(xdev->id_iobase + 8 + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1015 rsabase = isa_get_port(xdev) & 0xfff0;
1016 outb(isa_get_port(xdev) + 8 + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
983 } else
1017 } else
984 outb(xdev->id_iobase + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
985 }
1018 outb(isa_get_port(xdev) + (com_mcr << if_16550a_type[tmp & 0x0f].port_shift), 0);
1019 }
986#else
1020#else
987 if (xdev->id_driver == &siodriver && xdev->id_enabled)
988 outb(xdev->id_iobase + com_mcr, 0);
1021 for (i = 0; i < count; i++) {
1022 xdev = devs[i];
1023 outb(isa_get_port(xdev) + com_mcr, 0);
1024 }
989#endif
1025#endif
1026 free(devs, M_TEMP);
990 already_init = TRUE;
991 }
992
1027 already_init = TRUE;
1028 }
1029
993 if (COM_LLCONSOLE(dev)) {
994 printf("sio%d: reserved for low-level i/o\n", dev->id_unit);
995 return (0);
1030 if (COM_LLCONSOLE(flags)) {
1031 printf("sio%d: reserved for low-level i/o\n",
1032 device_get_unit(dev));
1033 return (ENXIO);
996 }
997
998#ifdef PC98
999 DELAY(10);
1000
1001 /*
1002 * If the port is i8251 UART (internal, B98_01)
1003 */
1004 if (pc98_check_if_type(dev, &iod) == -1)
1034 }
1035
1036#ifdef PC98
1037 DELAY(10);
1038
1039 /*
1040 * If the port is i8251 UART (internal, B98_01)
1041 */
1042 if (pc98_check_if_type(dev, &iod) == -1)
1005 return 0;
1043 return 0;
1006 if (iod.irq > 0)
1044 if (iod.irq > 0)
1007 dev->id_irq = 1 << iod.irq;
1045 isa_set_irq(dev, iod.irq);
1008 if (IS_8251(iod.if_type)) {
1009 outb(iod.cmd, 0);
1010 DELAY(10);
1011 outb(iod.cmd, 0);
1012 DELAY(10);
1013 outb(iod.cmd, 0);
1014 DELAY(10);
1015 outb(iod.cmd, CMD8251_RESET);

--- 34 unchanged lines hidden (view full) ---

1050 * Point idev to the device struct giving the correct id_irq.
1051 * This is the struct for the master device if there is one.
1052 */
1053 idev = dev;
1054 mcr_image = MCR_IENABLE;
1055#ifdef PC98
1056 if (iod.if_type == COM_IF_RSA98III) {
1057 mcr_image = 0;
1046 if (IS_8251(iod.if_type)) {
1047 outb(iod.cmd, 0);
1048 DELAY(10);
1049 outb(iod.cmd, 0);
1050 DELAY(10);
1051 outb(iod.cmd, 0);
1052 DELAY(10);
1053 outb(iod.cmd, CMD8251_RESET);

--- 34 unchanged lines hidden (view full) ---

1088 * Point idev to the device struct giving the correct id_irq.
1089 * This is the struct for the master device if there is one.
1090 */
1091 idev = dev;
1092 mcr_image = MCR_IENABLE;
1093#ifdef PC98
1094 if (iod.if_type == COM_IF_RSA98III) {
1095 mcr_image = 0;
1058 rsabase = idev->id_iobase & 0xfff0;
1059 if (rsabase != idev->id_iobase)
1096 rsabase = isa_get_port(idev) & 0xfff0;
1097 if (rsabase != isa_get_port(idev))
1060 return(0);
1061 outb(rsabase + rsa_msr, 0x04);
1062 outb(rsabase + rsa_frr, 0x00);
1063 if ((inb(rsabase + rsa_srr) & 0x36) != 0x36)
1064 return (0);
1065 outb(rsabase + rsa_ier, 0x00);
1066 outb(rsabase + rsa_frr, 0x00);
1067 outb(rsabase + rsa_tivsr, 0x00);
1068 outb(rsabase + rsa_tcr, 0x00);
1069 }
1070#endif /* PC98 */
1071#ifdef COM_MULTIPORT
1098 return(0);
1099 outb(rsabase + rsa_msr, 0x04);
1100 outb(rsabase + rsa_frr, 0x00);
1101 if ((inb(rsabase + rsa_srr) & 0x36) != 0x36)
1102 return (0);
1103 outb(rsabase + rsa_ier, 0x00);
1104 outb(rsabase + rsa_frr, 0x00);
1105 outb(rsabase + rsa_tivsr, 0x00);
1106 outb(rsabase + rsa_tcr, 0x00);
1107 }
1108#endif /* PC98 */
1109#ifdef COM_MULTIPORT
1072 if (COM_ISMULTIPORT(dev)) {
1073 idev = find_isadev(isa_devtab_tty, &siodriver,
1074 COM_MPMASTER(dev));
1110 if (COM_ISMULTIPORT(flags)) {
1111 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
1075 if (idev == NULL) {
1076 printf("sio%d: master device %d not configured\n",
1112 if (idev == NULL) {
1113 printf("sio%d: master device %d not configured\n",
1077 dev->id_unit, COM_MPMASTER(dev));
1078 dev->id_irq = 0;
1114 device_get_unit(dev), COM_MPMASTER(flags));
1115 isa_set_irq(dev, 0);
1079 idev = dev;
1080 }
1081#ifndef PC98
1116 idev = dev;
1117 }
1118#ifndef PC98
1082 if (!COM_NOTAST4(dev)) {
1083 outb(idev->id_iobase + com_scr,
1084 idev->id_irq ? 0x80 : 0);
1119 if (!COM_NOTAST4(flags)) {
1120 outb(isa_get_port(idev) + com_scr,
1121 isa_get_irq(idev) >= 0 ? 0x80 : 0);
1085 mcr_image = 0;
1086 }
1087#endif /* !PC98 */
1088 }
1089#endif /* COM_MULTIPORT */
1122 mcr_image = 0;
1123 }
1124#endif /* !PC98 */
1125 }
1126#endif /* COM_MULTIPORT */
1090 if (idev->id_irq == 0)
1127 if (isa_get_irq(idev) < 0)
1091 mcr_image = 0;
1092
1093#ifdef PC98
1094 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1095 if (tmp != -1) {
1096 /* MC16550II */
1128 mcr_image = 0;
1129
1130#ifdef PC98
1131 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1132 if (tmp != -1) {
1133 /* MC16550II */
1097 switch (idev->id_irq) {
1098 case IRQ3: irqout = 4; break;
1099 case IRQ5: irqout = 5; break;
1100 case IRQ6: irqout = 6; break;
1101 case IRQ12: irqout = 7; break;
1134 switch (isa_get_irq(idev)) {
1135 case 3: irqout = 4; break;
1136 case 5: irqout = 5; break;
1137 case 6: irqout = 6; break;
1138 case 12: irqout = 7; break;
1102 default:
1139 default:
1103 printf("sio%d: irq configuration error\n", dev->id_unit);
1140 printf("sio%d: irq configuration error\n",
1141 device_get_unit(dev));
1104 return (0);
1105 }
1142 return (0);
1143 }
1106 outb((dev->id_iobase & 0x00ff) | tmp, irqout);
1144 outb((isa_get_port(dev) & 0x00ff) | tmp, irqout);
1107 }
1108 port_shift = if_16550a_type[iod.if_type & 0x0f].port_shift;
1109#endif
1110 bzero(failures, sizeof failures);
1145 }
1146 port_shift = if_16550a_type[iod.if_type & 0x0f].port_shift;
1147#endif
1148 bzero(failures, sizeof failures);
1149 iobase = isa_get_port(dev);
1111#ifdef PC98
1112 if (iod.if_type == COM_IF_RSA98III)
1150#ifdef PC98
1151 if (iod.if_type == COM_IF_RSA98III)
1113 iobase = dev->id_iobase + 8;
1114 else
1152 iobase += 8;
1115#endif
1153#endif
1116 iobase = dev->id_iobase;
1117
1118 /*
1119 * We don't want to get actual interrupts, just masked ones.
1120 * Interrupts from this line should already be masked in the ICU,
1121 * but mask them in the processor as well in case there are some
1122 * (misconfigured) shared interrupts.
1123 */
1124 disable_intr();

--- 60 unchanged lines hidden (view full) ---

1185 * IER_ETXRDY generates an interrupt independent of the current
1186 * setting and independent of whether the THR is empty. On 16450's,
1187 * setting IER_ETXRDY generates an interrupt independent of the
1188 * current setting. On 16550A's, setting IER_ETXRDY only
1189 * generates an interrupt when IER_ETXRDY is not already set.
1190 */
1191#ifdef PC98
1192 outb(iobase + (com_ier << port_shift), IER_ETXRDY);
1154
1155 /*
1156 * We don't want to get actual interrupts, just masked ones.
1157 * Interrupts from this line should already be masked in the ICU,
1158 * but mask them in the processor as well in case there are some
1159 * (misconfigured) shared interrupts.
1160 */
1161 disable_intr();

--- 60 unchanged lines hidden (view full) ---

1222 * IER_ETXRDY generates an interrupt independent of the current
1223 * setting and independent of whether the THR is empty. On 16450's,
1224 * setting IER_ETXRDY generates an interrupt independent of the
1225 * current setting. On 16550A's, setting IER_ETXRDY only
1226 * generates an interrupt when IER_ETXRDY is not already set.
1227 */
1228#ifdef PC98
1229 outb(iobase + (com_ier << port_shift), IER_ETXRDY);
1193 if (iod.if_type == COM_IF_RSA98III) {
1230 if (iod.if_type == COM_IF_RSA98III)
1194 outb(rsabase + rsa_ier, 0x04);
1231 outb(rsabase + rsa_ier, 0x04);
1195 }
1196#else
1197 outb(iobase + com_ier, IER_ETXRDY);
1198#endif /* PC98 */
1199
1200 /*
1201 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1202 * an interrupt. They'd better generate one for actually doing
1203 * output. Loopback may be broken on the same incompatibles but

--- 19 unchanged lines hidden (view full) ---

1223#else
1224 outb(iobase + com_mcr, mcr_image);
1225#endif /* PC98 */
1226
1227 /*
1228 * It's a definitly Serial PCMCIA(16550A), but still be required
1229 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1230 */
1232#else
1233 outb(iobase + com_ier, IER_ETXRDY);
1234#endif /* PC98 */
1235
1236 /*
1237 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1238 * an interrupt. They'd better generate one for actually doing
1239 * output. Loopback may be broken on the same incompatibles but

--- 19 unchanged lines hidden (view full) ---

1259#else
1260 outb(iobase + com_mcr, mcr_image);
1261#endif /* PC98 */
1262
1263 /*
1264 * It's a definitly Serial PCMCIA(16550A), but still be required
1265 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... )
1266 */
1231 if ( COM_NOPROBE(dev) ) {
1267 if ( COM_NOPROBE(flags) ) {
1232 /* Reading IIR register twice */
1233 for ( fn = 0; fn < 2; fn ++ ) {
1234 DELAY(10000);
1235#ifdef PC98
1236 failures[6] = inb(iobase + (com_iir << port_shift));
1237#else
1238 failures[6] = inb(iobase + com_iir);
1239#endif
1240 }
1241 /* Check IIR_TXRDY clear ? */
1242#ifdef PC98
1268 /* Reading IIR register twice */
1269 for ( fn = 0; fn < 2; fn ++ ) {
1270 DELAY(10000);
1271#ifdef PC98
1272 failures[6] = inb(iobase + (com_iir << port_shift));
1273#else
1274 failures[6] = inb(iobase + com_iir);
1275#endif
1276 }
1277 /* Check IIR_TXRDY clear ? */
1278#ifdef PC98
1243 result = if_16550a_type[iod.if_type & 0x0f].io_size;
1279 isa_set_portsize(dev,
1280 if_16550a_type[iod.if_type & 0x0f].io_size);
1244#else
1281#else
1245 result = IO_COMSIZE;
1282 isa_set_portsize(dev, IO_COMSIZE);
1246#endif
1283#endif
1284 result = 0;
1247 if ( failures[6] & IIR_TXRDY ) {
1248 /* Nop, Double check with clearing IER */
1249#ifdef PC98
1250 outb(iobase + (com_ier << port_shift), 0);
1251 if (inb(iobase +
1252 (com_iir << port_shift)) & IIR_NOPEND) {
1253#else
1254 outb(iobase + com_ier, 0);
1255 if ( inb(iobase + com_iir) & IIR_NOPEND ) {
1256#endif
1257 /* Ok. we're familia this gang */
1285 if ( failures[6] & IIR_TXRDY ) {
1286 /* Nop, Double check with clearing IER */
1287#ifdef PC98
1288 outb(iobase + (com_ier << port_shift), 0);
1289 if (inb(iobase +
1290 (com_iir << port_shift)) & IIR_NOPEND) {
1291#else
1292 outb(iobase + com_ier, 0);
1293 if ( inb(iobase + com_iir) & IIR_NOPEND ) {
1294#endif
1295 /* Ok. we're familia this gang */
1258 dev->id_flags |= COM_C_IIR_TXRDYBUG; /* Set IIR_TXRDYBUG */
1296 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); /* Set IIR_TXRDYBUG */
1259 } else {
1260 /* Unknow, Just omit this chip.. XXX*/
1297 } else {
1298 /* Unknow, Just omit this chip.. XXX*/
1261 result = 0;
1299 result = ENXIO;
1262 }
1263 } else {
1264 /* OK. this is well-known guys */
1300 }
1301 } else {
1302 /* OK. this is well-known guys */
1265 dev->id_flags &= ~COM_C_IIR_TXRDYBUG; /*Clear IIR_TXRDYBUG*/
1303 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); /*Clear IIR_TXRDYBUG*/
1266 }
1267#ifdef PC98
1268 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1269#else
1270 outb(iobase + com_cfcr, CFCR_8BITS);
1271#endif
1272 enable_intr();
1304 }
1305#ifdef PC98
1306 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1307#else
1308 outb(iobase + com_cfcr, CFCR_8BITS);
1309#endif
1310 enable_intr();
1273 return (iobase == siocniobase ? IO_COMSIZE : result);
1311 return (iobase == siocniobase ? 0 : result);
1274 }
1275
1276 /*
1277 * Check that
1278 * o the CFCR, IER and MCR in UART hold the values written to them
1279 * (the values happen to be all distinct - this is good for
1280 * avoiding false positive tests from bus echoes).
1281 * o an output interrupt is generated and its vector is correct.

--- 9 unchanged lines hidden (view full) ---

1291 failures[1] = inb(iobase + com_ier) - IER_ETXRDY;
1292 failures[2] = inb(iobase + com_mcr) - mcr_image;
1293#endif
1294 DELAY(10000); /* Some internal modems need this time */
1295 irqmap[1] = isa_irq_pending();
1296#ifdef PC98
1297 failures[4] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1298 - IIR_TXRDY;
1312 }
1313
1314 /*
1315 * Check that
1316 * o the CFCR, IER and MCR in UART hold the values written to them
1317 * (the values happen to be all distinct - this is good for
1318 * avoiding false positive tests from bus echoes).
1319 * o an output interrupt is generated and its vector is correct.

--- 9 unchanged lines hidden (view full) ---

1329 failures[1] = inb(iobase + com_ier) - IER_ETXRDY;
1330 failures[2] = inb(iobase + com_mcr) - mcr_image;
1331#endif
1332 DELAY(10000); /* Some internal modems need this time */
1333 irqmap[1] = isa_irq_pending();
1334#ifdef PC98
1335 failures[4] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1336 - IIR_TXRDY;
1299 if (iod.if_type == COM_IF_RSA98III) {
1337 if (iod.if_type == COM_IF_RSA98III)
1300 inb(rsabase + rsa_srr);
1338 inb(rsabase + rsa_srr);
1301 }
1302#else
1303 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY;
1304#endif
1305 DELAY(1000); /* XXX */
1306 irqmap[2] = isa_irq_pending();
1307#ifdef PC98
1308 failures[6] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1309 - IIR_NOPEND;
1339#else
1340 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY;
1341#endif
1342 DELAY(1000); /* XXX */
1343 irqmap[2] = isa_irq_pending();
1344#ifdef PC98
1345 failures[6] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK)
1346 - IIR_NOPEND;
1310 if (iod.if_type == COM_IF_RSA98III) {
1347 if (iod.if_type == COM_IF_RSA98III)
1311 inb(rsabase + rsa_srr);
1348 inb(rsabase + rsa_srr);
1312 }
1313#else
1314 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1315#endif
1316
1317 /*
1318 * Turn off all device interrupts and check that they go off properly.
1319 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1320 * the OUT2 output of the UART to
1321 * the ICU input. Closing the gate would give a floating ICU input
1349#else
1350 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1351#endif
1352
1353 /*
1354 * Turn off all device interrupts and check that they go off properly.
1355 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1356 * the OUT2 output of the UART to
1357 * the ICU input. Closing the gate would give a floating ICU input
1322 * (unless there is another device driving it) and spurious interrupts.
1358 * (unless there is another device driving at) and spurious interrupts.
1323 * (On the system that this was first tested on, the input floats high
1324 * and gives a (masked) interrupt as soon as the gate is closed.)
1325 */
1326#ifdef PC98
1327 outb(iobase + (com_ier << port_shift), 0);
1328 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1329 failures[7] = inb(iobase + (com_ier << port_shift));
1359 * (On the system that this was first tested on, the input floats high
1360 * and gives a (masked) interrupt as soon as the gate is closed.)
1361 */
1362#ifdef PC98
1363 outb(iobase + (com_ier << port_shift), 0);
1364 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS);
1365 failures[7] = inb(iobase + (com_ier << port_shift));
1330 if (iod.if_type == COM_IF_RSA98III) {
1366 if (iod.if_type == COM_IF_RSA98III)
1331 outb(rsabase + rsa_ier, 0x00);
1367 outb(rsabase + rsa_ier, 0x00);
1332 }
1333#else
1334 outb(iobase + com_ier, 0);
1335 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1336 failures[7] = inb(iobase + com_ier);
1337#endif
1338 DELAY(1000); /* XXX */
1339 irqmap[3] = isa_irq_pending();
1340#ifdef PC98

--- 5 unchanged lines hidden (view full) ---

1346 }
1347#else
1348 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1349#endif
1350
1351 enable_intr();
1352
1353 irqs = irqmap[1] & ~irqmap[0];
1368#else
1369 outb(iobase + com_ier, 0);
1370 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1371 failures[7] = inb(iobase + com_ier);
1372#endif
1373 DELAY(1000); /* XXX */
1374 irqmap[3] = isa_irq_pending();
1375#ifdef PC98

--- 5 unchanged lines hidden (view full) ---

1381 }
1382#else
1383 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND;
1384#endif
1385
1386 enable_intr();
1387
1388 irqs = irqmap[1] & ~irqmap[0];
1354 if (idev->id_irq != 0 && (idev->id_irq & irqs) == 0)
1389 if (isa_get_irq(idev) >= 0 && ((1 << isa_get_irq(idev)) & irqs) == 0)
1355 printf(
1356 "sio%d: configured irq %d not in bitmap of probed irqs %#x\n",
1390 printf(
1391 "sio%d: configured irq %d not in bitmap of probed irqs %#x\n",
1357 dev->id_unit, ffs(idev->id_irq) - 1, irqs);
1392 device_get_unit(dev), isa_get_irq(idev), irqs);
1358 if (bootverbose)
1359 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1393 if (bootverbose)
1394 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1360 dev->id_unit, irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1395 device_get_unit(dev),
1396 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1361
1362#ifdef PC98
1397
1398#ifdef PC98
1363 result = if_16550a_type[iod.if_type & 0x0f].io_size;
1399 isa_set_portsize(dev, if_16550a_type[iod.if_type & 0x0f].io_size);
1364#else
1400#else
1365 result = IO_COMSIZE;
1401 isa_set_portsize(dev, IO_COMSIZE);
1366#endif
1402#endif
1403 result = 0;
1367 for (fn = 0; fn < sizeof failures; ++fn)
1368 if (failures[fn]) {
1369#ifdef PC98
1370 outb(iobase + (com_mcr << port_shift), 0);
1371#else
1372 outb(iobase + com_mcr, 0);
1373#endif
1404 for (fn = 0; fn < sizeof failures; ++fn)
1405 if (failures[fn]) {
1406#ifdef PC98
1407 outb(iobase + (com_mcr << port_shift), 0);
1408#else
1409 outb(iobase + com_mcr, 0);
1410#endif
1374 result = 0;
1411 result = ENXIO;
1375 if (bootverbose) {
1376 printf("sio%d: probe failed test(s):",
1412 if (bootverbose) {
1413 printf("sio%d: probe failed test(s):",
1377 dev->id_unit);
1414 device_get_unit(dev));
1378 for (fn = 0; fn < sizeof failures; ++fn)
1379 if (failures[fn])
1380 printf(" %d", fn);
1381 printf("\n");
1382 }
1383 break;
1384 }
1415 for (fn = 0; fn < sizeof failures; ++fn)
1416 if (failures[fn])
1417 printf(" %d", fn);
1418 printf("\n");
1419 }
1420 break;
1421 }
1385 return (iobase == siocniobase ? IO_COMSIZE : result);
1422 return (iobase == siocniobase ? 0 : result);
1386}
1387
1388#ifdef COM_ESP
1389static int
1390espattach(isdp, com, esp_port)
1391 struct isa_device *isdp;
1392 struct com_s *com;
1393 Port_t esp_port;

--- 68 unchanged lines hidden (view full) ---

1462 */
1463 com->esp = TRUE;
1464 com->esp_port = esp_port;
1465 return (1);
1466}
1467#endif /* COM_ESP */
1468
1469static int
1423}
1424
1425#ifdef COM_ESP
1426static int
1427espattach(isdp, com, esp_port)
1428 struct isa_device *isdp;
1429 struct com_s *com;
1430 Port_t esp_port;

--- 68 unchanged lines hidden (view full) ---

1499 */
1500 com->esp = TRUE;
1501 com->esp_port = esp_port;
1502 return (1);
1503}
1504#endif /* COM_ESP */
1505
1506static int
1470sioattach(isdp)
1471 struct isa_device *isdp;
1507sioattach(dev)
1508 device_t dev;
1472{
1473 struct com_s *com;
1509{
1510 struct com_s *com;
1474 dev_t dev;
1475#ifdef COM_ESP
1476 Port_t *espp;
1477#endif
1511#ifdef COM_ESP
1512 Port_t *espp;
1513#endif
1478#ifdef COM_MULTIPORT
1479 struct isa_device *idev;
1480#endif
1481 Port_t iobase;
1482 int s;
1483 int unit;
1514 Port_t iobase;
1515 int s;
1516 int unit;
1517 void *ih;
1518 struct resource *res;
1519 int zero = 0;
1520 u_int flags = isa_get_flags(dev);
1484#ifdef PC98
1485 int port_shift = 0;
1521#ifdef PC98
1522 int port_shift = 0;
1523 u_char *obuf;
1486 u_long obufsize;
1487#endif
1488
1524 u_long obufsize;
1525#endif
1526
1489 isdp->id_ointr = siointr;
1527#if 0
1490 isdp->id_ri_flags |= RI_FAST;
1528 isdp->id_ri_flags |= RI_FAST;
1529#endif
1530 iobase = isa_get_port(dev);
1491#ifdef PC98
1531#ifdef PC98
1492 if (((isdp->id_flags >> 24) & 0xff) == COM_IF_RSA98III)
1493 iobase = isdp->id_iobase + 8;
1494 else
1532 if (((flags >> 24) & 0xff) == COM_IF_RSA98III)
1533 iobase += 8;
1495#endif
1534#endif
1496 iobase = isdp->id_iobase;
1497 unit = isdp->id_unit;
1498#ifndef PC98
1499 com = malloc(sizeof *com, M_DEVBUF, M_NOWAIT);
1500#else
1535 unit = device_get_unit(dev);
1536 com = device_get_softc(dev);
1537#ifdef PC98
1501 obufsize = 256;
1538 obufsize = 256;
1502 if (((isdp->id_flags >> 24) & 0xff) == COM_IF_RSA98III)
1539 if (((flags >> 24) & 0xff) == COM_IF_RSA98III)
1503 obufsize = 2048;
1540 obufsize = 2048;
1504 com = malloc((sizeof *com) + obufsize * 2, M_DEVBUF, M_NOWAIT);
1505#endif
1506 if (com == NULL)
1541 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL)
1507 return (0);
1542 return (0);
1543 bzero(obuf, obufsize * 2);
1544#endif
1508
1509 /*
1510 * sioprobe() has initialized the device registers as follows:
1511 * o cfcr = CFCR_8BITS.
1512 * It is most important that CFCR_DLAB is off, so that the
1513 * data port is not hidden when we enable interrupts.
1514 * o ier = 0.
1515 * Interrupts are only enabled when the line is open.
1516 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1517 * interrupt control register or the config specifies no irq.
1518 * Keeping MCR_DTR and MCR_RTS off might stop the external
1519 * device from sending before we are ready.
1520 */
1521 bzero(com, sizeof *com);
1522#ifdef PC98
1523 com->obufsize = obufsize;
1545
1546 /*
1547 * sioprobe() has initialized the device registers as follows:
1548 * o cfcr = CFCR_8BITS.
1549 * It is most important that CFCR_DLAB is off, so that the
1550 * data port is not hidden when we enable interrupts.
1551 * o ier = 0.
1552 * Interrupts are only enabled when the line is open.
1553 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1554 * interrupt control register or the config specifies no irq.
1555 * Keeping MCR_DTR and MCR_RTS off might stop the external
1556 * device from sending before we are ready.
1557 */
1558 bzero(com, sizeof *com);
1559#ifdef PC98
1560 com->obufsize = obufsize;
1524 com->obuf1 = (u_char *)com + (sizeof *com);
1525 com->obuf2 = com->obuf1 + obufsize;
1526 bzero(com->obuf1, obufsize * 2);
1561 com->obuf1 = obuf;
1562 com->obuf2 = obuf + obufsize;
1527#endif
1528 com->unit = unit;
1529 com->cfcr_image = CFCR_8BITS;
1530 com->dtr_wait = 3 * hz;
1563#endif
1564 com->unit = unit;
1565 com->cfcr_image = CFCR_8BITS;
1566 com->dtr_wait = 3 * hz;
1531 com->loses_outints = COM_LOSESOUTINTS(isdp) != 0;
1532 com->no_irq = isdp->id_irq == 0;
1567 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1568 com->no_irq = isa_get_irq(dev) < 0;
1533 com->tx_fifo_size = 1;
1534 com->obufs[0].l_head = com->obuf1;
1535 com->obufs[1].l_head = com->obuf2;
1536
1537 com->iobase = iobase;
1538#ifdef PC98
1569 com->tx_fifo_size = 1;
1570 com->obufs[0].l_head = com->obuf1;
1571 com->obufs[1].l_head = com->obuf2;
1572
1573 com->iobase = iobase;
1574#ifdef PC98
1539 if (pc98_set_ioport(com, isdp->id_flags) == -1) {
1540 com->pc98_if_type = (isdp->id_flags >> 24) & 0xff;
1575 if (pc98_set_ioport(com, isa_get_flags(dev)) == -1) {
1576 com->pc98_if_type = (isa_get_flags(dev) >> 24) & 0xff;
1541 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1542 com->data_port = iobase + (com_data << port_shift);
1543 com->int_id_port = iobase + (com_iir << port_shift);
1544 com->modem_ctl_port = iobase + (com_mcr << port_shift);
1545 com->mcr_image = inb(com->modem_ctl_port);
1546 com->line_status_port = iobase + (com_lsr << port_shift);
1547 com->modem_status_port = iobase + (com_msr << port_shift);
1548 com->intr_ctl_port = iobase + (com_ier << port_shift);

--- 43 unchanged lines hidden (view full) ---

1592 com->it_out = com->it_in;
1593
1594 /* attempt to determine UART type */
1595 printf("sio%d: type", unit);
1596
1597
1598#ifndef PC98
1599#ifdef COM_MULTIPORT
1577 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift;
1578 com->data_port = iobase + (com_data << port_shift);
1579 com->int_id_port = iobase + (com_iir << port_shift);
1580 com->modem_ctl_port = iobase + (com_mcr << port_shift);
1581 com->mcr_image = inb(com->modem_ctl_port);
1582 com->line_status_port = iobase + (com_lsr << port_shift);
1583 com->modem_status_port = iobase + (com_msr << port_shift);
1584 com->intr_ctl_port = iobase + (com_ier << port_shift);

--- 43 unchanged lines hidden (view full) ---

1628 com->it_out = com->it_in;
1629
1630 /* attempt to determine UART type */
1631 printf("sio%d: type", unit);
1632
1633
1634#ifndef PC98
1635#ifdef COM_MULTIPORT
1600 if (!COM_ISMULTIPORT(isdp) && !COM_IIR_TXRDYBUG(isdp))
1636 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags))
1601#else
1637#else
1602 if (!COM_IIR_TXRDYBUG(isdp))
1638 if (!COM_IIR_TXRDYBUG(flags))
1603#endif
1604 {
1605 u_char scr;
1606 u_char scr1;
1607 u_char scr2;
1608
1609 scr = inb(iobase + com_scr);
1610 outb(iobase + com_scr, 0xa5);

--- 27 unchanged lines hidden (view full) ---

1638 break;
1639 case FIFO_RX_MEDL:
1640 printf(" 16450?");
1641 break;
1642 case FIFO_RX_MEDH:
1643 printf(" 16550?");
1644 break;
1645 case FIFO_RX_HIGH:
1639#endif
1640 {
1641 u_char scr;
1642 u_char scr1;
1643 u_char scr2;
1644
1645 scr = inb(iobase + com_scr);
1646 outb(iobase + com_scr, 0xa5);

--- 27 unchanged lines hidden (view full) ---

1674 break;
1675 case FIFO_RX_MEDL:
1676 printf(" 16450?");
1677 break;
1678 case FIFO_RX_MEDH:
1679 printf(" 16550?");
1680 break;
1681 case FIFO_RX_HIGH:
1646 if (COM_NOFIFO(isdp)) {
1682 if (COM_NOFIFO(flags)) {
1647 printf(" 16550A fifo disabled");
1648 } else {
1649 com->hasfifo = TRUE;
1650#ifdef PC98
1651 com->tx_fifo_size = 0; /* XXX flag conflicts. */
1652 printf(" 16550A");
1653#else
1683 printf(" 16550A fifo disabled");
1684 } else {
1685 com->hasfifo = TRUE;
1686#ifdef PC98
1687 com->tx_fifo_size = 0; /* XXX flag conflicts. */
1688 printf(" 16550A");
1689#else
1654 if (COM_ST16650A(isdp)) {
1690 if (COM_ST16650A(flags)) {
1655 com->st16650a = 1;
1656 com->tx_fifo_size = 32;
1657 printf(" ST16650A");
1658 } else {
1691 com->st16650a = 1;
1692 com->tx_fifo_size = 32;
1693 printf(" ST16650A");
1694 } else {
1659 com->tx_fifo_size = COM_FIFOSIZE(isdp);
1695 com->tx_fifo_size = COM_FIFOSIZE(flags);
1660 printf(" 16550A");
1661 }
1662#endif
1663 }
1664#ifdef PC98
1665 if (com->pc98_if_type == COM_IF_RSA98III) {
1666 com->tx_fifo_size = 2048;
1696 printf(" 16550A");
1697 }
1698#endif
1699 }
1700#ifdef PC98
1701 if (com->pc98_if_type == COM_IF_RSA98III) {
1702 com->tx_fifo_size = 2048;
1667 com->rsabase = isdp->id_iobase;
1703 com->rsabase = isa_get_port(dev);
1668 outb(com->rsabase + rsa_ier, 0x00);
1669 outb(com->rsabase + rsa_frr, 0x00);
1670 }
1671#endif
1672
1673#ifdef COM_ESP
1674#ifdef PC98
1675 if (com->pc98_if_type == COM_IF_ESP98)
1676#endif
1677 for (espp = likely_esp_ports; *espp != 0; espp++)
1704 outb(com->rsabase + rsa_ier, 0x00);
1705 outb(com->rsabase + rsa_frr, 0x00);
1706 }
1707#endif
1708
1709#ifdef COM_ESP
1710#ifdef PC98
1711 if (com->pc98_if_type == COM_IF_ESP98)
1712#endif
1713 for (espp = likely_esp_ports; *espp != 0; espp++)
1678 if (espattach(isdp, com, *espp)) {
1714 if (espattach(dev, com, *espp)) {
1679 com->tx_fifo_size = 1024;
1680 break;
1681 }
1682#endif
1683 if (!com->st16650a) {
1684 if (!com->tx_fifo_size)
1685 com->tx_fifo_size = 16;
1686 else

--- 69 unchanged lines hidden (view full) ---

1756 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
1757 outb(iobase + (com_fifo << port_shift), 0);
1758#else
1759 outb(iobase + com_fifo, 0);
1760determined_type: ;
1761#endif
1762
1763#ifdef COM_MULTIPORT
1715 com->tx_fifo_size = 1024;
1716 break;
1717 }
1718#endif
1719 if (!com->st16650a) {
1720 if (!com->tx_fifo_size)
1721 com->tx_fifo_size = 16;
1722 else

--- 69 unchanged lines hidden (view full) ---

1792 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
1793 outb(iobase + (com_fifo << port_shift), 0);
1794#else
1795 outb(iobase + com_fifo, 0);
1796determined_type: ;
1797#endif
1798
1799#ifdef COM_MULTIPORT
1764 if (COM_ISMULTIPORT(isdp)) {
1800 if (COM_ISMULTIPORT(flags)) {
1765 com->multiport = TRUE;
1766 printf(" (multiport");
1801 com->multiport = TRUE;
1802 printf(" (multiport");
1767 if (unit == COM_MPMASTER(isdp))
1803 if (unit == COM_MPMASTER(flags))
1768 printf(" master");
1769 printf(")");
1804 printf(" master");
1805 printf(")");
1770 idev = find_isadev(isa_devtab_tty, &siodriver,
1771 COM_MPMASTER(isdp));
1772 com->no_irq = (idev == NULL || idev->id_irq == 0);
1806 com->no_irq =
1807 isa_get_irq(devclass_get_device
1808 (sio_devclass, COM_MPMASTER(flags))) < 0;
1773 }
1774#endif /* COM_MULTIPORT */
1775#ifdef PC98
1776 }
1777#endif
1778 if (unit == comconsole)
1779 printf(", console");
1809 }
1810#endif /* COM_MULTIPORT */
1811#ifdef PC98
1812 }
1813#endif
1814 if (unit == comconsole)
1815 printf(", console");
1780 if ( COM_IIR_TXRDYBUG(isdp) )
1816 if ( COM_IIR_TXRDYBUG(flags) )
1781 printf(" with a bogus IIR_TXRDY register");
1782 printf("\n");
1783
1817 printf(" with a bogus IIR_TXRDY register");
1818 printf("\n");
1819
1784 s = spltty();
1785 com_addr(unit) = com;
1786 splx(s);
1787
1788 if (!sio_registered) {
1820 if (!sio_registered) {
1789 dev = makedev(CDEV_MAJOR, 0);
1790 cdevsw_add(&dev, &sio_cdevsw, NULL);
1791 register_swi(SWI_TTY, siopoll);
1792 sio_registered = TRUE;
1793 }
1794#ifdef DEVFS
1795 com->devfs_token_ttyd = devfs_add_devswf(&sio_cdevsw,
1796 unit, DV_CHR,
1797 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1798 com->devfs_token_ttyi = devfs_add_devswf(&sio_cdevsw,

--- 7 unchanged lines hidden (view full) ---

1806 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1807 com->devfs_token_cuai = devfs_add_devswf(&sio_cdevsw,
1808 unit | CALLOUT_MASK | CONTROL_INIT_STATE, DV_CHR,
1809 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1810 com->devfs_token_cual = devfs_add_devswf(&sio_cdevsw,
1811 unit | CALLOUT_MASK | CONTROL_LOCK_STATE, DV_CHR,
1812 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1813#endif
1821 register_swi(SWI_TTY, siopoll);
1822 sio_registered = TRUE;
1823 }
1824#ifdef DEVFS
1825 com->devfs_token_ttyd = devfs_add_devswf(&sio_cdevsw,
1826 unit, DV_CHR,
1827 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit);
1828 com->devfs_token_ttyi = devfs_add_devswf(&sio_cdevsw,

--- 7 unchanged lines hidden (view full) ---

1836 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit);
1837 com->devfs_token_cuai = devfs_add_devswf(&sio_cdevsw,
1838 unit | CALLOUT_MASK | CONTROL_INIT_STATE, DV_CHR,
1839 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit);
1840 com->devfs_token_cual = devfs_add_devswf(&sio_cdevsw,
1841 unit | CALLOUT_MASK | CONTROL_LOCK_STATE, DV_CHR,
1842 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit);
1843#endif
1814 com->id_flags = isdp->id_flags; /* Heritate id_flags for later */
1844 com->flags = isa_get_flags(dev); /* Heritate id_flags for later */
1815 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1816 pps_init(&com->pps);
1845 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1846 pps_init(&com->pps);
1817 return (1);
1847
1848 res = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 0ul, ~0ul, 1,
1849 RF_SHAREABLE | RF_ACTIVE);
1850 BUS_SETUP_INTR(device_get_parent(dev), dev, res, siointr, com,
1851 &ih);
1852
1853 return (0);
1818}
1819
1820static int
1821sioopen(dev, flag, mode, p)
1822 dev_t dev;
1823 int flag;
1824 int mode;
1825 struct proc *p;

--- 164 unchanged lines hidden (view full) ---

1990 com->pc98_prev_modem_status = pc98_get_modem_status(com);
1991 com_int_Rx_enable(com);
1992 } else {
1993#endif
1994 (void) inb(com->line_status_port);
1995 (void) inb(com->data_port);
1996 com->prev_modem_status = com->last_modem_status
1997 = inb(com->modem_status_port);
1854}
1855
1856static int
1857sioopen(dev, flag, mode, p)
1858 dev_t dev;
1859 int flag;
1860 int mode;
1861 struct proc *p;

--- 164 unchanged lines hidden (view full) ---

2026 com->pc98_prev_modem_status = pc98_get_modem_status(com);
2027 com_int_Rx_enable(com);
2028 } else {
2029#endif
2030 (void) inb(com->line_status_port);
2031 (void) inb(com->data_port);
2032 com->prev_modem_status = com->last_modem_status
2033 = inb(com->modem_status_port);
1998 if (COM_IIR_TXRDYBUG(com)) {
2034 if (COM_IIR_TXRDYBUG(com->flags)) {
1999 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
2000 | IER_EMSC);
2001 } else {
2002 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
2003 | IER_ERLS | IER_EMSC);
2004 }
2005#ifdef PC98
2006 if (com->pc98_if_type == COM_IF_RSA98III) {

--- 81 unchanged lines hidden (view full) ---

2088 siostop(tp, FREAD | FWRITE);
2089 comhardclose(com);
2090 ttyclose(tp);
2091 siosettimeout();
2092 splx(s);
2093 if (com->gone) {
2094 printf("sio%d: gone\n", com->unit);
2095 s = spltty();
2035 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS
2036 | IER_EMSC);
2037 } else {
2038 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY
2039 | IER_ERLS | IER_EMSC);
2040 }
2041#ifdef PC98
2042 if (com->pc98_if_type == COM_IF_RSA98III) {

--- 81 unchanged lines hidden (view full) ---

2124 siostop(tp, FREAD | FWRITE);
2125 comhardclose(com);
2126 ttyclose(tp);
2127 siosettimeout();
2128 splx(s);
2129 if (com->gone) {
2130 printf("sio%d: gone\n", com->unit);
2131 s = spltty();
2096 com_addr(com->unit) = NULL;
2097 if (com->ibuf != NULL)
2098 free(com->ibuf, M_DEVBUF);
2132 if (com->ibuf != NULL)
2133 free(com->ibuf, M_DEVBUF);
2099 bzero(tp, sizeof *tp);
2134 bzero(tp,sizeof *tp);
2100 free(com, M_DEVBUF);
2101 splx(s);
2102 }
2103 return (0);
2104}
2105
2106static void
2107comhardclose(com)

--- 289 unchanged lines hidden (view full) ---

2397 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2398#else
2399 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
2400 !(tp->t_state & TS_TBLOCK))
2401 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2402#endif
2403}
2404
2135 free(com, M_DEVBUF);
2136 splx(s);
2137 }
2138 return (0);
2139}
2140
2141static void
2142comhardclose(com)

--- 289 unchanged lines hidden (view full) ---

2432 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2433#else
2434 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
2435 !(tp->t_state & TS_TBLOCK))
2436 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2437#endif
2438}
2439
2405static void
2406siointr(unit)
2407 int unit;
2440void
2441siointr(arg)
2442 void *arg;
2408{
2409#ifndef COM_MULTIPORT
2410 COM_LOCK();
2443{
2444#ifndef COM_MULTIPORT
2445 COM_LOCK();
2411 siointr1(com_addr(unit));
2446 siointr1((struct com_s *) arg);
2412 COM_UNLOCK();
2413#else /* COM_MULTIPORT */
2447 COM_UNLOCK();
2448#else /* COM_MULTIPORT */
2414 struct com_s *com;
2415 bool_t possibly_more_intrs;
2416#ifdef PC98
2417 u_char rsa_buf_status;
2418#endif
2419
2420 /*
2421 * Loop until there is no activity on any port. This is necessary
2422 * to get an interrupt edge more than to avoid another interrupt.

--- 286 unchanged lines hidden (view full) ---

2709 ++com->bytes_out;
2710 }
2711#ifdef PC98
2712 if (IS_8251(com->pc98_if_type))
2713 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
2714 com_int_Tx_enable(com);
2715#endif
2716 com->obufq.l_head = ioptr;
2449 bool_t possibly_more_intrs;
2450#ifdef PC98
2451 u_char rsa_buf_status;
2452#endif
2453
2454 /*
2455 * Loop until there is no activity on any port. This is necessary
2456 * to get an interrupt edge more than to avoid another interrupt.

--- 286 unchanged lines hidden (view full) ---

2743 ++com->bytes_out;
2744 }
2745#ifdef PC98
2746 if (IS_8251(com->pc98_if_type))
2747 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
2748 com_int_Tx_enable(com);
2749#endif
2750 com->obufq.l_head = ioptr;
2717 if (COM_IIR_TXRDYBUG(com)) {
2751 if (COM_IIR_TXRDYBUG(com->flags)) {
2718 int_ctl_new = int_ctl | IER_ETXRDY;
2719 }
2720 if (ioptr >= com->obufq.l_tail) {
2721 struct lbq *qp;
2722
2723 qp = com->obufq.l_next;
2724 qp->l_queued = FALSE;
2725 qp = qp->l_next;
2726 if (qp != NULL) {
2727 com->obufq.l_head = qp->l_head;
2728 com->obufq.l_tail = qp->l_tail;
2729 com->obufq.l_next = qp;
2730 } else {
2731 /* output just completed */
2752 int_ctl_new = int_ctl | IER_ETXRDY;
2753 }
2754 if (ioptr >= com->obufq.l_tail) {
2755 struct lbq *qp;
2756
2757 qp = com->obufq.l_next;
2758 qp->l_queued = FALSE;
2759 qp = qp->l_next;
2760 if (qp != NULL) {
2761 com->obufq.l_head = qp->l_head;
2762 com->obufq.l_tail = qp->l_tail;
2763 com->obufq.l_next = qp;
2764 } else {
2765 /* output just completed */
2732 if ( COM_IIR_TXRDYBUG(com) ) {
2766 if ( COM_IIR_TXRDYBUG(com->flags) ) {
2733 int_ctl_new = int_ctl & ~IER_ETXRDY;
2734 }
2735 com->state &= ~CS_BUSY;
2736#if defined(PC98)
2737 if (IS_8251(com->pc98_if_type))
2738 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2739 com_int_Tx_disable(com);
2740#endif
2741 }
2742 if (!(com->state & CS_ODONE)) {
2743 com_events += LOTS_OF_EVENTS;
2744 com->state |= CS_ODONE;
2745 setsofttty(); /* handle at high level ASAP */
2746 }
2747 }
2767 int_ctl_new = int_ctl & ~IER_ETXRDY;
2768 }
2769 com->state &= ~CS_BUSY;
2770#if defined(PC98)
2771 if (IS_8251(com->pc98_if_type))
2772 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG )
2773 com_int_Tx_disable(com);
2774#endif
2775 }
2776 if (!(com->state & CS_ODONE)) {
2777 com_events += LOTS_OF_EVENTS;
2778 com->state |= CS_ODONE;
2779 setsofttty(); /* handle at high level ASAP */
2780 }
2781 }
2748 if ( COM_IIR_TXRDYBUG(com) && (int_ctl != int_ctl_new)) {
2782 if ( COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) {
2749#ifdef PC98
2750 if (com->pc98_if_type == COM_IF_RSA98III) {
2751 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
2752 outb(com->intr_ctl_port, int_ctl_new);
2753 outb(com->rsabase + rsa_ier, 0x1d);
2754 } else
2755#endif
2756 outb(com->intr_ctl_port, int_ctl_new);

--- 32 unchanged lines hidden (view full) ---

2789{
2790 struct com_s *com;
2791 int error;
2792 Port_t iobase;
2793 int mynor;
2794 int s;
2795 struct tty *tp;
2796#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2783#ifdef PC98
2784 if (com->pc98_if_type == COM_IF_RSA98III) {
2785 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
2786 outb(com->intr_ctl_port, int_ctl_new);
2787 outb(com->rsabase + rsa_ier, 0x1d);
2788 } else
2789#endif
2790 outb(com->intr_ctl_port, int_ctl_new);

--- 32 unchanged lines hidden (view full) ---

2823{
2824 struct com_s *com;
2825 int error;
2826 Port_t iobase;
2827 int mynor;
2828 int s;
2829 struct tty *tp;
2830#if defined(COMPAT_43) || defined(COMPAT_SUNOS)
2797 int oldcmd;
2831 u_long oldcmd;
2798 struct termios term;
2799#endif
2800
2801 mynor = minor(dev);
2802 com = com_addr(MINOR_TO_UNIT(mynor));
2803 if (com->gone)
2804 return (ENODEV);
2805 iobase = com->iobase;

--- 1061 unchanged lines hidden (view full) ---

3867 u_char dlbl;
3868 u_char dlbh;
3869 u_char ier;
3870 u_char cfcr;
3871 u_char mcr;
3872};
3873
3874static speed_t siocngetspeed __P((Port_t, struct speedtab *));
2832 struct termios term;
2833#endif
2834
2835 mynor = minor(dev);
2836 com = com_addr(MINOR_TO_UNIT(mynor));
2837 if (com->gone)
2838 return (ENODEV);
2839 iobase = com->iobase;

--- 1061 unchanged lines hidden (view full) ---

3901 u_char dlbl;
3902 u_char dlbh;
3903 u_char ier;
3904 u_char cfcr;
3905 u_char mcr;
3906};
3907
3908static speed_t siocngetspeed __P((Port_t, struct speedtab *));
3875static void siocnclose __P((struct siocnstate *sp));
3876static void siocnopen __P((struct siocnstate *sp));
3877static void siocntxwait __P((void));
3909static void siocnclose __P((struct siocnstate *sp, Port_t iobase));
3910static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed));
3911static void siocntxwait __P((Port_t iobase));
3878
3912
3913#ifdef __i386__
3879/*
3880 * XXX: sciocnget() and sciocnputc() are not declared static, as they are
3881 * referred to from i386/i386/i386-gdbstub.c.
3882 */
3883static cn_probe_t siocnprobe;
3884static cn_init_t siocninit;
3885static cn_checkc_t siocncheckc;
3886 cn_getc_t siocngetc;
3887 cn_putc_t siocnputc;
3888
3889CONS_DRIVER(sio, siocnprobe, siocninit, siocngetc, siocncheckc, siocnputc);
3890
3914/*
3915 * XXX: sciocnget() and sciocnputc() are not declared static, as they are
3916 * referred to from i386/i386/i386-gdbstub.c.
3917 */
3918static cn_probe_t siocnprobe;
3919static cn_init_t siocninit;
3920static cn_checkc_t siocncheckc;
3921 cn_getc_t siocngetc;
3922 cn_putc_t siocnputc;
3923
3924CONS_DRIVER(sio, siocnprobe, siocninit, siocngetc, siocncheckc, siocnputc);
3925
3926#endif
3927
3891static void
3928static void
3892siocntxwait()
3929siocntxwait(iobase)
3930 Port_t iobase;
3893{
3894 int timo;
3895
3896 /*
3897 * Wait for any pending transmission to finish. Required to avoid
3898 * the UART lockup bug when the speed is changed, and for normal
3899 * transmits.
3900 */
3901 timo = 100000;
3931{
3932 int timo;
3933
3934 /*
3935 * Wait for any pending transmission to finish. Required to avoid
3936 * the UART lockup bug when the speed is changed, and for normal
3937 * transmits.
3938 */
3939 timo = 100000;
3902 while ((inb(siocniobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3940 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3903 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3904 ;
3905}
3906
3907/*
3908 * Read the serial port specified and try to figure out what speed
3909 * it's currently running at. We're assuming the serial port has
3910 * been initialized and is basicly idle. This routine is only intended

--- 25 unchanged lines hidden (view full) ---

3936 for ( ; table->sp_speed != -1; table++)
3937 if (table->sp_code == code)
3938 return (table->sp_speed);
3939
3940 return 0; /* didn't match anything sane */
3941}
3942
3943static void
3941 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3942 ;
3943}
3944
3945/*
3946 * Read the serial port specified and try to figure out what speed
3947 * it's currently running at. We're assuming the serial port has
3948 * been initialized and is basicly idle. This routine is only intended

--- 25 unchanged lines hidden (view full) ---

3974 for ( ; table->sp_speed != -1; table++)
3975 if (table->sp_code == code)
3976 return (table->sp_speed);
3977
3978 return 0; /* didn't match anything sane */
3979}
3980
3981static void
3944siocnopen(sp)
3982siocnopen(sp, iobase, speed)
3945 struct siocnstate *sp;
3983 struct siocnstate *sp;
3984 Port_t iobase;
3985 int speed;
3946{
3947 int divisor;
3948 u_char dlbh;
3949 u_char dlbl;
3986{
3987 int divisor;
3988 u_char dlbh;
3989 u_char dlbl;
3950 Port_t iobase;
3951
3952 /*
3953 * Save all the device control registers except the fifo register
3954 * and set our default ones (cs8 -parenb speed=comdefaultrate).
3955 * We can't save the fifo register since it is read-only.
3956 */
3990
3991 /*
3992 * Save all the device control registers except the fifo register
3993 * and set our default ones (cs8 -parenb speed=comdefaultrate).
3994 * We can't save the fifo register since it is read-only.
3995 */
3957 iobase = siocniobase;
3958 sp->ier = inb(iobase + com_ier);
3959 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
3996 sp->ier = inb(iobase + com_ier);
3997 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
3960 siocntxwait();
3998 siocntxwait(iobase);
3961 sp->cfcr = inb(iobase + com_cfcr);
3962 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3963 sp->dlbl = inb(iobase + com_dlbl);
3964 sp->dlbh = inb(iobase + com_dlbh);
3965 /*
3966 * Only set the divisor registers if they would change, since on
3967 * some 16550 incompatibles (Startech), setting them clears the
3968 * data input register. This also reduces the effects of the
3969 * UMC8669F bug.
3970 */
3999 sp->cfcr = inb(iobase + com_cfcr);
4000 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4001 sp->dlbl = inb(iobase + com_dlbl);
4002 sp->dlbh = inb(iobase + com_dlbh);
4003 /*
4004 * Only set the divisor registers if they would change, since on
4005 * some 16550 incompatibles (Startech), setting them clears the
4006 * data input register. This also reduces the effects of the
4007 * UMC8669F bug.
4008 */
3971 divisor = ttspeedtab(comdefaultrate, comspeedtab);
4009 divisor = ttspeedtab(speed, comspeedtab);
3972 dlbl = divisor & 0xFF;
3973 if (sp->dlbl != dlbl)
3974 outb(iobase + com_dlbl, dlbl);
3975 dlbh = (u_int) divisor >> 8;
3976 if (sp->dlbh != dlbh)
3977 outb(iobase + com_dlbh, dlbh);
3978 outb(iobase + com_cfcr, CFCR_8BITS);
3979 sp->mcr = inb(iobase + com_mcr);
3980 /*
3981 * We don't want interrupts, but must be careful not to "disable"
3982 * them by clearing the MCR_IENABLE bit, since that might cause
3983 * an interrupt by floating the IRQ line.
3984 */
3985 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
3986}
3987
3988static void
4010 dlbl = divisor & 0xFF;
4011 if (sp->dlbl != dlbl)
4012 outb(iobase + com_dlbl, dlbl);
4013 dlbh = (u_int) divisor >> 8;
4014 if (sp->dlbh != dlbh)
4015 outb(iobase + com_dlbh, dlbh);
4016 outb(iobase + com_cfcr, CFCR_8BITS);
4017 sp->mcr = inb(iobase + com_mcr);
4018 /*
4019 * We don't want interrupts, but must be careful not to "disable"
4020 * them by clearing the MCR_IENABLE bit, since that might cause
4021 * an interrupt by floating the IRQ line.
4022 */
4023 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
4024}
4025
4026static void
3989siocnclose(sp)
4027siocnclose(sp, iobase)
3990 struct siocnstate *sp;
4028 struct siocnstate *sp;
4029 Port_t iobase;
3991{
4030{
3992 Port_t iobase;
3993
3994 /*
3995 * Restore the device control registers.
3996 */
4031 /*
4032 * Restore the device control registers.
4033 */
3997 siocntxwait();
3998 iobase = siocniobase;
4034 siocntxwait(iobase);
3999 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4000 if (sp->dlbl != inb(iobase + com_dlbl))
4001 outb(iobase + com_dlbl, sp->dlbl);
4002 if (sp->dlbh != inb(iobase + com_dlbh))
4003 outb(iobase + com_dlbh, sp->dlbh);
4004 outb(iobase + com_cfcr, sp->cfcr);
4005 /*
4006 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
4007 */
4008 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
4009 outb(iobase + com_ier, sp->ier);
4010}
4011
4035 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
4036 if (sp->dlbl != inb(iobase + com_dlbl))
4037 outb(iobase + com_dlbl, sp->dlbl);
4038 if (sp->dlbh != inb(iobase + com_dlbh))
4039 outb(iobase + com_dlbh, sp->dlbh);
4040 outb(iobase + com_cfcr, sp->cfcr);
4041 /*
4042 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
4043 */
4044 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
4045 outb(iobase + com_ier, sp->ier);
4046}
4047
4012static void
4048#ifdef __i386__
4049static
4050#endif
4051void
4013siocnprobe(cp)
4014 struct consdev *cp;
4015{
4016 speed_t boot_speed;
4017 u_char cfcr;
4052siocnprobe(cp)
4053 struct consdev *cp;
4054{
4055 speed_t boot_speed;
4056 u_char cfcr;
4018 struct isa_device *dvp;
4019 int s;
4057 int s, unit;
4020 struct siocnstate sp;
4021
4022 /*
4023 * Find our first enabled console, if any. If it is a high-level
4024 * console device, then initialize it and return successfully.
4025 * If it is a low-level console device, then initialize it and
4026 * return unsuccessfully. It must be initialized in both cases
4027 * for early use by console drivers and debuggers. Initializing
4028 * the hardware is not necessary in all cases, since the i/o
4029 * routines initialize it on the fly, but it is necessary if
4030 * input might arrive while the hardware is switched back to an
4031 * uninitialized state. We can't handle multiple console devices
4032 * yet because our low-level routines don't take a device arg.
4033 * We trust the user to set the console flags properly so that we
4034 * don't need to probe.
4035 */
4036 cp->cn_pri = CN_DEAD;
4058 struct siocnstate sp;
4059
4060 /*
4061 * Find our first enabled console, if any. If it is a high-level
4062 * console device, then initialize it and return successfully.
4063 * If it is a low-level console device, then initialize it and
4064 * return unsuccessfully. It must be initialized in both cases
4065 * for early use by console drivers and debuggers. Initializing
4066 * the hardware is not necessary in all cases, since the i/o
4067 * routines initialize it on the fly, but it is necessary if
4068 * input might arrive while the hardware is switched back to an
4069 * uninitialized state. We can't handle multiple console devices
4070 * yet because our low-level routines don't take a device arg.
4071 * We trust the user to set the console flags properly so that we
4072 * don't need to probe.
4073 */
4074 cp->cn_pri = CN_DEAD;
4037 for (dvp = isa_devtab_tty; dvp->id_driver != NULL; dvp++)
4038 if (dvp->id_driver == &siodriver && dvp->id_enabled
4039 && COM_CONSOLE(dvp)) {
4040 siocniobase = dvp->id_iobase;
4075
4076 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
4077 int flags;
4078 if (resource_int_value("sio", unit, "flags", &flags))
4079 continue;
4080 if (COM_CONSOLE(flags)) {
4081 int port;
4082 if (resource_int_value("sio", unit, "port", &port))
4083 continue;
4084 siocniobase = port;
4041 s = spltty();
4042 if (boothowto & RB_SERIAL) {
4043 boot_speed = siocngetspeed(siocniobase,
4044 comspeedtab);
4045 if (boot_speed)
4046 comdefaultrate = boot_speed;
4047 }
4048

--- 9 unchanged lines hidden (view full) ---

4058 cfcr = inb(siocniobase + com_cfcr);
4059 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
4060 outb(siocniobase + com_dlbl,
4061 COMBRD(comdefaultrate) & 0xff);
4062 outb(siocniobase + com_dlbh,
4063 (u_int) COMBRD(comdefaultrate) >> 8);
4064 outb(siocniobase + com_cfcr, cfcr);
4065
4085 s = spltty();
4086 if (boothowto & RB_SERIAL) {
4087 boot_speed = siocngetspeed(siocniobase,
4088 comspeedtab);
4089 if (boot_speed)
4090 comdefaultrate = boot_speed;
4091 }
4092

--- 9 unchanged lines hidden (view full) ---

4102 cfcr = inb(siocniobase + com_cfcr);
4103 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
4104 outb(siocniobase + com_dlbl,
4105 COMBRD(comdefaultrate) & 0xff);
4106 outb(siocniobase + com_dlbh,
4107 (u_int) COMBRD(comdefaultrate) >> 8);
4108 outb(siocniobase + com_cfcr, cfcr);
4109
4066 siocnopen(&sp);
4110 siocnopen(&sp, siocniobase, comdefaultrate);
4067 splx(s);
4111 splx(s);
4068 if (!COM_LLCONSOLE(dvp)) {
4069 cp->cn_dev = makedev(CDEV_MAJOR, dvp->id_unit);
4070 cp->cn_pri = COM_FORCECONSOLE(dvp)
4112 if (!COM_LLCONSOLE(flags)) {
4113 cp->cn_dev = makedev(CDEV_MAJOR, unit);
4114 cp->cn_pri = COM_FORCECONSOLE(flags)
4071 || boothowto & RB_SERIAL
4072 ? CN_REMOTE : CN_NORMAL;
4073 }
4074 break;
4075 }
4115 || boothowto & RB_SERIAL
4116 ? CN_REMOTE : CN_NORMAL;
4117 }
4118 break;
4119 }
4120 }
4076}
4077
4121}
4122
4078static void
4123#ifdef __alpha__
4124
4125struct consdev siocons = {
4126 NULL, NULL, siocngetc, siocncheckc, siocnputc,
4127 NULL, makedev(CDEV_MAJOR, 0), CN_NORMAL,
4128};
4129
4130extern struct consdev *cn_tab;
4131
4132int
4133siocnattach(port, speed)
4134 int port;
4135 int speed;
4136{
4137 int s;
4138 u_char cfcr;
4139 struct siocnstate sp;
4140
4141 siocniobase = port;
4142 comdefaultrate = speed;
4143
4144 s = spltty();
4145
4146 /*
4147 * Initialize the divisor latch. We can't rely on
4148 * siocnopen() to do this the first time, since it
4149 * avoids writing to the latch if the latch appears
4150 * to have the correct value. Also, if we didn't
4151 * just read the speed from the hardware, then we
4152 * need to set the speed in hardware so that
4153 * switching it later is null.
4154 */
4155 cfcr = inb(siocniobase + com_cfcr);
4156 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr);
4157 outb(siocniobase + com_dlbl,
4158 COMBRD(comdefaultrate) & 0xff);
4159 outb(siocniobase + com_dlbh,
4160 (u_int) COMBRD(comdefaultrate) >> 8);
4161 outb(siocniobase + com_cfcr, cfcr);
4162
4163 siocnopen(&sp, siocniobase, comdefaultrate);
4164 splx(s);
4165
4166 cn_tab = &siocons;
4167 return 0;
4168}
4169
4170int
4171siogdbattach(port, speed)
4172 int port;
4173 int speed;
4174{
4175 int s;
4176 u_char cfcr;
4177 struct siocnstate sp;
4178
4179 siogdbiobase = port;
4180 gdbdefaultrate = speed;
4181
4182 s = spltty();
4183
4184 /*
4185 * Initialize the divisor latch. We can't rely on
4186 * siocnopen() to do this the first time, since it
4187 * avoids writing to the latch if the latch appears
4188 * to have the correct value. Also, if we didn't
4189 * just read the speed from the hardware, then we
4190 * need to set the speed in hardware so that
4191 * switching it later is null.
4192 */
4193 cfcr = inb(siogdbiobase + com_cfcr);
4194 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr);
4195 outb(siogdbiobase + com_dlbl,
4196 COMBRD(gdbdefaultrate) & 0xff);
4197 outb(siogdbiobase + com_dlbh,
4198 (u_int) COMBRD(gdbdefaultrate) >> 8);
4199 outb(siogdbiobase + com_cfcr, cfcr);
4200
4201 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4202 splx(s);
4203
4204 return 0;
4205}
4206
4207#endif
4208
4209#ifdef __i386__
4210static
4211#endif
4212void
4079siocninit(cp)
4080 struct consdev *cp;
4081{
4082 comconsole = DEV_TO_UNIT(cp->cn_dev);
4083}
4084
4213siocninit(cp)
4214 struct consdev *cp;
4215{
4216 comconsole = DEV_TO_UNIT(cp->cn_dev);
4217}
4218
4085static int
4219#ifdef __i386__
4220static
4221#endif
4222int
4086siocncheckc(dev)
4087 dev_t dev;
4088{
4089 int c;
4090 Port_t iobase;
4091 int s;
4092 struct siocnstate sp;
4093
4094 iobase = siocniobase;
4095 s = spltty();
4223siocncheckc(dev)
4224 dev_t dev;
4225{
4226 int c;
4227 Port_t iobase;
4228 int s;
4229 struct siocnstate sp;
4230
4231 iobase = siocniobase;
4232 s = spltty();
4096 siocnopen(&sp);
4233 siocnopen(&sp, iobase, comdefaultrate);
4097 if (inb(iobase + com_lsr) & LSR_RXRDY)
4098 c = inb(iobase + com_data);
4099 else
4100 c = -1;
4234 if (inb(iobase + com_lsr) & LSR_RXRDY)
4235 c = inb(iobase + com_data);
4236 else
4237 c = -1;
4101 siocnclose(&sp);
4238 siocnclose(&sp, iobase);
4102 splx(s);
4103 return (c);
4104}
4105
4106
4107int
4108siocngetc(dev)
4109 dev_t dev;
4110{
4111 int c;
4112 Port_t iobase;
4113 int s;
4114 struct siocnstate sp;
4115
4116 iobase = siocniobase;
4117 s = spltty();
4239 splx(s);
4240 return (c);
4241}
4242
4243
4244int
4245siocngetc(dev)
4246 dev_t dev;
4247{
4248 int c;
4249 Port_t iobase;
4250 int s;
4251 struct siocnstate sp;
4252
4253 iobase = siocniobase;
4254 s = spltty();
4118 siocnopen(&sp);
4255 siocnopen(&sp, iobase, comdefaultrate);
4119 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4120 ;
4121 c = inb(iobase + com_data);
4256 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4257 ;
4258 c = inb(iobase + com_data);
4122 siocnclose(&sp);
4259 siocnclose(&sp, iobase);
4123 splx(s);
4124 return (c);
4125}
4126
4127void
4128siocnputc(dev, c)
4129 dev_t dev;
4130 int c;
4131{
4132 int s;
4133 struct siocnstate sp;
4134
4135 s = spltty();
4260 splx(s);
4261 return (c);
4262}
4263
4264void
4265siocnputc(dev, c)
4266 dev_t dev;
4267 int c;
4268{
4269 int s;
4270 struct siocnstate sp;
4271
4272 s = spltty();
4136 siocnopen(&sp);
4137 siocntxwait();
4273 siocnopen(&sp, siocniobase, comdefaultrate);
4274 siocntxwait(siocniobase);
4138 outb(siocniobase + com_data, c);
4275 outb(siocniobase + com_data, c);
4139 siocnclose(&sp);
4276 siocnclose(&sp, siocniobase);
4140 splx(s);
4141}
4142
4277 splx(s);
4278}
4279
4280int
4281siogdbgetc()
4282{
4283 int c;
4284 Port_t iobase;
4285 int s;
4286 struct siocnstate sp;
4143
4287
4288 iobase = siogdbiobase;
4289 s = spltty();
4290 siocnopen(&sp, iobase, gdbdefaultrate);
4291 while (!(inb(iobase + com_lsr) & LSR_RXRDY))
4292 ;
4293 c = inb(iobase + com_data);
4294 siocnclose(&sp, iobase);
4295 splx(s);
4296 return (c);
4297}
4298
4299void
4300siogdbputc(c)
4301 int c;
4302{
4303 int s;
4304 struct siocnstate sp;
4305
4306 s = spltty();
4307 siocnopen(&sp, siogdbiobase, gdbdefaultrate);
4308 siocntxwait(siogdbiobase);
4309 outb(siogdbiobase + com_data, c);
4310 siocnclose(&sp, siogdbiobase);
4311 splx(s);
4312}
4313
4314
4144/*
4145 * support PnP cards if we are using 'em
4146 */
4147
4148#if NPNP > 0
4149
4150static pnpid_t siopnp_ids[] = {
4151 { 0x5015f435, "MOT1550"},

--- 47 unchanged lines hidden (view full) ---

4199
4200 return (s);
4201}
4202
4203static void
4204siopnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev)
4205{
4206 struct pnp_cinfo d;
4315/*
4316 * support PnP cards if we are using 'em
4317 */
4318
4319#if NPNP > 0
4320
4321static pnpid_t siopnp_ids[] = {
4322 { 0x5015f435, "MOT1550"},

--- 47 unchanged lines hidden (view full) ---

4370
4371 return (s);
4372}
4373
4374static void
4375siopnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev)
4376{
4377 struct pnp_cinfo d;
4207 struct isa_device *dvp;
4208
4209 if (dev->id_unit >= NSIOTOT)
4210 return;
4211
4212 if (read_pnp_parms(&d, 0) == 0) {
4213 printf("failed to read pnp parms\n");
4214 return;
4215 }

--- 5 unchanged lines hidden (view full) ---

4221 dev->id_iobase = d.port[0];
4222 dev->id_irq = (1 << d.irq[0]);
4223 dev->id_ointr = siointr;
4224 dev->id_ri_flags = RI_FAST;
4225 dev->id_drq = -1;
4226
4227 if (dev->id_driver == NULL) {
4228 dev->id_driver = &siodriver;
4378
4379 if (dev->id_unit >= NSIOTOT)
4380 return;
4381
4382 if (read_pnp_parms(&d, 0) == 0) {
4383 printf("failed to read pnp parms\n");
4384 return;
4385 }

--- 5 unchanged lines hidden (view full) ---

4391 dev->id_iobase = d.port[0];
4392 dev->id_irq = (1 << d.irq[0]);
4393 dev->id_ointr = siointr;
4394 dev->id_ri_flags = RI_FAST;
4395 dev->id_drq = -1;
4396
4397 if (dev->id_driver == NULL) {
4398 dev->id_driver = &siodriver;
4229 dvp = find_isadev(isa_devtab_tty, &siodriver, 0);
4230 if (dvp != NULL)
4231 dev->id_id = dvp->id_id;
4399 dev->id_id = isa_compat_nextid();
4232 }
4233
4234 if ((dev->id_alive = sioprobe(dev)) != 0)
4235 sioattach(dev);
4236 else
4237 printf("sio%d: probe failed\n", dev->id_unit);
4238}
4239#endif
4240
4400 }
4401
4402 if ((dev->id_alive = sioprobe(dev)) != 0)
4403 sioattach(dev);
4404 else
4405 printf("sio%d: probe failed\n", dev->id_unit);
4406}
4407#endif
4408
4409CDEV_DRIVER_MODULE(sio, isa, sio_driver, sio_devclass,
4410 CDEV_MAJOR, sio_cdevsw, 0, 0);
4411
4241#ifdef PC98
4242/*
4243 * pc98 local function
4244 */
4245
4246static void
4247com_tiocm_set(struct com_s *com, int msr)
4248{

--- 444 unchanged lines hidden (view full) ---

4693 */
4694 outb(io | PC98SIO_func_port(if_type),
4695 (count & 0x20000) ? 0xf0 : 0xf2);
4696#endif
4697 break;
4698 }
4699}
4700static int
4412#ifdef PC98
4413/*
4414 * pc98 local function
4415 */
4416
4417static void
4418com_tiocm_set(struct com_s *com, int msr)
4419{

--- 444 unchanged lines hidden (view full) ---

4864 */
4865 outb(io | PC98SIO_func_port(if_type),
4866 (count & 0x20000) ? 0xf0 : 0xf2);
4867#endif
4868 break;
4869 }
4870}
4871static int
4701pc98_check_if_type(struct isa_device *dev, struct siodev *iod)
4872pc98_check_if_type(device_t dev, struct siodev *iod)
4702{
4703 int irr, io, if_type, tmp;
4704 static short irq_tab[2][8] = {
4705 { 3, 5, 6, 9, 10, 12, 13, -1},
4706 { 3, 10, 12, 13, 5, 6, 9, -1}
4707 };
4708
4873{
4874 int irr, io, if_type, tmp;
4875 static short irq_tab[2][8] = {
4876 { 3, 5, 6, 9, 10, 12, 13, -1},
4877 { 3, 10, 12, 13, 5, 6, 9, -1}
4878 };
4879
4709 iod->if_type = if_type = (dev->id_flags >> 24) & 0xff;
4880 iod->if_type = if_type = (isa_get_flags(dev) >> 24) & 0xff;
4710 if ((if_type < 0 || if_type > COM_IF_END1) &&
4711 (if_type < 0x10 || if_type > COM_IF_END2))
4712 return(-1);
4713 if_type &= 0x0f;
4714 iod->irq = 0;
4881 if ((if_type < 0 || if_type > COM_IF_END1) &&
4882 (if_type < 0x10 || if_type > COM_IF_END2))
4883 return(-1);
4884 if_type &= 0x0f;
4885 iod->irq = 0;
4715 io = dev->id_iobase & 0xff00;
4886 io = isa_get_port(dev) & 0xff00;
4716
4717 if (IS_8251(iod->if_type)) {
4718 if (PC98SIO_func_port(if_type) != -1) {
4719 outb(io | PC98SIO_func_port(if_type), 0xf2);
4720 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
4721 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
4722 outb(io | PC98SIO_baud_rate_port(if_type), tmp);
4723 }

--- 15 unchanged lines hidden (view full) ---

4739 if_8251_type[if_type].name = " (internal fast)";
4740 if_8251_type[if_type].speedtab = pc98fast_speedtab;
4741 break;
4742 }
4743 DELAY(1);
4744 }
4745 } else {
4746 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
4887
4888 if (IS_8251(iod->if_type)) {
4889 if (PC98SIO_func_port(if_type) != -1) {
4890 outb(io | PC98SIO_func_port(if_type), 0xf2);
4891 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
4892 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
4893 outb(io | PC98SIO_baud_rate_port(if_type), tmp);
4894 }

--- 15 unchanged lines hidden (view full) ---

4910 if_8251_type[if_type].name = " (internal fast)";
4911 if_8251_type[if_type].speedtab = pc98fast_speedtab;
4912 break;
4913 }
4914 DELAY(1);
4915 }
4916 } else {
4917 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
4747 if ((dev->id_iobase & 0xff) == IO_COM2)
4918 if ((isa_get_port(dev) & 0xff) == IO_COM2)
4748 iod->irq = irq_tab[0][tmp];
4749 else
4750 iod->irq = irq_tab[1][tmp];
4751 }
4752 } else {
4753 irr = if_16550a_type[if_type].irr_read;
4754#ifdef COM_MULTIPORT
4755 if (!COM_ISMULTIPORT(dev) || dev->id_unit == COM_MPMASTER(dev))
4756#endif
4757 if (irr != -1) {
4758 tmp = inb(io | irr);
4919 iod->irq = irq_tab[0][tmp];
4920 else
4921 iod->irq = irq_tab[1][tmp];
4922 }
4923 } else {
4924 irr = if_16550a_type[if_type].irr_read;
4925#ifdef COM_MULTIPORT
4926 if (!COM_ISMULTIPORT(dev) || dev->id_unit == COM_MPMASTER(dev))
4927#endif
4928 if (irr != -1) {
4929 tmp = inb(io | irr);
4759 if (dev->id_iobase & 0x01) /* XXX depend on RSB-384 */
4930 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */
4760 iod->irq = irq_tab[1][tmp >> 3];
4761 else
4762 iod->irq = irq_tab[0][tmp & 0x07];
4763 }
4764 }
4765 if ( iod->irq == -1 ) return -1;
4766
4767 return 0;

--- 23 unchanged lines hidden --- 		4931 iod->irq = irq_tab[1][tmp >> 3];
4932 else
4933 iod->irq = irq_tab[0][tmp & 0x07];
4934 }
4935 }
4936 if ( iod->irq == -1 ) return -1;
4937
4938 return 0;

--- 23 unchanged lines hidden ---