| sff8472.h (258692) | sff8472.h (265587) |
|---|---|
| 1/*- 2 * Copyright (c) 2013 George V. Neville-Neil 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2013 George V. Neville-Neil 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/net/sff8472.h 258692 2013-11-27 20:20:02Z gnn $ | 26 * $FreeBSD: stable/9/sys/net/sff8472.h 265587 2014-05-07 19:05:14Z np $ |
| 27 */ 28 29/* 30 * The following set of constants are from Document SFF-8472 31 * "Diagnostic Monitoring Interface for Optical Transceivers" revision 32 * 11.3 published by the SFF Committee on June 11, 2013 33 * 34 * The SFF standard defines two ranges of addresses, each 255 bytes --- 22 unchanged lines hidden (view full) --- 57 * device wishing to read these addresses must first have support for 58 * i2c calls. The Chelsio T4/T5 driver (dev/cxgbe) is one such 59 * driver. 60 */ 61 62 63/* Table 3.1 Two-wire interface ID: Data Fields */ 64 | 27 */ 28 29/* 30 * The following set of constants are from Document SFF-8472 31 * "Diagnostic Monitoring Interface for Optical Transceivers" revision 32 * 11.3 published by the SFF Committee on June 11, 2013 33 * 34 * The SFF standard defines two ranges of addresses, each 255 bytes --- 22 unchanged lines hidden (view full) --- 57 * device wishing to read these addresses must first have support for 58 * i2c calls. The Chelsio T4/T5 driver (dev/cxgbe) is one such 59 * driver. 60 */ 61 62 63/* Table 3.1 Two-wire interface ID: Data Fields */ 64 |
| 65#define SFF_8472_BASE 0xa0 /* Base address for all our queries. */ 66#define SFF_8472_ID 0 /* Transceiver Type (Table 3.2) */ 67#define SFF_8472_EXT_ID 1 /* Extended transceiver type (Table 3.3) */ 68#define SFF_8472_CONNECTOR 2 /* Connector type (Table 3.4) */ 69#define SFF_8472_TRANS_START 3 /* Elec or Optical Compatibility | 65enum { 66 SFF_8472_BASE = 0xa0, /* Base address for all our queries. */ 67 SFF_8472_ID = 0, /* Transceiver Type (Table 3.2) */ 68 SFF_8472_EXT_ID = 1, /* Extended transceiver type (Table 3.3) */ 69 SFF_8472_CONNECTOR = 2, /* Connector type (Table 3.4) */ 70 SFF_8472_TRANS_START = 3, /* Elec or Optical Compatibility |
| 70 * (Table 3.5) */ | 71 * (Table 3.5) */ |
| 71#define SFF_8472_TRANS_END 10 72#define SFF_8472_ENCODING 11 /* Encoding Code for high speed 73 * serial encoding algorithm (see 74 * Table 3.6) */ 75#define SFF_8472_BITRATE 12 /* Nominal signaling rate, units 76 * of 100MBd. (see details for 77 * rates > 25.0Gb/s) */ 78#define SFF_8472_RATEID 13 /* Type of rate select 79 * functionality (see Table 80 * 3.6a) */ 81#define SFF_8472_LEN_SMF_KM 14 /* Link length supported for single | 72 SFF_8472_TRANS_END = 10, 73 SFF_8472_ENCODING = 11, /* Encoding Code for high speed 74 * serial encoding algorithm (see 75 * Table 3.6) */ 76 SFF_8472_BITRATE = 12, /* Nominal signaling rate, units 77 * of 100MBd. (see details for 78 * rates > 25.0Gb/s) */ 79 SFF_8472_RATEID = 13, /* Type of rate select 80 * functionality (see Table 81 * 3.6a) */ 82 SFF_8472_LEN_SMF_KM = 14, /* Link length supported for single |
| 82 * mode fiber, units of km */ | 83 * mode fiber, units of km */ |
| 83#define SFF_8472_LEN_SMF 15 /* Link length supported for single | 84 SFF_8472_LEN_SMF = 15, /* Link length supported for single |
| 84 * mode fiber, units of 100 m */ | 85 * mode fiber, units of 100 m */ |
| 85#define SFF_8472_LEN_50UM 16 /* Link length supported for 50 um | 86 SFF_8472_LEN_50UM = 16, /* Link length supported for 50 um |
| 86 * OM2 fiber, units of 10 m */ | 87 * OM2 fiber, units of 10 m */ |
| 87#define SFF_8472_LEN_625UM 17 /* Link length supported for 62.5 | 88 SFF_8472_LEN_625UM = 17, /* Link length supported for 62.5 |
| 88 * um OM1 fiber, units of 10 m */ | 89 * um OM1 fiber, units of 10 m */ |
| 89#define SFF_8472_LEN_OM4 18 /* Link length supported for 50um | 90 SFF_8472_LEN_OM4 = 18, /* Link length supported for 50um |
| 90 * OM4 fiber, units of 10m. 91 * Alternatively copper or direct 92 * attach cable, units of m */ | 91 * OM4 fiber, units of 10m. 92 * Alternatively copper or direct 93 * attach cable, units of m */ |
| 93#define SFF_8472_LEN_OM3 19 /* Link length supported for 50 um OM3 fiber, units of 10 m */ 94#define SFF_8472_VENDOR_START 20 /* Vendor name [Address A0h, Bytes | 94 SFF_8472_LEN_OM3 = 19, /* Link length supported for 50 um OM3 fiber, units of 10 m */ 95 SFF_8472_VENDOR_START = 20, /* Vendor name [Address A0h, Bytes |
| 95 * 20-35] */ | 96 * 20-35] */ |
| 96#define SFF_8472_VENDOR_END 35 97#define SFF_8472_TRANS 36 /* Transceiver Code for electronic | 97 SFF_8472_VENDOR_END = 35, 98 SFF_8472_TRANS = 36, /* Transceiver Code for electronic |
| 98 * or optical compatibility (see 99 * Table 3.5) */ | 99 * or optical compatibility (see 100 * Table 3.5) */ |
| 100#define SFF_8472_VENDOR_OUI_START 37 /* Vendor OUI SFP vendor IEEE | 101 SFF_8472_VENDOR_OUI_START = 37, /* Vendor OUI SFP vendor IEEE |
| 101 * company ID */ | 102 * company ID */ |
| 102#define SFF_8472_VENDOR_OUI_END 39 103#define SFF_8472_PN_START 40 /* Vendor PN */ 104#define SFF_8472_PN_END 55 105#define SFF_8472_REV_START 56 /* Vendor Revision */ 106#define SFF_8472_REV_END 59 107#define SFF_8472_WAVELEN_START 60 /* Wavelength Laser wavelength | 103 SFF_8472_VENDOR_OUI_END = 39, 104 SFF_8472_PN_START = 40, /* Vendor PN */ 105 SFF_8472_PN_END = 55, 106 SFF_8472_REV_START = 56, /* Vendor Revision */ 107 SFF_8472_REV_END = 59, 108 SFF_8472_WAVELEN_START = 60, /* Wavelength Laser wavelength |
| 108 * (Passive/Active Cable 109 * Specification Compliance) */ | 109 * (Passive/Active Cable 110 * Specification Compliance) */ |
| 110#define SFF_8472_WAVELEN_END 61 111#define SFF_8472_CC_BASE 63 /* CC_BASE Check code for Base ID | 111 SFF_8472_WAVELEN_END = 61, 112 SFF_8472_CC_BASE = 63, /* CC_BASE Check code for Base ID |
| 112 * Fields (addresses 0 to 62) */ 113 114/* 115 * Extension Fields (optional) check the options before reading other 116 * addresses. 117 */ | 113 * Fields (addresses 0 to 62) */ 114 115/* 116 * Extension Fields (optional) check the options before reading other 117 * addresses. 118 */ |
| 118#define SFF_8472_OPTIONS_MSB 64 /* Options Indicates which optional | 119 SFF_8472_OPTIONS_MSB = 64, /* Options Indicates which optional |
| 119 * transceiver signals are 120 * implemented */ | 120 * transceiver signals are 121 * implemented */ |
| 121#define SFF_8472_OPTIONS_LSB 65 /* (see Table 3.7) */ 122#define SFF_8472_BR_MAX 66 /* BR max Upper bit rate margin, | 122 SFF_8472_OPTIONS_LSB = 65, /* (see Table 3.7) */ 123 SFF_8472_BR_MAX = 66, /* BR max Upper bit rate margin, |
| 123 * units of % (see details for 124 * rates > 25.0Gb/s) */ | 124 * units of % (see details for 125 * rates > 25.0Gb/s) */ |
| 125#define SFF_8472_BR_MIN 67 /* Lower bit rate margin, units of | 126 SFF_8472_BR_MIN = 67, /* Lower bit rate margin, units of |
| 126 * % (see details for rates > 127 * 25.0Gb/s) */ | 127 * % (see details for rates > 128 * 25.0Gb/s) */ |
| 128#define SFF_8472_SN_START 68 /* Vendor SN [Address A0h, Bytes 68-83] */ 129#define SFF_8472_SN_END 83 130#define SFF_8472_DATE_START 84 /* Date code Vendor���s manufacturing | 129 SFF_8472_SN_START = 68, /* Vendor SN [Address A0h, Bytes 68-83] */ 130 SFF_8472_SN_END = 83, 131 SFF_8472_DATE_START = 84, /* Date code Vendor���s manufacturing |
| 131 * date code (see Table 3.8) */ | 132 * date code (see Table 3.8) */ |
| 132#define SFF_8472_DATE_END 91 133#define SFF_8472_DIAG_TYPE 92 /* Diagnostic Monitoring Type | 133 SFF_8472_DATE_END = 91, 134 SFF_8472_DIAG_TYPE = 92, /* Diagnostic Monitoring Type |
| 134 * Indicates which type of 135 * diagnostic monitoring is 136 * implemented (if any) in the 137 * transceiver (see Table 3.9) 138 */ | 135 * Indicates which type of 136 * diagnostic monitoring is 137 * implemented (if any) in the 138 * transceiver (see Table 3.9) 139 */ |
| 139#define SFF_8472_DIAG_IMPL (1 << 6) /* Required to be 1 */ 140#define SFF_8472_DIAG_INTERNAL (1 << 5) /* Internal measurements. */ 141#define SFF_8472_DIAG_EXTERNAL (1 << 4) /* External measurements. */ 142#define SFF_8472_DIAG_POWER (1 << 3) /* Power measurement type */ 143#define SFF_8472_DIAG_ADDR_CHG (1 << 2) /* Address change required. 144 * See SFF-8472 doc. */ | |
| 145 | 140 |
| 146#define SFF_8472_ENHANCED 93 /* Enhanced Options Indicates which | 141 SFF_8472_ENHANCED = 93, /* Enhanced Options Indicates which |
| 147 * optional enhanced features are 148 * implemented (if any) in the 149 * transceiver (see Table 3.10) */ | 142 * optional enhanced features are 143 * implemented (if any) in the 144 * transceiver (see Table 3.10) */ |
| 150#define SFF_8472_COMPLIANCE 94 /* SFF-8472 Compliance Indicates | 145 SFF_8472_COMPLIANCE = 94, /* SFF-8472 Compliance Indicates |
| 151 * which revision of SFF-8472 the 152 * transceiver complies with. (see 153 * Table 3.12)*/ | 146 * which revision of SFF-8472 the 147 * transceiver complies with. (see 148 * Table 3.12)*/ |
| 154#define SFF_8472_CC_EXT 95 /* Check code for the Extended ID | 149 SFF_8472_CC_EXT = 95, /* Check code for the Extended ID |
| 155 * Fields (addresses 64 to 94) 156 */ 157 | 150 * Fields (addresses 64 to 94) 151 */ 152 |
| 158#define SFF_8472_VENDOR_RSRVD_START 96 159#define SFF_8472_VENDOR_RSRVD_END 127 | 153 SFF_8472_VENDOR_RSRVD_START = 96, 154 SFF_8472_VENDOR_RSRVD_END = 127, |
| 160 | 155 |
| 161#define SFF_8472_RESERVED_START 128 162#define SFF_8472_RESERVED_END 255 | 156 SFF_8472_RESERVED_START = 128, 157 SFF_8472_RESERVED_END = 255 158}; |
| 163 | 159 |
| 160#define SFF_8472_DIAG_IMPL (1 << 6) /* Required to be 1 */ 161#define SFF_8472_DIAG_INTERNAL (1 << 5) /* Internal measurements. */ 162#define SFF_8472_DIAG_EXTERNAL (1 << 4) /* External measurements. */ 163#define SFF_8472_DIAG_POWER (1 << 3) /* Power measurement type */ 164#define SFF_8472_DIAG_ADDR_CHG (1 << 2) /* Address change required. 165 * See SFF-8472 doc. */ 166 |
|
| 164 /* 165 * Diagnostics are available at the two wire address 0xa2. All 166 * diagnostics are OPTIONAL so you should check 0xa0 registers 92 to 167 * see which, if any are supported. 168 */ 169 | 167 /* 168 * Diagnostics are available at the two wire address 0xa2. All 169 * diagnostics are OPTIONAL so you should check 0xa0 registers 92 to 170 * see which, if any are supported. 171 */ 172 |
| 170#define SFF_8472_DIAG 0xa2 /* Base address for diagnostics. */ | 173enum {SFF_8472_DIAG = 0xa2}; /* Base address for diagnostics. */ |
| 171 172 /* 173 * Table 3.15 Alarm and Warning Thresholds All values are 2 bytes 174 * and MUST be read in a single read operation starting at the MSB 175 */ 176 | 174 175 /* 176 * Table 3.15 Alarm and Warning Thresholds All values are 2 bytes 177 * and MUST be read in a single read operation starting at the MSB 178 */ 179 |
| 177#define SFF_8472_TEMP_HIGH_ALM 0 /* Temp High Alarm */ 178#define SFF_8472_TEMP_LOW_ALM 2 /* Temp Low Alarm */ 179#define SFF_8472_TEMP_HIGH_WARN 4 /* Temp High Warning */ 180#define SFF_8472_TEMP_LOW_WARN 6 /* Temp Low Warning */ 181#define SFF_8472_VOLTAGE_HIGH_ALM 8 /* Voltage High Alarm */ 182#define SFF_8472_VOLTAGE_LOW_ALM 10 /* Voltage Low Alarm */ 183#define SFF_8472_VOLTAGE_HIGH_WARN 12 /* Voltage High Warning */ 184#define SFF_8472_VOLTAGE_LOW_WARN 14 /* Voltage Low Warning */ 185#define SFF_8472_BIAS_HIGH_ALM 16 /* Bias High Alarm */ 186#define SFF_8472_BIAS_LOW_ALM 18 /* Bias Low Alarm */ 187#define SFF_8472_BIAS_HIGH_WARN 20 /* Bias High Warning */ 188#define SFF_8472_BIAS_LOW_WARN 22 /* Bias Low Warning */ 189#define SFF_8472_TX_POWER_HIGH_ALM 24 /* TX Power High Alarm */ 190#define SFF_8472_TX_POWER_LOW_ALM 26 /* TX Power Low Alarm */ 191#define SFF_8472_TX_POWER_HIGH_WARN 28 /* TX Power High Warning */ 192#define SFF_8472_TX_POWER_LOW_WARN 30 /* TX Power Low Warning */ 193#define SFF_8472_RX_POWER_HIGH_ALM 32 /* RX Power High Alarm */ 194#define SFF_8472_RX_POWER_LOW_ALM 34 /* RX Power Low Alarm */ 195#define SFF_8472_RX_POWER_HIGH_WARN 36 /* RX Power High Warning */ 196#define SFF_8472_RX_POWER_LOW_WARN 38 /* RX Power Low Warning */ | 180enum { 181 SFF_8472_TEMP_HIGH_ALM = 0, /* Temp High Alarm */ 182 SFF_8472_TEMP_LOW_ALM = 2, /* Temp Low Alarm */ 183 SFF_8472_TEMP_HIGH_WARN = 4, /* Temp High Warning */ 184 SFF_8472_TEMP_LOW_WARN = 6, /* Temp Low Warning */ 185 SFF_8472_VOLTAGE_HIGH_ALM = 8, /* Voltage High Alarm */ 186 SFF_8472_VOLTAGE_LOW_ALM = 10, /* Voltage Low Alarm */ 187 SFF_8472_VOLTAGE_HIGH_WARN = 12, /* Voltage High Warning */ 188 SFF_8472_VOLTAGE_LOW_WARN = 14, /* Voltage Low Warning */ 189 SFF_8472_BIAS_HIGH_ALM = 16, /* Bias High Alarm */ 190 SFF_8472_BIAS_LOW_ALM = 18, /* Bias Low Alarm */ 191 SFF_8472_BIAS_HIGH_WARN = 20, /* Bias High Warning */ 192 SFF_8472_BIAS_LOW_WARN = 22, /* Bias Low Warning */ 193 SFF_8472_TX_POWER_HIGH_ALM = 24, /* TX Power High Alarm */ 194 SFF_8472_TX_POWER_LOW_ALM = 26, /* TX Power Low Alarm */ 195 SFF_8472_TX_POWER_HIGH_WARN = 28, /* TX Power High Warning */ 196 SFF_8472_TX_POWER_LOW_WARN = 30, /* TX Power Low Warning */ 197 SFF_8472_RX_POWER_HIGH_ALM = 32, /* RX Power High Alarm */ 198 SFF_8472_RX_POWER_LOW_ALM = 34, /* RX Power Low Alarm */ 199 SFF_8472_RX_POWER_HIGH_WARN = 36, /* RX Power High Warning */ 200 SFF_8472_RX_POWER_LOW_WARN = 38, /* RX Power Low Warning */ |
| 197 | 201 |
| 198#define SFF_8472_RX_POWER4 56 /* Rx_PWR(4) Single precision | 202 SFF_8472_RX_POWER4 = 56, /* Rx_PWR(4) Single precision |
| 199 * floating point calibration data 200 * - Rx optical power. Bit 7 of 201 * byte 56 is MSB. Bit 0 of byte 202 * 59 is LSB. Rx_PWR(4) should be 203 * set to zero for ���internally 204 * calibrated��� devices. */ | 203 * floating point calibration data 204 * - Rx optical power. Bit 7 of 205 * byte 56 is MSB. Bit 0 of byte 206 * 59 is LSB. Rx_PWR(4) should be 207 * set to zero for ���internally 208 * calibrated��� devices. */ |
| 205#define SFF_8472_RX_POWER3 60 /* Rx_PWR(3) Single precision | 209 SFF_8472_RX_POWER3 = 60, /* Rx_PWR(3) Single precision |
| 206 * floating point calibration data 207 * - Rx optical power. Bit 7 of 208 * byte 60 is MSB. Bit 0 of byte 63 209 * is LSB. Rx_PWR(3) should be set 210 * to zero for ���internally 211 * calibrated��� devices.*/ | 210 * floating point calibration data 211 * - Rx optical power. Bit 7 of 212 * byte 60 is MSB. Bit 0 of byte 63 213 * is LSB. Rx_PWR(3) should be set 214 * to zero for ���internally 215 * calibrated��� devices.*/ |
| 212#define SFF_8472_RX_POWER2 64 /* Rx_PWR(2) Single precision | 216 SFF_8472_RX_POWER2 = 64, /* Rx_PWR(2) Single precision |
| 213 * floating point calibration data, 214 * Rx optical power. Bit 7 of byte 215 * 64 is MSB, bit 0 of byte 67 is 216 * LSB. Rx_PWR(2) should be set to 217 * zero for ���internally calibrated��� 218 * devices. */ | 217 * floating point calibration data, 218 * Rx optical power. Bit 7 of byte 219 * 64 is MSB, bit 0 of byte 67 is 220 * LSB. Rx_PWR(2) should be set to 221 * zero for ���internally calibrated��� 222 * devices. */ |
| 219#define SFF_8472_RX_POWER1 68 /* Rx_PWR(1) Single precision | 223 SFF_8472_RX_POWER1 = 68, /* Rx_PWR(1) Single precision |
| 220 * floating point calibration data, 221 * Rx optical power. Bit 7 of byte 222 * 68 is MSB, bit 0 of byte 71 is 223 * LSB. Rx_PWR(1) should be set to 224 * 1 for ���internally calibrated��� 225 * devices. */ | 224 * floating point calibration data, 225 * Rx optical power. Bit 7 of byte 226 * 68 is MSB, bit 0 of byte 71 is 227 * LSB. Rx_PWR(1) should be set to 228 * 1 for ���internally calibrated��� 229 * devices. */ |
| 226#define SFF_8472_RX_POWER0 72 /* Rx_PWR(0) Single precision | 230 SFF_8472_RX_POWER0 = 72, /* Rx_PWR(0) Single precision |
| 227 * floating point calibration data, 228 * Rx optical power. Bit 7 of byte 229 * 72 is MSB, bit 0 of byte 75 is 230 * LSB. Rx_PWR(0) should be set to 231 * zero for ���internally calibrated��� 232 * devices. */ | 231 * floating point calibration data, 232 * Rx optical power. Bit 7 of byte 233 * 72 is MSB, bit 0 of byte 75 is 234 * LSB. Rx_PWR(0) should be set to 235 * zero for ���internally calibrated��� 236 * devices. */ |
| 233#define SFF_8472_TX_I_SLOPE 76 /* Tx_I(Slope) Fixed decimal | 237 SFF_8472_TX_I_SLOPE = 76, /* Tx_I(Slope) Fixed decimal |
| 234 * (unsigned) calibration data, 235 * laser bias current. Bit 7 of 236 * byte 76 is MSB, bit 0 of byte 77 237 * is LSB. Tx_I(Slope) should be 238 * set to 1 for ���internally 239 * calibrated��� devices. */ | 238 * (unsigned) calibration data, 239 * laser bias current. Bit 7 of 240 * byte 76 is MSB, bit 0 of byte 77 241 * is LSB. Tx_I(Slope) should be 242 * set to 1 for ���internally 243 * calibrated��� devices. */ |
| 240#define SFF_8472_TX_I_OFFSET 78 /* Tx_I(Offset) Fixed decimal | 244 SFF_8472_TX_I_OFFSET = 78, /* Tx_I(Offset) Fixed decimal |
| 241 * (signed two���s complement) 242 * calibration data, laser bias 243 * current. Bit 7 of byte 78 is 244 * MSB, bit 0 of byte 79 is 245 * LSB. Tx_I(Offset) should be set 246 * to zero for ���internally 247 * calibrated��� devices. */ | 245 * (signed two���s complement) 246 * calibration data, laser bias 247 * current. Bit 7 of byte 78 is 248 * MSB, bit 0 of byte 79 is 249 * LSB. Tx_I(Offset) should be set 250 * to zero for ���internally 251 * calibrated��� devices. */ |
| 248#define SFF_8472_TX_POWER_SLOPE 80 /* Tx_PWR(Slope) Fixed decimal | 252 SFF_8472_TX_POWER_SLOPE = 80, /* Tx_PWR(Slope) Fixed decimal |
| 249 * (unsigned) calibration data, 250 * transmitter coupled output 251 * power. Bit 7 of byte 80 is MSB, 252 * bit 0 of byte 81 is LSB. 253 * Tx_PWR(Slope) should be set to 1 254 * for ���internally calibrated��� 255 * devices. */ | 253 * (unsigned) calibration data, 254 * transmitter coupled output 255 * power. Bit 7 of byte 80 is MSB, 256 * bit 0 of byte 81 is LSB. 257 * Tx_PWR(Slope) should be set to 1 258 * for ���internally calibrated��� 259 * devices. */ |
| 256#define SFF_8472_TX_POWER_OFFSET 82 /* Tx_PWR(Offset) Fixed decimal 257 * (signed two���s complement) 258 * calibration data, transmitter 259 * coupled output power. Bit 7 of 260 * byte 82 is MSB, bit 0 of byte 83 261 * is LSB. Tx_PWR(Offset) should be 262 * set to zero for ���internally 263 * calibrated��� devices. */ 264#define SFF_8472_T_SLOPE 84 /* T (Slope) Fixed decimal | 260 SFF_8472_TX_POWER_OFFSET = 82, /* Tx_PWR(Offset) Fixed decimal 261 * (signed two���s complement) 262 * calibration data, transmitter 263 * coupled output power. Bit 7 of 264 * byte 82 is MSB, bit 0 of byte 83 265 * is LSB. Tx_PWR(Offset) should be 266 * set to zero for ���internally 267 * calibrated��� devices. */ 268 SFF_8472_T_SLOPE = 84, /* T (Slope) Fixed decimal |
| 265 * (unsigned) calibration data, 266 * internal module temperature. Bit 267 * 7 of byte 84 is MSB, bit 0 of 268 * byte 85 is LSB. T(Slope) should 269 * be set to 1 for ���internally 270 * calibrated��� devices. */ | 269 * (unsigned) calibration data, 270 * internal module temperature. Bit 271 * 7 of byte 84 is MSB, bit 0 of 272 * byte 85 is LSB. T(Slope) should 273 * be set to 1 for ���internally 274 * calibrated��� devices. */ |
| 271#define SFF_8472_T_OFFSET 86 /* T (Offset) Fixed decimal (signed | 275 SFF_8472_T_OFFSET = 86, /* T (Offset) Fixed decimal (signed |
| 272 * two���s complement) calibration 273 * data, internal module 274 * temperature. Bit 7 of byte 86 is 275 * MSB, bit 0 of byte 87 is LSB. 276 * T(Offset) should be set to zero 277 * for ���internally calibrated��� 278 * devices. */ | 276 * two���s complement) calibration 277 * data, internal module 278 * temperature. Bit 7 of byte 86 is 279 * MSB, bit 0 of byte 87 is LSB. 280 * T(Offset) should be set to zero 281 * for ���internally calibrated��� 282 * devices. */ |
| 279#define SFF_8472_V_SLOPE 88 /* V (Slope) Fixed decimal | 283 SFF_8472_V_SLOPE = 88, /* V (Slope) Fixed decimal |
| 280 * (unsigned) calibration data, 281 * internal module supply 282 * voltage. Bit 7 of byte 88 is 283 * MSB, bit 0 of byte 89 is 284 * LSB. V(Slope) should be set to 1 285 * for ���internally calibrated��� 286 * devices. */ | 284 * (unsigned) calibration data, 285 * internal module supply 286 * voltage. Bit 7 of byte 88 is 287 * MSB, bit 0 of byte 89 is 288 * LSB. V(Slope) should be set to 1 289 * for ���internally calibrated��� 290 * devices. */ |
| 287#define SFF_8472_V_OFFSET 90 /* V (Offset) Fixed decimal (signed | 291 SFF_8472_V_OFFSET = 90, /* V (Offset) Fixed decimal (signed |
| 288 * two���s complement) calibration 289 * data, internal module supply 290 * voltage. Bit 7 of byte 90 is 291 * MSB. Bit 0 of byte 91 is 292 * LSB. V(Offset) should be set to 293 * zero for ���internally calibrated��� 294 * devices. */ | 292 * two���s complement) calibration 293 * data, internal module supply 294 * voltage. Bit 7 of byte 90 is 295 * MSB. Bit 0 of byte 91 is 296 * LSB. V(Offset) should be set to 297 * zero for ���internally calibrated��� 298 * devices. */ |
| 295#define SFF_8472_CHECKSUM 95 /* Checksum Byte 95 contains the | 299 SFF_8472_CHECKSUM = 95, /* Checksum Byte 95 contains the |
| 296 * low order 8 bits of the sum of 297 * bytes 0 ��� 94. */ | 300 * low order 8 bits of the sum of 301 * bytes 0 ��� 94. */ |
| 298 /* Internal measurements. */ | 302 /* Internal measurements. */ |
| 299 | 303 |
| 300#define SFF_8472_TEMP 96 /* Internally measured module temperature. */ 301#define SFF_8472_VCC 98 /* Internally measured supply | 304 SFF_8472_TEMP = 96, /* Internally measured module temperature. */ 305 SFF_8472_VCC = 98, /* Internally measured supply |
| 302 * voltage in transceiver. 303 */ | 306 * voltage in transceiver. 307 */ |
| 304#define SFF_8472_TX_BIAS 100 /* Internally measured TX Bias Current. */ 305#define SFF_8472_TX_POWER 102 /* Measured TX output power. */ 306#define SFF_8472_RX_POWER 104 /* Measured RX input power. */ | 308 SFF_8472_TX_BIAS = 100, /* Internally measured TX Bias Current. */ 309 SFF_8472_TX_POWER = 102, /* Measured TX output power. */ 310 SFF_8472_RX_POWER = 104, /* Measured RX input power. */ |
| 307 | 311 |
| 308#define SFF_8472_STATUS 110 /* See below */ 309 | 312 SFF_8472_STATUS = 110 /* See below */ 313}; |
| 310 /* Status Bits Described */ 311 312/* 313 * TX Disable State Digital state of the TX Disable Input Pin. Updated 314 * within 100ms of change on pin. 315 */ 316#define SFF_8472_STATUS_TX_DISABLE (1 << 7) 317 --- 49 unchanged lines hidden (view full) --- 367/* 368 * Indicates transceiver has achieved power up and data is ready. Bit 369 * remains high until data is ready to be read at which time the 370 * device sets the bit low. 371 */ 372#define SFF_8472_STATUS_DATA_READY (1 << 0) 373 374/* Table 3.2 Identifier values */ | 314 /* Status Bits Described */ 315 316/* 317 * TX Disable State Digital state of the TX Disable Input Pin. Updated 318 * within 100ms of change on pin. 319 */ 320#define SFF_8472_STATUS_TX_DISABLE (1 << 7) 321 --- 49 unchanged lines hidden (view full) --- 371/* 372 * Indicates transceiver has achieved power up and data is ready. Bit 373 * remains high until data is ready to be read at which time the 374 * device sets the bit low. 375 */ 376#define SFF_8472_STATUS_DATA_READY (1 << 0) 377 378/* Table 3.2 Identifier values */ |
| 375#define SFF_8472_ID_UNKNOWN 0x0 /* Unknown or unspecified */ 376#define SFF_8472_ID_GBIC 0x1 /* GBIC */ 377#define SFF_8472_ID_SFF 0x2 /* Module soldered to motherboard (ex: SFF)*/ 378#define SFF_8472_ID_SFP 0x3 /* SFP or SFP ���Plus��� */ 379#define SFF_8472_ID_XBI 0x4 /* Reserved for ���300 pin XBI��� devices */ 380#define SFF_8472_ID_XENPAK 0x5 /* Reserved for ���Xenpak��� devices */ 381#define SFF_8472_ID_XFP 0x6 /* Reserved for ���XFP��� devices */ 382#define SFF_8472_ID_XFF 0x7 /* Reserved for ���XFF��� devices */ 383#define SFF_8472_ID_XFPE 0x8 /* Reserved for ���XFP-E��� devices */ 384#define SFF_8472_ID_XPAK 0x9 /* Reserved for ���XPak��� devices */ 385#define SFF_8472_ID_X2 0xA /* Reserved for ���X2��� devices */ 386#define SFF_8472_ID_DWDM_SFP 0xB /* Reserved for ���DWDM-SFP��� devices */ 387#define SFF_8472_ID_QSFP 0xC /* Reserved for ���QSFP��� devices */ 388#define SFF_8472_ID_LAST SFF_8472_ID_QSFP | 379enum { 380 SFF_8472_ID_UNKNOWN = 0x0, /* Unknown or unspecified */ 381 SFF_8472_ID_GBIC = 0x1, /* GBIC */ 382 SFF_8472_ID_SFF = 0x2, /* Module soldered to motherboard (ex: SFF)*/ 383 SFF_8472_ID_SFP = 0x3, /* SFP or SFP ���Plus��� */ 384 SFF_8472_ID_XBI = 0x4, /* Reserved for ���300 pin XBI��� devices */ 385 SFF_8472_ID_XENPAK = 0x5, /* Reserved for ���Xenpak��� devices */ 386 SFF_8472_ID_XFP = 0x6, /* Reserved for ���XFP��� devices */ 387 SFF_8472_ID_XFF = 0x7, /* Reserved for ���XFF��� devices */ 388 SFF_8472_ID_XFPE = 0x8, /* Reserved for ���XFP-E��� devices */ 389 SFF_8472_ID_XPAK = 0x9, /* Reserved for ���XPak��� devices */ 390 SFF_8472_ID_X2 = 0xA, /* Reserved for ���X2��� devices */ 391 SFF_8472_ID_DWDM_SFP = 0xB, /* Reserved for ���DWDM-SFP��� devices */ 392 SFF_8472_ID_QSFP = 0xC, /* Reserved for ���QSFP��� devices */ 393 SFF_8472_ID_LAST = SFF_8472_ID_QSFP 394 }; |
| 389 390static char *sff_8472_id[SFF_8472_ID_LAST + 1] = {"Unknown", 391 "GBIC", 392 "SFF", 393 "SFP", 394 "XBI", 395 "Xenpak", 396 "XFP", --- 37 unchanged lines hidden --- | 395 396static char *sff_8472_id[SFF_8472_ID_LAST + 1] = {"Unknown", 397 "GBIC", 398 "SFF", 399 "SFP", 400 "XBI", 401 "Xenpak", 402 "XFP", --- 37 unchanged lines hidden --- |