| intr.h (84541) | intr.h (108737) |
|---|---|
| 1/*- 2 * Copyright (c) 1998 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 1998 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/ia64/include/intr.h 84541 2001-10-05 10:30:09Z dfr $ | 26 * $FreeBSD: head/sys/ia64/include/intr.h 108737 2003-01-05 22:14:30Z marcel $ |
| 27 */ 28 29#ifndef _MACHINE_INTR_H_ 30#define _MACHINE_INTR_H_ 31 32/* 33 * Layout of the Processor Interrupt Block. 34 */ 35struct ia64_interrupt_block 36{ 37 u_int64_t ib_ipi[0x20000]; /* 1Mb of IPI interrupts */ 38 u_int8_t ib_reserved1[0xe0000]; 39 u_int8_t ib_inta; /* Generate INTA cycle */ 40 u_int8_t ib_reserved2[7]; 41 u_int8_t ib_xtp; /* XTP cycle */ 42 u_int8_t ib_reserved3[7]; 43 u_int8_t ib_reserved4[0x1fff0]; 44}; 45 | 27 */ 28 29#ifndef _MACHINE_INTR_H_ 30#define _MACHINE_INTR_H_ 31 32/* 33 * Layout of the Processor Interrupt Block. 34 */ 35struct ia64_interrupt_block 36{ 37 u_int64_t ib_ipi[0x20000]; /* 1Mb of IPI interrupts */ 38 u_int8_t ib_reserved1[0xe0000]; 39 u_int8_t ib_inta; /* Generate INTA cycle */ 40 u_int8_t ib_reserved2[7]; 41 u_int8_t ib_xtp; /* XTP cycle */ 42 u_int8_t ib_reserved3[7]; 43 u_int8_t ib_reserved4[0x1fff0]; 44}; 45 |
| 46extern u_int64_t ia64_lapic_address; 47 |
|
| 46#define IA64_INTERRUPT_BLOCK \ | 48#define IA64_INTERRUPT_BLOCK \ |
| 47 (struct ia64_interrupt_block *)IA64_PHYS_TO_RR6(0xfee00000) | 49 (struct ia64_interrupt_block *)IA64_PHYS_TO_RR6(ia64_lapic_address) |
| 48 49struct sapic; 50 51void ia64_add_sapic(struct sapic *sa); 52int ia64_setup_intr(const char *name, int irq, driver_intr_t handler, 53 void *arg, enum intr_type flags, void **cookiep, 54 volatile long *cntp); 55int ia64_teardown_intr(void *cookie); 56void ia64_dispatch_intr(void *frame, unsigned long vector); 57 58#endif /* !_MACHINE_INTR_H_ */ | 50 51struct sapic; 52 53void ia64_add_sapic(struct sapic *sa); 54int ia64_setup_intr(const char *name, int irq, driver_intr_t handler, 55 void *arg, enum intr_type flags, void **cookiep, 56 volatile long *cntp); 57int ia64_teardown_intr(void *cookie); 58void ia64_dispatch_intr(void *frame, unsigned long vector); 59 60#endif /* !_MACHINE_INTR_H_ */ |