1/*-
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
|
32 * $FreeBSD: head/sys/pci/if_xlreg.h 146435 2005-05-20 07:16:09Z glebius $
|
| 32 * $FreeBSD: head/sys/pci/if_xlreg.h 147256 2005-06-10 16:49:24Z brooks $ |
33 */
34
35#define XL_EE_READ 0x0080 /* read, 5 bit address */
36#define XL_EE_WRITE 0x0040 /* write, 5 bit address */
37#define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */
38#define XL_EE_EWEN 0x0030 /* erase, no data needed */
39#define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */
40#define XL_EE_BUSY 0x8000
41
42#define XL_EE_EADDR0 0x00 /* station address, first word */
43#define XL_EE_EADDR1 0x01 /* station address, next word, */
44#define XL_EE_EADDR2 0x02 /* station address, last word */
45#define XL_EE_PRODID 0x03 /* product ID code */
46#define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */
47#define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */
48#define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */
49#define XL_EE_MFG_ID 0x07
50#define XL_EE_PCI_PARM 0x08
51#define XL_EE_ROM_ONFO 0x09
52#define XL_EE_OEM_ADR0 0x0A
53#define XL_EE_OEM_ADR1 0x0B
54#define XL_EE_OEM_ADR2 0x0C
55#define XL_EE_SOFTINFO1 0x0D
56#define XL_EE_COMPAT 0x0E
57#define XL_EE_SOFTINFO2 0x0F
58#define XL_EE_CAPS 0x10 /* capabilities word */
59#define XL_EE_RSVD0 0x11
60#define XL_EE_ICFG_0 0x12
61#define XL_EE_ICFG_1 0x13
62#define XL_EE_RSVD1 0x14
63#define XL_EE_SOFTINFO3 0x15
64#define XL_EE_RSVD_2 0x16
65
66/*
67 * Bits in the capabilities word
68 */
69#define XL_CAPS_PNP 0x0001
70#define XL_CAPS_FULL_DUPLEX 0x0002
71#define XL_CAPS_LARGE_PKTS 0x0004
72#define XL_CAPS_SLAVE_DMA 0x0008
73#define XL_CAPS_SECOND_DMA 0x0010
74#define XL_CAPS_FULL_BM 0x0020
75#define XL_CAPS_FRAG_BM 0x0040
76#define XL_CAPS_CRC_PASSTHRU 0x0080
77#define XL_CAPS_TXDONE 0x0100
78#define XL_CAPS_NO_TXLENGTH 0x0200
79#define XL_CAPS_RX_REPEAT 0x0400
80#define XL_CAPS_SNOOPING 0x0800
81#define XL_CAPS_100MBPS 0x1000
82#define XL_CAPS_PWRMGMT 0x2000
83
84#define XL_PACKET_SIZE 1540
85#define XL_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)
86
87/*
88 * Register layouts.
89 */
90#define XL_COMMAND 0x0E
91#define XL_STATUS 0x0E
92
93#define XL_TX_STATUS 0x1B
94#define XL_TX_FREE 0x1C
95#define XL_DMACTL 0x20
96#define XL_DOWNLIST_PTR 0x24
97#define XL_DOWN_POLL 0x2D /* 3c90xB only */
98#define XL_TX_FREETHRESH 0x2F
99#define XL_UPLIST_PTR 0x38
100#define XL_UPLIST_STATUS 0x30
101#define XL_UP_POLL 0x3D /* 3c90xB only */
102
103#define XL_PKTSTAT_UP_STALLED 0x00002000
104#define XL_PKTSTAT_UP_ERROR 0x00004000
105#define XL_PKTSTAT_UP_CMPLT 0x00008000
106
107#define XL_DMACTL_DN_CMPLT_REQ 0x00000002
108#define XL_DMACTL_DOWN_STALLED 0x00000004
109#define XL_DMACTL_UP_CMPLT 0x00000008
110#define XL_DMACTL_DOWN_CMPLT 0x00000010
111#define XL_DMACTL_UP_RX_EARLY 0x00000020
112#define XL_DMACTL_ARM_COUNTDOWN 0x00000040
113#define XL_DMACTL_DOWN_INPROG 0x00000080
114#define XL_DMACTL_COUNTER_SPEED 0x00000100
115#define XL_DMACTL_DOWNDOWN_MODE 0x00000200
116#define XL_DMACTL_TARGET_ABORT 0x40000000
117#define XL_DMACTL_MASTER_ABORT 0x80000000
118
119/*
120 * Command codes. Some command codes require that we wait for
121 * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.'
122 */
123#define XL_CMD_RESET 0x0000 /* mustwait */
124#define XL_CMD_WINSEL 0x0800
125#define XL_CMD_COAX_START 0x1000
126#define XL_CMD_RX_DISABLE 0x1800
127#define XL_CMD_RX_ENABLE 0x2000
128#define XL_CMD_RX_RESET 0x2800 /* mustwait */
129#define XL_CMD_UP_STALL 0x3000 /* mustwait */
130#define XL_CMD_UP_UNSTALL 0x3001
131#define XL_CMD_DOWN_STALL 0x3002 /* mustwait */
132#define XL_CMD_DOWN_UNSTALL 0x3003
133#define XL_CMD_RX_DISCARD 0x4000
134#define XL_CMD_TX_ENABLE 0x4800
135#define XL_CMD_TX_DISABLE 0x5000
136#define XL_CMD_TX_RESET 0x5800 /* mustwait */
137#define XL_CMD_INTR_FAKE 0x6000
138#define XL_CMD_INTR_ACK 0x6800
139#define XL_CMD_INTR_ENB 0x7000
140#define XL_CMD_STAT_ENB 0x7800
141#define XL_CMD_RX_SET_FILT 0x8000
142#define XL_CMD_RX_SET_THRESH 0x8800
143#define XL_CMD_TX_SET_THRESH 0x9000
144#define XL_CMD_TX_SET_START 0x9800
145#define XL_CMD_DMA_UP 0xA000
146#define XL_CMD_DMA_STOP 0xA001
147#define XL_CMD_STATS_ENABLE 0xA800
148#define XL_CMD_STATS_DISABLE 0xB000
149#define XL_CMD_COAX_STOP 0xB800
150
151#define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */
152#define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */
153
154#define XL_HASH_SET 0x0400
155#define XL_HASHFILT_SIZE 256
156
157/*
158 * status codes
159 * Note that bits 15 to 13 indicate the currently visible register window
160 * which may be anything from 0 to 7.
161 */
162#define XL_STAT_INTLATCH 0x0001 /* 0 */
163#define XL_STAT_ADFAIL 0x0002 /* 1 */
164#define XL_STAT_TX_COMPLETE 0x0004 /* 2 */
165#define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */
166#define XL_STAT_RX_COMPLETE 0x0010 /* 4 */
167#define XL_STAT_RX_EARLY 0x0020 /* 5 */
168#define XL_STAT_INTREQ 0x0040 /* 6 */
169#define XL_STAT_STATSOFLOW 0x0080 /* 7 */
170#define XL_STAT_DMADONE 0x0100 /* 8 first generation */
171#define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */
172#define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */
173#define XL_STAT_UP_COMPLETE 0x0400 /* 10 */
174#define XL_STAT_DMABUSY 0x0800 /* 11 first generation */
175#define XL_STAT_CMDBUSY 0x1000 /* 12 */
176
177/*
178 * Interrupts we normally want enabled.
179 */
180#define XL_INTRS \
181 (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \
182 XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH)
183
184/*
185 * Window 0 registers
186 */
187#define XL_W0_EE_DATA 0x0C
188#define XL_W0_EE_CMD 0x0A
189#define XL_W0_RSRC_CFG 0x08
190#define XL_W0_ADDR_CFG 0x06
191#define XL_W0_CFG_CTRL 0x04
192
193#define XL_W0_PROD_ID 0x02
194#define XL_W0_MFG_ID 0x00
195
196/*
197 * Window 1
198 */
199
200#define XL_W1_TX_FIFO 0x10
201
202#define XL_W1_FREE_TX 0x0C
203#define XL_W1_TX_STATUS 0x0B
204#define XL_W1_TX_TIMER 0x0A
205#define XL_W1_RX_STATUS 0x08
206#define XL_W1_RX_FIFO 0x00
207
208/*
209 * RX status codes
210 */
211#define XL_RXSTATUS_OVERRUN 0x01
212#define XL_RXSTATUS_RUNT 0x02
213#define XL_RXSTATUS_ALIGN 0x04
214#define XL_RXSTATUS_CRC 0x08
215#define XL_RXSTATUS_OVERSIZE 0x10
216#define XL_RXSTATUS_DRIBBLE 0x20
217
218/*
219 * TX status codes
220 */
221#define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */
222#define XL_TXSTATUS_OVERFLOW 0x04
223#define XL_TXSTATUS_MAXCOLS 0x08
224#define XL_TXSTATUS_UNDERRUN 0x10
225#define XL_TXSTATUS_JABBER 0x20
226#define XL_TXSTATUS_INTREQ 0x40
227#define XL_TXSTATUS_COMPLETE 0x80
228
229/*
230 * Window 2
231 */
232#define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */
233#define XL_W2_STATION_MASK_HI 0x0A
234#define XL_W2_STATION_MASK_MID 0x08
235#define XL_W2_STATION_MASK_LO 0x06
236#define XL_W2_STATION_ADDR_HI 0x04
237#define XL_W2_STATION_ADDR_MID 0x02
238#define XL_W2_STATION_ADDR_LO 0x00
239
240#define XL_RESETOPT_FEATUREMASK (0x0001 | 0x0002 | 0x004)
241#define XL_RESETOPT_D3RESETDIS 0x0008
242#define XL_RESETOPT_DISADVFD 0x0010
243#define XL_RESETOPT_DISADV100 0x0020
244#define XL_RESETOPT_DISAUTONEG 0x0040
245#define XL_RESETOPT_DEBUGMODE 0x0080
246#define XL_RESETOPT_FASTAUTO 0x0100
247#define XL_RESETOPT_FASTEE 0x0200
248#define XL_RESETOPT_FORCEDCONF 0x0400
249#define XL_RESETOPT_TESTPDTPDR 0x0800
250#define XL_RESETOPT_TEST100TX 0x1000
251#define XL_RESETOPT_TEST100RX 0x2000
252
253#define XL_RESETOPT_INVERT_LED 0x0010
254#define XL_RESETOPT_INVERT_MII 0x4000
255
256/*
257 * Window 3 (fifo management)
258 */
259#define XL_W3_INTERNAL_CFG 0x00
260#define XL_W3_MAXPKTSIZE 0x04 /* 3c905B only */
261#define XL_W3_RESET_OPT 0x08
262#define XL_W3_FREE_TX 0x0C
263#define XL_W3_FREE_RX 0x0A
264#define XL_W3_MAC_CTRL 0x06
265
266#define XL_ICFG_CONNECTOR_MASK 0x00F00000
267#define XL_ICFG_CONNECTOR_BITS 20
268
269#define XL_ICFG_RAMSIZE_MASK 0x00000007
270#define XL_ICFG_RAMWIDTH 0x00000008
271#define XL_ICFG_ROMSIZE_MASK (0x00000040 | 0x00000080)
272#define XL_ICFG_DISABLE_BASSD 0x00000100
273#define XL_ICFG_RAMLOC 0x00000200
274#define XL_ICFG_RAMPART (0x00010000 | 0x00020000)
275#define XL_ICFG_XCVRSEL (0x00100000 | 0x00200000 | 0x00400000)
276#define XL_ICFG_AUTOSEL 0x01000000
277
278#define XL_XCVR_10BT 0x00
279#define XL_XCVR_AUI 0x01
280#define XL_XCVR_RSVD_0 0x02
281#define XL_XCVR_COAX 0x03
282#define XL_XCVR_100BTX 0x04
283#define XL_XCVR_100BFX 0x05
284#define XL_XCVR_MII 0x06
285#define XL_XCVR_RSVD_1 0x07
286#define XL_XCVR_AUTO 0x08 /* 3c905B only */
287
288#define XL_MACCTRL_DEFER_EXT_END 0x0001
289#define XL_MACCTRL_DEFER_0 0x0002
290#define XL_MACCTRL_DEFER_1 0x0004
291#define XL_MACCTRL_DEFER_2 0x0008
292#define XL_MACCTRL_DEFER_3 0x0010
293#define XL_MACCTRL_DUPLEX 0x0020
294#define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040
295#define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 /* 3c905B only */
296#define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 /* 3c905B only */
297#define XL_MACCTRL_VLT_END 0x0200 /* 3c905B only */
298
299/*
300 * The 'reset options' register contains power-on reset values
301 * loaded from the EEPROM. This includes the supported media
302 * types on the card. It is also known as the media options register.
303 */
304#define XL_W3_MEDIA_OPT 0x08
305
306#define XL_MEDIAOPT_BT4 0x0001 /* MII */
307#define XL_MEDIAOPT_BTX 0x0002 /* on-chip */
308#define XL_MEDIAOPT_BFX 0x0004 /* on-chip */
309#define XL_MEDIAOPT_BT 0x0008 /* on-chip */
310#define XL_MEDIAOPT_BNC 0x0010 /* on-chip */
311#define XL_MEDIAOPT_AUI 0x0020 /* on-chip */
312#define XL_MEDIAOPT_MII 0x0040 /* MII */
313#define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */
314
315#define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */
316#define XL_MEDIAOPT_MASK 0x01FF
317
318/*
319 * Window 4 (diagnostics)
320 */
321#define XL_W4_UPPERBYTESOK 0x0D
322#define XL_W4_BADSSD 0x0C
323#define XL_W4_MEDIA_STATUS 0x0A
324#define XL_W4_PHY_MGMT 0x08
325#define XL_W4_NET_DIAG 0x06
326#define XL_W4_FIFO_DIAG 0x04
327#define XL_W4_VCO_DIAG 0x02
328
329#define XL_W4_CTRLR_STAT 0x08
330#define XL_W4_TX_DIAG 0x00
331
332#define XL_MII_CLK 0x01
333#define XL_MII_DATA 0x02
334#define XL_MII_DIR 0x04
335
336#define XL_MEDIA_SQE 0x0008
337#define XL_MEDIA_10TP 0x00C0
338#define XL_MEDIA_LNK 0x0080
339#define XL_MEDIA_LNKBEAT 0x0800
340
341#define XL_MEDIASTAT_CRCSTRIP 0x0004
342#define XL_MEDIASTAT_SQEENB 0x0008
343#define XL_MEDIASTAT_COLDET 0x0010
344#define XL_MEDIASTAT_CARRIER 0x0020
345#define XL_MEDIASTAT_JABGUARD 0x0040
346#define XL_MEDIASTAT_LINKBEAT 0x0080
347#define XL_MEDIASTAT_JABDETECT 0x0200
348#define XL_MEDIASTAT_POLREVERS 0x0400
349#define XL_MEDIASTAT_LINKDETECT 0x0800
350#define XL_MEDIASTAT_TXINPROG 0x1000
351#define XL_MEDIASTAT_DCENB 0x4000
352#define XL_MEDIASTAT_AUIDIS 0x8000
353
354#define XL_NETDIAG_TEST_LOWVOLT 0x0001
355#define XL_NETDIAG_ASIC_REVMASK \
356 (0x0002 | 0x0004 | 0x0008 | 0x0010 | 0x0020)
357#define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040
358#define XL_NETDIAG_STATS_ENABLED 0x0080
359#define XL_NETDIAG_TX_FATALERR 0x0100
360#define XL_NETDIAG_TRANSMITTING 0x0200
361#define XL_NETDIAG_RX_ENABLED 0x0400
362#define XL_NETDIAG_TX_ENABLED 0x0800
363#define XL_NETDIAG_FIFO_LOOPBACK 0x1000
364#define XL_NETDIAG_MAC_LOOPBACK 0x2000
365#define XL_NETDIAG_ENDEC_LOOPBACK 0x4000
366#define XL_NETDIAG_EXTERNAL_LOOP 0x8000
367
368/*
369 * Window 5
370 */
371#define XL_W5_STAT_ENB 0x0C
372#define XL_W5_INTR_ENB 0x0A
373#define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */
374#define XL_W5_RX_FILTER 0x08
375#define XL_W5_RX_EARLYTHRESH 0x06
376#define XL_W5_TX_AVAILTHRESH 0x02
377#define XL_W5_TX_STARTTHRESH 0x00
378
379/*
380 * RX filter bits
381 */
382#define XL_RXFILTER_INDIVIDUAL 0x01
383#define XL_RXFILTER_ALLMULTI 0x02
384#define XL_RXFILTER_BROADCAST 0x04
385#define XL_RXFILTER_ALLFRAMES 0x08
386#define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */
387
388/*
389 * Window 6 (stats)
390 */
391#define XL_W6_TX_BYTES_OK 0x0C
392#define XL_W6_RX_BYTES_OK 0x0A
393#define XL_W6_UPPER_FRAMES_OK 0x09
394#define XL_W6_DEFERRED 0x08
395#define XL_W6_RX_OK 0x07
396#define XL_W6_TX_OK 0x06
397#define XL_W6_RX_OVERRUN 0x05
398#define XL_W6_COL_LATE 0x04
399#define XL_W6_COL_SINGLE 0x03
400#define XL_W6_COL_MULTIPLE 0x02
401#define XL_W6_SQE_ERRORS 0x01
402#define XL_W6_CARRIER_LOST 0x00
403
404/*
405 * Window 7 (bus master control)
406 */
407#define XL_W7_BM_ADDR 0x00
408#define XL_W7_BM_LEN 0x06
409#define XL_W7_BM_STATUS 0x0B
410#define XL_W7_BM_TIMEr 0x0A
411
412/*
413 * bus master control registers
414 */
415#define XL_BM_PKTSTAT 0x20
416#define XL_BM_DOWNLISTPTR 0x24
417#define XL_BM_FRAGADDR 0x28
418#define XL_BM_FRAGLEN 0x2C
419#define XL_BM_TXFREETHRESH 0x2F
420#define XL_BM_UPPKTSTAT 0x30
421#define XL_BM_UPLISTPTR 0x38
422
423#define XL_LAST_FRAG 0x80000000
424
425#define XL_MAXFRAGS 63
426#define XL_RX_LIST_CNT 128
427#define XL_TX_LIST_CNT 256
428#define XL_RX_LIST_SZ \
429 (XL_RX_LIST_CNT * sizeof(struct xl_list_onefrag))
430#define XL_TX_LIST_SZ \
431 (XL_TX_LIST_CNT * sizeof(struct xl_list))
432#define XL_MIN_FRAMELEN 60
433#define ETHER_ALIGN 2
434#define XL_INC(x, y) (x) = (x + 1) % y
435
436/*
437 * Boomerang/Cyclone TX/RX list structure.
438 * For the TX lists, bits 0 to 12 of the status word indicate
439 * length.
440 * This looks suspiciously like the ThunderLAN, doesn't it.
441 */
442struct xl_frag {
443 u_int32_t xl_addr; /* 63 addr/len pairs */
444 u_int32_t xl_len;
445};
446
447struct xl_list {
448 u_int32_t xl_next; /* final entry has 0 nextptr */
449 u_int32_t xl_status;
450 struct xl_frag xl_frag[XL_MAXFRAGS];
451};
452
453struct xl_list_onefrag {
454 u_int32_t xl_next; /* final entry has 0 nextptr */
455 u_int32_t xl_status;
456 struct xl_frag xl_frag;
457};
458
459struct xl_list_data {
460 struct xl_list_onefrag *xl_rx_list;
461 struct xl_list *xl_tx_list;
462 u_int32_t xl_rx_dmaaddr;
463 bus_dma_tag_t xl_rx_tag;
464 bus_dmamap_t xl_rx_dmamap;
465 u_int32_t xl_tx_dmaaddr;
466 bus_dma_tag_t xl_tx_tag;
467 bus_dmamap_t xl_tx_dmamap;
468};
469
470struct xl_chain {
471 struct xl_list *xl_ptr;
472 struct mbuf *xl_mbuf;
473 struct xl_chain *xl_next;
474 struct xl_chain *xl_prev;
475 u_int32_t xl_phys;
476 bus_dmamap_t xl_map;
477};
478
479struct xl_chain_onefrag {
480 struct xl_list_onefrag *xl_ptr;
481 struct mbuf *xl_mbuf;
482 struct xl_chain_onefrag *xl_next;
483 bus_dmamap_t xl_map;
484};
485
486struct xl_chain_data {
487 struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT];
488 struct xl_chain xl_tx_chain[XL_TX_LIST_CNT];
489
490 struct xl_chain_onefrag *xl_rx_head;
491
492 /* 3c90x "boomerang" queuing stuff */
493 struct xl_chain *xl_tx_head;
494 struct xl_chain *xl_tx_tail;
495 struct xl_chain *xl_tx_free;
496
497 /* 3c90xB "cyclone/hurricane/tornado" stuff */
498 int xl_tx_prod;
499 int xl_tx_cons;
500 int xl_tx_cnt;
501};
502
503#define XL_RXSTAT_LENMASK 0x00001FFF
504#define XL_RXSTAT_UP_ERROR 0x00004000
505#define XL_RXSTAT_UP_CMPLT 0x00008000
506#define XL_RXSTAT_UP_OVERRUN 0x00010000
507#define XL_RXSTAT_RUNT 0x00020000
508#define XL_RXSTAT_ALIGN 0x00040000
509#define XL_RXSTAT_CRC 0x00080000
510#define XL_RXSTAT_OVERSIZE 0x00100000
511#define XL_RXSTAT_DRIBBLE 0x00800000
512#define XL_RXSTAT_UP_OFLOW 0x01000000
513#define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */
514#define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */
515#define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */
516#define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */
517#define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */
518#define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */
519#define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */
520
521#define XL_TXSTAT_LENMASK 0x00001FFF
522#define XL_TXSTAT_CRCDIS 0x00002000
523#define XL_TXSTAT_TX_INTR 0x00008000
524#define XL_TXSTAT_DL_COMPLETE 0x00010000
525#define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */
526#define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */
527#define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */
528#define XL_TXSTAT_RND_DEFEAT 0x10000000 /* 3c905B only */
529#define XL_TXSTAT_EMPTY 0x20000000 /* 3c905B only */
530#define XL_TXSTAT_DL_INTR 0x80000000
531
532#define XL_CAPABILITY_BM 0x20
533
534struct xl_type {
535 u_int16_t xl_vid;
536 u_int16_t xl_did;
537 char *xl_name;
538};
539
540struct xl_mii_frame {
541 u_int8_t mii_stdelim;
542 u_int8_t mii_opcode;
543 u_int8_t mii_phyaddr;
544 u_int8_t mii_regaddr;
545 u_int8_t mii_turnaround;
546 u_int16_t mii_data;
547};
548
549/*
550 * MII constants
551 */
552#define XL_MII_STARTDELIM 0x01
553#define XL_MII_READOP 0x02
554#define XL_MII_WRITEOP 0x01
555#define XL_MII_TURNAROUND 0x02
556
557/*
558 * The 3C905B adapters implement a few features that we want to
559 * take advantage of, namely the multicast hash filter. With older
560 * chips, you only have the option of turning on reception of all
561 * multicast frames, which is kind of lame.
562 *
563 * We also use this to decide on a transmit strategy. For the 3c90xB
564 * cards, we can use polled descriptor mode, which reduces CPU overhead.
565 */
566#define XL_TYPE_905B 1
567#define XL_TYPE_90X 2
568
569#define XL_FLAG_FUNCREG 0x0001
570#define XL_FLAG_PHYOK 0x0002
571#define XL_FLAG_EEPROM_OFFSET_30 0x0004
572#define XL_FLAG_WEIRDRESET 0x0008
573#define XL_FLAG_8BITROM 0x0010
574#define XL_FLAG_INVERT_LED_PWR 0x0020
575#define XL_FLAG_INVERT_MII_PWR 0x0040
576#define XL_FLAG_NO_XCVR_PWR 0x0080
577#define XL_FLAG_USE_MMIO 0x0100
578#define XL_FLAG_NO_MMIO 0x0200
579
580#define XL_NO_XCVR_PWR_MAGICBITS 0x0900
581
582struct xl_softc {
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583 struct arpcom arpcom; /* interface info */
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| 583 struct ifnet *xl_ifp; /* interface info */ |
584 struct ifmedia ifmedia; /* media info */
585 bus_space_handle_t xl_bhandle;
586 bus_space_tag_t xl_btag;
587 void *xl_intrhand;
588 struct resource *xl_irq;
589 struct resource *xl_res;
590 device_t xl_miibus;
591 struct xl_type *xl_info; /* 3Com adapter info */
592 bus_dma_tag_t xl_mtag;
593 bus_dmamap_t xl_tmpmap; /* spare DMA map */
594 u_int8_t xl_unit; /* interface number */
595 u_int8_t xl_type;
596 u_int32_t xl_xcvr;
597 u_int16_t xl_media;
598 u_int16_t xl_caps;
599 u_int8_t xl_stats_no_timeout;
600 u_int16_t xl_tx_thresh;
601 int xl_if_flags;
602 struct xl_list_data xl_ldata;
603 struct xl_chain_data xl_cdata;
604 struct callout_handle xl_stat_ch;
605 int xl_flags;
606 struct resource *xl_fres;
607 bus_space_handle_t xl_fhandle;
608 bus_space_tag_t xl_ftag;
609 struct mtx xl_mtx;
610 struct task xl_task;
611#ifdef DEVICE_POLLING
612 int rxcycles;
613#endif
614};
615
616#define XL_LOCK(_sc) mtx_lock(&(_sc)->xl_mtx)
617#define XL_UNLOCK(_sc) mtx_unlock(&(_sc)->xl_mtx)
618#define XL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->xl_mtx, MA_OWNED)
619
620#define xl_rx_goodframes(x) \
621 ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok
622
623#define xl_tx_goodframes(x) \
624 ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok
625
626struct xl_stats {
627 u_int8_t xl_carrier_lost;
628 u_int8_t xl_sqe_errs;
629 u_int8_t xl_tx_multi_collision;
630 u_int8_t xl_tx_single_collision;
631 u_int8_t xl_tx_late_collision;
632 u_int8_t xl_rx_overrun;
633 u_int8_t xl_tx_frames_ok;
634 u_int8_t xl_rx_frames_ok;
635 u_int8_t xl_tx_deferred;
636 u_int8_t xl_upper_frames_ok;
637 u_int16_t xl_rx_bytes_ok;
638 u_int16_t xl_tx_bytes_ok;
639 u_int16_t status;
640};
641
642/*
643 * register space access macros
644 */
645#define CSR_WRITE_4(sc, reg, val) \
646 bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val)
647#define CSR_WRITE_2(sc, reg, val) \
648 bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val)
649#define CSR_WRITE_1(sc, reg, val) \
650 bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val)
651
652#define CSR_READ_4(sc, reg) \
653 bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg)
654#define CSR_READ_2(sc, reg) \
655 bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg)
656#define CSR_READ_1(sc, reg) \
657 bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg)
658
659#define XL_SEL_WIN(x) \
660 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x)
661#define XL_TIMEOUT 1000
662
663/*
664 * General constants that are fun to know.
665 *
666 * 3Com PCI vendor ID
667 */
668#define TC_VENDORID 0x10B7
669
670/*
671 * 3Com chip device IDs.
672 */
673#define TC_DEVICEID_BOOMERANG_10BT 0x9000
674#define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001
675#define TC_DEVICEID_BOOMERANG_10_100BT 0x9050
676#define TC_DEVICEID_BOOMERANG_100BT4 0x9051
677#define TC_DEVICEID_KRAKATOA_10BT 0x9004
678#define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005
679#define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006
680#define TC_DEVICEID_CYCLONE_10FL 0x900A
681#define TC_DEVICEID_HURRICANE_10_100BT 0x9055
682#define TC_DEVICEID_CYCLONE_10_100BT4 0x9056
683#define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058
684#define TC_DEVICEID_CYCLONE_10_100FX 0x905A
685#define TC_DEVICEID_TORNADO_10_100BT 0x9200
686#define TC_DEVICEID_TORNADO_10_100BT_920B 0x9201
687#define TC_DEVICEID_TORNADO_10_100BT_920B_WNM 0x9202
688#define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800
689#define TC_DEVICEID_TORNADO_10_100BT_SERV 0x9805
690#define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646
691#define TC_DEVICEID_TORNADO_HOMECONNECT 0x4500
692#define TC_DEVICEID_HURRICANE_555 0x5055
693#define TC_DEVICEID_HURRICANE_556 0x6055
694#define TC_DEVICEID_HURRICANE_556B 0x6056
695#define TC_DEVICEID_HURRICANE_575A 0x5057
696#define TC_DEVICEID_HURRICANE_575B 0x5157
697#define TC_DEVICEID_HURRICANE_575C 0x5257
698#define TC_DEVICEID_HURRICANE_656 0x6560
699#define TC_DEVICEID_HURRICANE_656B 0x6562
700#define TC_DEVICEID_TORNADO_656C 0x6564
701
702/*
703 * PCI low memory base and low I/O base register, and
704 * other PCI registers. Note: some are only available on
705 * the 3c905B, in particular those that related to power management.
706 */
707#define XL_PCI_VENDOR_ID 0x00
708#define XL_PCI_DEVICE_ID 0x02
709#define XL_PCI_COMMAND 0x04
710#define XL_PCI_STATUS 0x06
711#define XL_PCI_CLASSCODE 0x09
712#define XL_PCI_LATENCY_TIMER 0x0D
713#define XL_PCI_HEADER_TYPE 0x0E
714#define XL_PCI_LOIO 0x10
715#define XL_PCI_LOMEM 0x14
716#define XL_PCI_FUNCMEM 0x18
717#define XL_PCI_BIOSROM 0x30
718#define XL_PCI_INTLINE 0x3C
719#define XL_PCI_INTPIN 0x3D
720#define XL_PCI_MINGNT 0x3E
721#define XL_PCI_MINLAT 0x0F
722#define XL_PCI_RESETOPT 0x48
723#define XL_PCI_EEPROM_DATA 0x4C
724
725/* 3c905B-only registers */
726#define XL_PCI_CAPID 0xDC /* 8 bits */
727#define XL_PCI_NEXTPTR 0xDD /* 8 bits */
728#define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */
729#define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */
730
731#define XL_PSTATE_MASK 0x0003
732#define XL_PSTATE_D0 0x0000
733#define XL_PSTATE_D1 0x0002
734#define XL_PSTATE_D2 0x0002
735#define XL_PSTATE_D3 0x0003
736#define XL_PME_EN 0x0010
737#define XL_PME_STATUS 0x8000
738
739#ifndef IFM_10_FL
740#define IFM_10_FL 13 /* 10baseFL - Fiber */
741#endif
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