1/*-
2 * Copyright (c) 1997, 1998, 1999, 2000
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/dev/usb2/ethernet/if_cuereg.h 187378 2009-01-18 05:35:58Z thompsa $
33 */
34
35/*
36 * Definitions for the CATC Netmate II USB to ethernet controller.
37 */
38
39/* Vendor specific control commands. */
40#define CUE_CMD_RESET 0xF4
41#define CUE_CMD_GET_MACADDR 0xF2
42#define CUE_CMD_WRITEREG 0xFA
43#define CUE_CMD_READREG 0xFB
44#define CUE_CMD_READSRAM 0xF1
45#define CUE_CMD_WRITESRAM 0xFC
46/* Internal registers. */
47#define CUE_TX_BUFCNT 0x20
48#define CUE_RX_BUFCNT 0x21
49#define CUE_ADVANCED_OPMODES 0x22
50#define CUE_TX_BUFPKTS 0x23
51#define CUE_RX_BUFPKTS 0x24
52#define CUE_RX_MAXCHAIN 0x25
53#define CUE_ETHCTL 0x60
54#define CUE_ETHSTS 0x61
55#define CUE_PAR5 0x62
56#define CUE_PAR4 0x63
57#define CUE_PAR3 0x64
58#define CUE_PAR2 0x65
59#define CUE_PAR1 0x66
60#define CUE_PAR0 0x67
61/* Error counters, all 16 bits wide. */
62#define CUE_TX_SINGLECOLL 0x69
63#define CUE_TX_MULTICOLL 0x6B
64#define CUE_TX_EXCESSCOLL 0x6D
65#define CUE_RX_FRAMEERR 0x6F
66#define CUE_LEDCTL 0x81
67/* Advenced operating mode register. */
68#define CUE_AOP_SRAMWAITS 0x03
69#define CUE_AOP_EMBED_RXLEN 0x08
70#define CUE_AOP_RXCOMBINE 0x10
71#define CUE_AOP_TXCOMBINE 0x20
72#define CUE_AOP_EVEN_PKT_READS 0x40
73#define CUE_AOP_LOOPBK 0x80
74/* Ethernet control register. */
75#define CUE_ETHCTL_RX_ON 0x01
76#define CUE_ETHCTL_LINK_POLARITY 0x02
77#define CUE_ETHCTL_LINK_FORCE_OK 0x04
78#define CUE_ETHCTL_MCAST_ON 0x08
79#define CUE_ETHCTL_PROMISC 0x10
80/* Ethernet status register. */
81#define CUE_ETHSTS_NO_CARRIER 0x01
82#define CUE_ETHSTS_LATECOLL 0x02
83#define CUE_ETHSTS_EXCESSCOLL 0x04
84#define CUE_ETHSTS_TXBUF_AVAIL 0x08
85#define CUE_ETHSTS_BAD_POLARITY 0x10
86#define CUE_ETHSTS_LINK_OK 0x20
87/* LED control register. */
88#define CUE_LEDCTL_BLINK_1X 0x00
89#define CUE_LEDCTL_BLINK_2X 0x01
90#define CUE_LEDCTL_BLINK_QUARTER_ON 0x02
91#define CUE_LEDCTL_BLINK_QUARTER_OFF 0x03
92#define CUE_LEDCTL_OFF 0x04
93#define CUE_LEDCTL_FOLLOW_LINK 0x08
94
95/*
96 * Address in ASIC's internal SRAM where the multicast hash table lives.
97 * The table is 64 bytes long, giving us a 512-bit table. We have to set
98 * the bit that corresponds to the broadcast address in order to enable
99 * reception of broadcast frames.
100 */
101#define CUE_MCAST_TABLE_ADDR 0xFA80
102#define CUE_MCAST_TABLE_LEN 64
103
104#define CUE_TIMEOUT 1000
105#define CUE_MIN_FRAMELEN 60
106#define CUE_RX_FRAMES 1
107#define CUE_TX_FRAMES 1
108
109#define CUE_CTL_READ 0x01
110#define CUE_CTL_WRITE 0x02
111
112#define CUE_CONFIG_IDX 0 /* config number 1 */
113#define CUE_IFACE_IDX 0
114
115/* The interrupt endpoint is currently unused by the KLSI part. */
116enum {
117 CUE_BULK_DT_WR,
118 CUE_BULK_DT_RD,
119 CUE_BULK_CS_WR,
120 CUE_BULK_CS_RD,
121 CUE_N_TRANSFER = 4,
122};
123
124struct cue_softc {
125 struct ifnet *sc_ifp;
126
127 struct usb2_config_td sc_config_td;
128 struct usb2_callout sc_watchdog;
129 struct mtx sc_mtx;
130
131 device_t sc_dev;
132 struct usb2_device *sc_udev;
133 struct usb2_xfer *sc_xfer[CUE_N_TRANSFER];
134
135 uint32_t sc_unit;
136
137 uint16_t sc_flags;
138#define CUE_FLAG_READ_STALL 0x0010 /* wait for clearing of stall */
139#define CUE_FLAG_WRITE_STALL 0x0020 /* wait for clearing of stall */
140#define CUE_FLAG_LL_READY 0x0040 /* Lower Layer Ready */
141#define CUE_FLAG_HL_READY 0x0080 /* Higher Layer Ready */
142#define CUE_FLAG_INTR_STALL 0x0100 /* wait for clearing of stall */
143};