| xhcireg.h (229084) | xhcireg.h (242774) |
|---|---|
| 1/* $FreeBSD: stable/9/sys/dev/usb/controller/xhcireg.h 229084 2011-12-31 13:23:04Z hselasky $ */ | 1/* $FreeBSD: stable/9/sys/dev/usb/controller/xhcireg.h 242774 2012-11-08 16:04:32Z hselasky $ */ |
| 2 3/*- 4 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright --- 19 unchanged lines hidden (view full) --- 29#define _XHCIREG_H_ 30 31/* XHCI PCI config registers */ 32#define PCI_XHCI_CBMEM 0x10 /* configuration base MEM */ 33#define PCI_XHCI_USBREV 0x60 /* RO USB protocol revision */ 34#define PCI_USB_REV_3_0 0x30 /* USB 3.0 */ 35#define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ 36 | 2 3/*- 4 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright --- 19 unchanged lines hidden (view full) --- 29#define _XHCIREG_H_ 30 31/* XHCI PCI config registers */ 32#define PCI_XHCI_CBMEM 0x10 /* configuration base MEM */ 33#define PCI_XHCI_USBREV 0x60 /* RO USB protocol revision */ 34#define PCI_USB_REV_3_0 0x30 /* USB 3.0 */ 35#define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ 36 |
| 37#define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */ 38#define PCI_XHCI_INTEL_USB3_PSSEN 0xD8 /* Intel USB3 Port SuperSpeed Enable */ 39 |
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| 37/* XHCI capability registers */ 38#define XHCI_CAPLENGTH 0x00 /* RO capability */ 39#define XHCI_RESERVED 0x01 /* Reserved */ 40#define XHCI_HCIVERSION 0x02 /* RO Interface version number */ 41#define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */ 42#define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */ 43#define XHCI_HCSPARAMS1 0x04 /* RO structual parameters 1 */ 44#define XHCI_HCS1_DEVSLOT_MAX(x)((x) & 0xFF) --- 174 unchanged lines hidden --- | 40/* XHCI capability registers */ 41#define XHCI_CAPLENGTH 0x00 /* RO capability */ 42#define XHCI_RESERVED 0x01 /* Reserved */ 43#define XHCI_HCIVERSION 0x02 /* RO Interface version number */ 44#define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */ 45#define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */ 46#define XHCI_HCSPARAMS1 0x04 /* RO structual parameters 1 */ 47#define XHCI_HCS1_DEVSLOT_MAX(x)((x) & 0xFF) --- 174 unchanged lines hidden --- |