| if_tireg.h (76033) | if_tireg.h (98849) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/dev/ti/if_tireg.h 76033 2001-04-26 16:40:45Z wpaul $ | 32 * $FreeBSD: head/sys/dev/ti/if_tireg.h 98849 2002-06-26 03:37:47Z ken $ |
| 33 */ 34 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. --- 91 unchanged lines hidden (view full) --- 132#define TI_REV_TIGON_I 0x40000000 133#define TI_REV_TIGON_II 0x60000000 134 135/* 136 * Firmware revision that we want. 137 */ 138#define TI_FIRMWARE_MAJOR 0xc 139#define TI_FIRMWARE_MINOR 0x4 | 33 */ 34 35/* 36 * Tigon register offsets. These are memory mapped registers 37 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 38 * Each register must be accessed using 32 bit operations. 39 * 40 * All reegisters are accessed through a 16K shared memory block. --- 91 unchanged lines hidden (view full) --- 132#define TI_REV_TIGON_I 0x40000000 133#define TI_REV_TIGON_II 0x60000000 134 135/* 136 * Firmware revision that we want. 137 */ 138#define TI_FIRMWARE_MAJOR 0xc 139#define TI_FIRMWARE_MINOR 0x4 |
| 140#define TI_FIRMWARE_FIX 0xd | 140#define TI_FIRMWARE_FIX 0xb |
| 141 142/* 143 * Miscelaneous Local Control register. 144 */ 145#define TI_MLC_EE_WRITE_ENB 0x00000010 146#define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 147#define TI_MLC_LOCALADDR_21 0x00004000 148#define TI_MLC_LOCALADDR_22 0x00008000 --- 194 unchanged lines hidden (view full) --- 343#define TI_OPMODE_SBUS 0x00000100 344#define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200 345#define TI_OPMODE_INCLUDE_CRC 0x00000400 346#define TI_OPMODE_RX_BADFRAMES 0x00000800 347#define TI_OPMODE_NO_EVENT_INTRS 0x00001000 348#define TI_OPMODE_NO_TX_INTRS 0x00002000 349#define TI_OPMODE_NO_RX_INTRS 0x00004000 350#define TI_OPMODE_FATAL_ENB 0x40000000 /* not yet implimented */ | 141 142/* 143 * Miscelaneous Local Control register. 144 */ 145#define TI_MLC_EE_WRITE_ENB 0x00000010 146#define TI_MLC_SRAM_BANK_SIZE 0x00000300 /* Tigon 2 only */ 147#define TI_MLC_LOCALADDR_21 0x00004000 148#define TI_MLC_LOCALADDR_22 0x00008000 --- 194 unchanged lines hidden (view full) --- 343#define TI_OPMODE_SBUS 0x00000100 344#define TI_OPMODE_DONT_FRAG_JUMBO 0x00000200 345#define TI_OPMODE_INCLUDE_CRC 0x00000400 346#define TI_OPMODE_RX_BADFRAMES 0x00000800 347#define TI_OPMODE_NO_EVENT_INTRS 0x00001000 348#define TI_OPMODE_NO_TX_INTRS 0x00002000 349#define TI_OPMODE_NO_RX_INTRS 0x00004000 350#define TI_OPMODE_FATAL_ENB 0x40000000 /* not yet implimented */ |
| 351#define TI_OPMODE_JUMBO_HDRSPLIT 0x00008000 |
|
| 351 352/* 353 * DMA configuration thresholds. 354 */ 355#define TI_DMA_STATE_THRESH_16W 0x00000100 356#define TI_DMA_STATE_THRESH_8W 0x00000080 357#define TI_DMA_STATE_THRESH_4W 0x00000040 358#define TI_DMA_STATE_THRESH_2W 0x00000020 --- 59 unchanged lines hidden (view full) --- 418 * is limited to 2MB total, and in general I think most adapters have 419 * around 1MB. We use this value for zeroing the NIC's SRAM, so to 420 * be safe we use the largest possible value (zeroing memory that 421 * isn't there doesn't hurt anything). 422 */ 423#define TI_MEM_MAX 0x7FFFFF 424 425/* | 352 353/* 354 * DMA configuration thresholds. 355 */ 356#define TI_DMA_STATE_THRESH_16W 0x00000100 357#define TI_DMA_STATE_THRESH_8W 0x00000080 358#define TI_DMA_STATE_THRESH_4W 0x00000040 359#define TI_DMA_STATE_THRESH_2W 0x00000020 --- 59 unchanged lines hidden (view full) --- 419 * is limited to 2MB total, and in general I think most adapters have 420 * around 1MB. We use this value for zeroing the NIC's SRAM, so to 421 * be safe we use the largest possible value (zeroing memory that 422 * isn't there doesn't hurt anything). 423 */ 424#define TI_MEM_MAX 0x7FFFFF 425 426/* |
| 427 * Maximum register address on the Tigon. 428 */ 429#define TI_REG_MAX 0x3fff 430 431/* 432 * These values were taken from Alteon's tg.h. 433 */ 434#define TI_BEG_SRAM 0x0 /* host thinks it's here */ 435#define TI_BEG_SCRATCH 0xc00000 /* beg of scratch pad area */ 436#define TI_END_SRAM_II 0x800000 /* end of SRAM, for 2 MB stuffed */ 437#define TI_END_SCRATCH_II 0xc04000 /* end of scratch pad CPU A (16KB) */ 438#define TI_END_SCRATCH_B 0xc02000 /* end of scratch pad CPU B (8KB) */ 439#define TI_BEG_SCRATCH_B_DEBUG 0xd00000 /* beg of scratch pad for ioctl */ 440#define TI_END_SCRATCH_B_DEBUG 0xd02000 /* end of scratch pad for ioctl */ 441#define TI_SCRATCH_DEBUG_OFF 0x100000 /* offset for ioctl usage */ 442#define TI_END_SRAM_I 0x200000 /* end of SRAM, for 2 MB stuffed */ 443#define TI_END_SCRATCH_I 0xc00800 /* end of scratch pad area (2KB) */ 444#define TI_BEG_PROM 0x40000000 /* beg of PROM, special access */ 445#define TI_BEG_FLASH 0x80000000 /* beg of EEPROM, special access */ 446#define TI_END_FLASH 0x80100000 /* end of EEPROM for 1 MB stuff */ 447#define TI_BEG_SER_EEPROM 0xa0000000 /* beg of Serial EEPROM (fake out) */ 448#define TI_END_SER_EEPROM 0xa0002000 /* end of Serial EEPROM (fake out) */ 449#define TI_BEG_REGS 0xc0000000 /* beg of register area */ 450#define TI_END_REGS 0xc0000400 /* end of register area */ 451#define TI_END_WRITE_REGS 0xc0000180 /* can't write GPRs currently */ 452#define TI_BEG_REGS2 0xc0000200 /* beg of second writeable reg area */ 453/* the EEPROM is byte addressable in a pretty odd way */ 454#define EEPROM_BYTE_LOC 0xff000000 455 456/* 457 * From Alteon's tg.h. 458 */ 459#define TI_PROCESSOR_A 0 460#define TI_PROCESSOR_B 1 461#define TI_CPU_A TG_PROCESSOR_A 462#define TI_CPU_B TG_PROCESSOR_B 463 464/* 465 * Following macro can be used to access to any of the CPU registers 466 * It will adjust the address appropriately. 467 * Parameters: 468 * reg - The register to access, e.g TI_CPU_CONTROL 469 * cpu - cpu, i.e PROCESSOR_A or PROCESSOR_B (or TI_CPU_A or TI_CPU_B) 470 */ 471#define CPU_REG(reg, cpu) ((reg) + (cpu) * 0x100) 472 473/* |
|
| 426 * Even on the alpha, pci addresses are 32-bit quantities 427 */ 428 429#ifdef __64_bit_pci_addressing__ 430typedef struct { 431 u_int64_t ti_addr; 432} ti_hostaddr; 433#define TI_HOSTADDR(x) x.ti_addr --- 48 unchanged lines hidden (view full) --- 482#define TI_RCB_FLAG_RING_DISABLED 0x00000200 483 484struct ti_producer { 485 u_int32_t ti_idx; 486 u_int32_t ti_unused; 487}; 488 489/* | 474 * Even on the alpha, pci addresses are 32-bit quantities 475 */ 476 477#ifdef __64_bit_pci_addressing__ 478typedef struct { 479 u_int64_t ti_addr; 480} ti_hostaddr; 481#define TI_HOSTADDR(x) x.ti_addr --- 48 unchanged lines hidden (view full) --- 530#define TI_RCB_FLAG_RING_DISABLED 0x00000200 531 532struct ti_producer { 533 u_int32_t ti_idx; 534 u_int32_t ti_unused; 535}; 536 537/* |
| 490 * Tigon statistics counters. 491 */ 492struct ti_stats { 493 /* 494 * MAC stats, taken from RFC 1643, ethernet-like MIB 495 */ 496 volatile u_int32_t dot3StatsAlignmentErrors; /* 0 */ 497 volatile u_int32_t dot3StatsFCSErrors; /* 1 */ 498 volatile u_int32_t dot3StatsSingleCollisionFrames; /* 2 */ 499 volatile u_int32_t dot3StatsMultipleCollisionFrames; /* 3 */ 500 volatile u_int32_t dot3StatsSQETestErrors; /* 4 */ 501 volatile u_int32_t dot3StatsDeferredTransmissions; /* 5 */ 502 volatile u_int32_t dot3StatsLateCollisions; /* 6 */ 503 volatile u_int32_t dot3StatsExcessiveCollisions; /* 7 */ 504 volatile u_int32_t dot3StatsInternalMacTransmitErrors; /* 8 */ 505 volatile u_int32_t dot3StatsCarrierSenseErrors; /* 9 */ 506 volatile u_int32_t dot3StatsFrameTooLongs; /* 10 */ 507 volatile u_int32_t dot3StatsInternalMacReceiveErrors; /* 11 */ 508 /* 509 * interface stats, taken from RFC 1213, MIB-II, interfaces group 510 */ 511 volatile u_int32_t ifIndex; /* 12 */ 512 volatile u_int32_t ifType; /* 13 */ 513 volatile u_int32_t ifMtu; /* 14 */ 514 volatile u_int32_t ifSpeed; /* 15 */ 515 volatile u_int32_t ifAdminStatus; /* 16 */ 516#define IF_ADMIN_STATUS_UP 1 517#define IF_ADMIN_STATUS_DOWN 2 518#define IF_ADMIN_STATUS_TESTING 3 519 volatile u_int32_t ifOperStatus; /* 17 */ 520#define IF_OPER_STATUS_UP 1 521#define IF_OPER_STATUS_DOWN 2 522#define IF_OPER_STATUS_TESTING 3 523#define IF_OPER_STATUS_UNKNOWN 4 524#define IF_OPER_STATUS_DORMANT 5 525 volatile u_int32_t ifLastChange; /* 18 */ 526 volatile u_int32_t ifInDiscards; /* 19 */ 527 volatile u_int32_t ifInErrors; /* 20 */ 528 volatile u_int32_t ifInUnknownProtos; /* 21 */ 529 volatile u_int32_t ifOutDiscards; /* 22 */ 530 volatile u_int32_t ifOutErrors; /* 23 */ 531 volatile u_int32_t ifOutQLen; /* deprecated */ /* 24 */ 532 volatile u_int8_t ifPhysAddress[8]; /* 8 bytes */ /* 25 - 26 */ 533 volatile u_int8_t ifDescr[32]; /* 27 - 34 */ 534 u_int32_t alignIt; /* align to 64 bit for u_int64_ts following */ 535 /* 536 * more interface stats, taken from RFC 1573, MIB-IIupdate, 537 * interfaces group 538 */ 539 volatile u_int64_t ifHCInOctets; /* 36 - 37 */ 540 volatile u_int64_t ifHCInUcastPkts; /* 38 - 39 */ 541 volatile u_int64_t ifHCInMulticastPkts; /* 40 - 41 */ 542 volatile u_int64_t ifHCInBroadcastPkts; /* 42 - 43 */ 543 volatile u_int64_t ifHCOutOctets; /* 44 - 45 */ 544 volatile u_int64_t ifHCOutUcastPkts; /* 46 - 47 */ 545 volatile u_int64_t ifHCOutMulticastPkts; /* 48 - 49 */ 546 volatile u_int64_t ifHCOutBroadcastPkts; /* 50 - 51 */ 547 volatile u_int32_t ifLinkUpDownTrapEnable; /* 52 */ 548 volatile u_int32_t ifHighSpeed; /* 53 */ 549 volatile u_int32_t ifPromiscuousMode; /* 54 */ 550 volatile u_int32_t ifConnectorPresent; /* follow link state 55 */ 551 /* 552 * Host Commands 553 */ 554 volatile u_int32_t nicCmdsHostState; /* 56 */ 555 volatile u_int32_t nicCmdsFDRFiltering; /* 57 */ 556 volatile u_int32_t nicCmdsSetRecvProdIndex; /* 58 */ 557 volatile u_int32_t nicCmdsUpdateGencommStats; /* 59 */ 558 volatile u_int32_t nicCmdsResetJumboRing; /* 60 */ 559 volatile u_int32_t nicCmdsAddMCastAddr; /* 61 */ 560 volatile u_int32_t nicCmdsDelMCastAddr; /* 62 */ 561 volatile u_int32_t nicCmdsSetPromiscMode; /* 63 */ 562 volatile u_int32_t nicCmdsLinkNegotiate; /* 64 */ 563 volatile u_int32_t nicCmdsSetMACAddr; /* 65 */ 564 volatile u_int32_t nicCmdsClearProfile; /* 66 */ 565 volatile u_int32_t nicCmdsSetMulticastMode; /* 67 */ 566 volatile u_int32_t nicCmdsClearStats; /* 68 */ 567 volatile u_int32_t nicCmdsSetRecvJumboProdIndex; /* 69 */ 568 volatile u_int32_t nicCmdsSetRecvMiniProdIndex; /* 70 */ 569 volatile u_int32_t nicCmdsRefreshStats; /* 71 */ 570 volatile u_int32_t nicCmdsUnknown; /* 72 */ 571 /* 572 * NIC Events 573 */ 574 volatile u_int32_t nicEventsNICFirmwareOperational; /* 73 */ 575 volatile u_int32_t nicEventsStatsUpdated; /* 74 */ 576 volatile u_int32_t nicEventsLinkStateChanged; /* 75 */ 577 volatile u_int32_t nicEventsError; /* 76 */ 578 volatile u_int32_t nicEventsMCastListUpdated; /* 77 */ 579 volatile u_int32_t nicEventsResetJumboRing; /* 78 */ 580 /* 581 * Ring manipulation 582 */ 583 volatile u_int32_t nicRingSetSendProdIndex; /* 79 */ 584 volatile u_int32_t nicRingSetSendConsIndex; /* 80 */ 585 volatile u_int32_t nicRingSetRecvReturnProdIndex; /* 81 */ 586 /* 587 * Interrupts 588 */ 589 volatile u_int32_t nicInterrupts; /* 82 */ 590 volatile u_int32_t nicAvoidedInterrupts; /* 83 */ 591 /* 592 * BD Coalessing Thresholds 593 */ 594 volatile u_int32_t nicEventThresholdHit; /* 84 */ 595 volatile u_int32_t nicSendThresholdHit; /* 85 */ 596 volatile u_int32_t nicRecvThresholdHit; /* 86 */ 597 /* 598 * DMA Attentions 599 */ 600 volatile u_int32_t nicDmaRdOverrun; /* 87 */ 601 volatile u_int32_t nicDmaRdUnderrun; /* 88 */ 602 volatile u_int32_t nicDmaWrOverrun; /* 89 */ 603 volatile u_int32_t nicDmaWrUnderrun; /* 90 */ 604 volatile u_int32_t nicDmaWrMasterAborts; /* 91 */ 605 volatile u_int32_t nicDmaRdMasterAborts; /* 92 */ 606 /* 607 * NIC Resources 608 */ 609 volatile u_int32_t nicDmaWriteRingFull; /* 93 */ 610 volatile u_int32_t nicDmaReadRingFull; /* 94 */ 611 volatile u_int32_t nicEventRingFull; /* 95 */ 612 volatile u_int32_t nicEventProducerRingFull; /* 96 */ 613 volatile u_int32_t nicTxMacDescrRingFull; /* 97 */ 614 volatile u_int32_t nicOutOfTxBufSpaceFrameRetry; /* 98 */ 615 volatile u_int32_t nicNoMoreWrDMADescriptors; /* 99 */ 616 volatile u_int32_t nicNoMoreRxBDs; /* 100 */ 617 volatile u_int32_t nicNoSpaceInReturnRing; /* 101 */ 618 volatile u_int32_t nicSendBDs; /* current count 102 */ 619 volatile u_int32_t nicRecvBDs; /* current count 103 */ 620 volatile u_int32_t nicJumboRecvBDs; /* current count 104 */ 621 volatile u_int32_t nicMiniRecvBDs; /* current count 105 */ 622 volatile u_int32_t nicTotalRecvBDs; /* current count 106 */ 623 volatile u_int32_t nicTotalSendBDs; /* current count 107 */ 624 volatile u_int32_t nicJumboSpillOver; /* 108 */ 625 volatile u_int32_t nicSbusHangCleared; /* 109 */ 626 volatile u_int32_t nicEnqEventDelayed; /* 110 */ 627 /* 628 * Stats from MAC rx completion 629 */ 630 volatile u_int32_t nicMacRxLateColls; /* 111 */ 631 volatile u_int32_t nicMacRxLinkLostDuringPkt; /* 112 */ 632 volatile u_int32_t nicMacRxPhyDecodeErr; /* 113 */ 633 volatile u_int32_t nicMacRxMacAbort; /* 114 */ 634 volatile u_int32_t nicMacRxTruncNoResources; /* 115 */ 635 /* 636 * Stats from the mac_stats area 637 */ 638 volatile u_int32_t nicMacRxDropUla; /* 116 */ 639 volatile u_int32_t nicMacRxDropMcast; /* 117 */ 640 volatile u_int32_t nicMacRxFlowControl; /* 118 */ 641 volatile u_int32_t nicMacRxDropSpace; /* 119 */ 642 volatile u_int32_t nicMacRxColls; /* 120 */ 643 /* 644 * MAC RX Attentions 645 */ 646 volatile u_int32_t nicMacRxTotalAttns; /* 121 */ 647 volatile u_int32_t nicMacRxLinkAttns; /* 122 */ 648 volatile u_int32_t nicMacRxSyncAttns; /* 123 */ 649 volatile u_int32_t nicMacRxConfigAttns; /* 124 */ 650 volatile u_int32_t nicMacReset; /* 125 */ 651 volatile u_int32_t nicMacRxBufDescrAttns; /* 126 */ 652 volatile u_int32_t nicMacRxBufAttns; /* 127 */ 653 volatile u_int32_t nicMacRxZeroFrameCleanup; /* 128 */ 654 volatile u_int32_t nicMacRxOneFrameCleanup; /* 129 */ 655 volatile u_int32_t nicMacRxMultipleFrameCleanup; /* 130 */ 656 volatile u_int32_t nicMacRxTimerCleanup; /* 131 */ 657 volatile u_int32_t nicMacRxDmaCleanup; /* 132 */ 658 /* 659 * Stats from the mac_stats area 660 */ 661 volatile u_int32_t nicMacTxCollisionHistogram[15]; /* 133 */ 662 /* 663 * MAC TX Attentions 664 */ 665 volatile u_int32_t nicMacTxTotalAttns; /* 134 */ 666 /* 667 * NIC Profile 668 */ 669 volatile u_int32_t nicProfile[32]; /* 135 */ 670 /* 671 * Pat to 1024 bytes. 672 */ 673 u_int32_t pad[75]; 674}; 675/* | |
| 676 * Tigon general information block. This resides in host memory 677 * and contains the status counters, ring control blocks and 678 * producer pointers. 679 */ 680 681struct ti_gib { 682 struct ti_stats ti_stats; 683 struct ti_rcb ti_ev_rcb; --- 368 unchanged lines hidden (view full) --- 1052/* 1053 * Ring structures. Most of these reside in host memory and we tell 1054 * the NIC where they are via the ring control blocks. The exceptions 1055 * are the tx and command rings, which live in NIC memory and which 1056 * we access via the shared memory window. 1057 */ 1058struct ti_ring_data { 1059 struct ti_rx_desc ti_rx_std_ring[TI_STD_RX_RING_CNT]; | 538 * Tigon general information block. This resides in host memory 539 * and contains the status counters, ring control blocks and 540 * producer pointers. 541 */ 542 543struct ti_gib { 544 struct ti_stats ti_stats; 545 struct ti_rcb ti_ev_rcb; --- 368 unchanged lines hidden (view full) --- 914/* 915 * Ring structures. Most of these reside in host memory and we tell 916 * the NIC where they are via the ring control blocks. The exceptions 917 * are the tx and command rings, which live in NIC memory and which 918 * we access via the shared memory window. 919 */ 920struct ti_ring_data { 921 struct ti_rx_desc ti_rx_std_ring[TI_STD_RX_RING_CNT]; |
| 922#ifdef PRIVATE_JUMBOS |
|
| 1060 struct ti_rx_desc ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT]; | 923 struct ti_rx_desc ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT]; |
| 924#else 925 struct ti_rx_desc_ext ti_rx_jumbo_ring[TI_JUMBO_RX_RING_CNT]; 926#endif |
|
| 1061 struct ti_rx_desc ti_rx_mini_ring[TI_MINI_RX_RING_CNT]; 1062 struct ti_rx_desc ti_rx_return_ring[TI_RETURN_RING_CNT]; 1063 struct ti_event_desc ti_event_ring[TI_EVENT_RING_CNT]; 1064 struct ti_tx_desc ti_tx_ring[TI_TX_RING_CNT]; 1065 /* 1066 * Make sure producer structures are aligned on 32-byte cache 1067 * line boundaries. 1068 */ --- 39 unchanged lines hidden (view full) --- 1108 SLIST_ENTRY(ti_mc_entry) mc_entries; 1109}; 1110 1111struct ti_jpool_entry { 1112 int slot; 1113 SLIST_ENTRY(ti_jpool_entry) jpool_entries; 1114}; 1115 | 927 struct ti_rx_desc ti_rx_mini_ring[TI_MINI_RX_RING_CNT]; 928 struct ti_rx_desc ti_rx_return_ring[TI_RETURN_RING_CNT]; 929 struct ti_event_desc ti_event_ring[TI_EVENT_RING_CNT]; 930 struct ti_tx_desc ti_tx_ring[TI_TX_RING_CNT]; 931 /* 932 * Make sure producer structures are aligned on 32-byte cache 933 * line boundaries. 934 */ --- 39 unchanged lines hidden (view full) --- 974 SLIST_ENTRY(ti_mc_entry) mc_entries; 975}; 976 977struct ti_jpool_entry { 978 int slot; 979 SLIST_ENTRY(ti_jpool_entry) jpool_entries; 980}; 981 |
| 982typedef enum { 983 TI_FLAG_NONE = 0x00, 984 TI_FLAG_DEBUGING = 0x01, 985 TI_FLAG_WAIT_FOR_LINK = 0x02 986} ti_flag_vals; 987 |
|
| 1116struct ti_softc { | 988struct ti_softc { |
| 989 STAILQ_ENTRY(ti_softc) ti_links; |
|
| 1117 struct arpcom arpcom; /* interface info */ 1118 bus_space_handle_t ti_bhandle; 1119 vm_offset_t ti_vhandle; 1120 bus_space_tag_t ti_btag; 1121 void *ti_intrhand; 1122 struct resource *ti_irq; 1123 struct resource *ti_res; 1124 struct ifmedia ifmedia; /* media info */ 1125 u_int8_t ti_unit; /* interface number */ 1126 u_int8_t ti_hwrev; /* Tigon rev (1 or 2) */ 1127 u_int8_t ti_copper; /* 1000baseTX card */ 1128 u_int8_t ti_linkstat; /* Link state */ | 990 struct arpcom arpcom; /* interface info */ 991 bus_space_handle_t ti_bhandle; 992 vm_offset_t ti_vhandle; 993 bus_space_tag_t ti_btag; 994 void *ti_intrhand; 995 struct resource *ti_irq; 996 struct resource *ti_res; 997 struct ifmedia ifmedia; /* media info */ 998 u_int8_t ti_unit; /* interface number */ 999 u_int8_t ti_hwrev; /* Tigon rev (1 or 2) */ 1000 u_int8_t ti_copper; /* 1000baseTX card */ 1001 u_int8_t ti_linkstat; /* Link state */ |
| 1002 int ti_hdrsplit; /* enable header splitting */ |
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| 1129 struct ti_ring_data *ti_rdata; /* rings */ 1130 struct ti_chain_data ti_cdata; /* mbufs */ 1131#define ti_ev_prodidx ti_rdata->ti_ev_prodidx_r 1132#define ti_return_prodidx ti_rdata->ti_return_prodidx_r 1133#define ti_tx_considx ti_rdata->ti_tx_considx_r 1134 u_int16_t ti_tx_saved_considx; 1135 u_int16_t ti_rx_saved_considx; 1136 u_int16_t ti_ev_saved_considx; --- 8 unchanged lines hidden (view full) --- 1145 u_int32_t ti_rx_coal_ticks; 1146 u_int32_t ti_tx_coal_ticks; 1147 u_int32_t ti_rx_max_coal_bds; 1148 u_int32_t ti_tx_max_coal_bds; 1149 u_int32_t ti_tx_buf_ratio; 1150 int ti_if_flags; 1151 int ti_txcnt; 1152 struct mtx ti_mtx; | 1003 struct ti_ring_data *ti_rdata; /* rings */ 1004 struct ti_chain_data ti_cdata; /* mbufs */ 1005#define ti_ev_prodidx ti_rdata->ti_ev_prodidx_r 1006#define ti_return_prodidx ti_rdata->ti_return_prodidx_r 1007#define ti_tx_considx ti_rdata->ti_tx_considx_r 1008 u_int16_t ti_tx_saved_considx; 1009 u_int16_t ti_rx_saved_considx; 1010 u_int16_t ti_ev_saved_considx; --- 8 unchanged lines hidden (view full) --- 1019 u_int32_t ti_rx_coal_ticks; 1020 u_int32_t ti_tx_coal_ticks; 1021 u_int32_t ti_rx_max_coal_bds; 1022 u_int32_t ti_tx_max_coal_bds; 1023 u_int32_t ti_tx_buf_ratio; 1024 int ti_if_flags; 1025 int ti_txcnt; 1026 struct mtx ti_mtx; |
| 1027 ti_flag_vals ti_flags; 1028 dev_t dev; |
|
| 1153}; 1154 1155#define TI_LOCK(_sc) mtx_lock(&(_sc)->ti_mtx) 1156#define TI_UNLOCK(_sc) mtx_unlock(&(_sc)->ti_mtx) 1157 1158/* 1159 * Microchip Technology 24Cxx EEPROM control bytes 1160 */ --- 31 unchanged lines hidden --- | 1029}; 1030 1031#define TI_LOCK(_sc) mtx_lock(&(_sc)->ti_mtx) 1032#define TI_UNLOCK(_sc) mtx_unlock(&(_sc)->ti_mtx) 1033 1034/* 1035 * Microchip Technology 24Cxx EEPROM control bytes 1036 */ --- 31 unchanged lines hidden --- |