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1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/dev/ti/if_ti.c 64139 2000-08-02 18:49:17Z wpaul $
33 */
34
35/*
36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
37 * Manuals, sample driver and firmware source kits are available
38 * from http://www.alteon.com/support/openkits.
39 *
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Electrical Engineering Department
42 * Columbia University, New York City
43 */
44
45/*
46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
50 * filtering and jumbo (9014 byte) frames. The hardware is largely
51 * controlled by firmware, which must be loaded into the NIC during
52 * initialization.
53 *
54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
55 * revision, which supports new features such as extended commands,
56 * extended jumbo receive ring desciptors and a mini receive ring.
57 *
58 * Alteon Networks is to be commended for releasing such a vast amount
59 * of development material for the Tigon NIC without requiring an NDA
60 * (although they really should have done it a long time ago). With
61 * any luck, the other vendors will finally wise up and follow Alteon's
62 * stellar example.
63 *
64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
65 * this driver by #including it as a C header file. This bloats the
66 * driver somewhat, but it's the easiest method considering that the
67 * driver code and firmware code need to be kept in sync. The source
68 * for the firmware is not provided with the FreeBSD distribution since
69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
70 *
71 * The following people deserve special thanks:
72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
73 * for testing
74 * - Raymond Lee of Netgear, for providing a pair of Netgear
75 * GA620 Tigon 2 boards for testing
76 * - Ulf Zimmermann, for bringing the GA260 to my attention and
77 * convincing me to write this driver.
78 * - Andrew Gallatin for providing FreeBSD/Alpha support.
79 */
80
81#include "vlan.h"
82
83#include <sys/param.h>
84#include <sys/systm.h>
85#include <sys/sockio.h>
86#include <sys/mbuf.h>
87#include <sys/malloc.h>
88#include <sys/kernel.h>
89#include <sys/socket.h>
90#include <sys/queue.h>
91
92#include <net/if.h>
93#include <net/if_arp.h>
94#include <net/ethernet.h>
95#include <net/if_dl.h>
96#include <net/if_media.h>
97
98#include <net/bpf.h>
99
100#if NVLAN > 0
101#include <net/if_types.h>
102#include <net/if_vlan_var.h>
103#endif
104
105#include <netinet/in_systm.h>
106#include <netinet/in.h>
107#include <netinet/ip.h>
108
109#include <vm/vm.h> /* for vtophys */
110#include <vm/pmap.h> /* for vtophys */
111#include <machine/clock.h> /* for DELAY */
112#include <machine/bus_memio.h>
113#include <machine/bus.h>
114#include <machine/resource.h>
115#include <sys/bus.h>
116#include <sys/rman.h>
117
118#include <pci/pcireg.h>
119#include <pci/pcivar.h>
120
121#include <pci/if_tireg.h>
122#include <pci/ti_fw.h>
123#include <pci/ti_fw2.h>
124
125#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
126
127#if !defined(lint)
128static const char rcsid[] =
129 "$FreeBSD: head/sys/dev/ti/if_ti.c 64139 2000-08-02 18:49:17Z wpaul $";
130#endif
131
132/*
133 * Various supported device vendors/types and their names.
134 */
135
136static struct ti_type ti_devs[] = {
137 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
138 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
139 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
140 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
141 { TC_VENDORID, TC_DEVICEID_3C985,
142 "3Com 3c985-SX Gigabit Ethernet" },
143 { NG_VENDORID, NG_DEVICEID_GA620,
144 "Netgear GA620 1000baseSX Gigabit Ethernet" },
145 { NG_VENDORID, NG_DEVICEID_GA620T,
146 "Netgear GA620 1000baseT Gigabit Ethernet" },
147 { SGI_VENDORID, SGI_DEVICEID_TIGON,
148 "Silicon Graphics Gigabit Ethernet" },
149 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
150 "Farallon PN9000SX Gigabit Ethernet" },
151 { 0, 0, NULL }
152};
153
154static int ti_probe __P((device_t));
155static int ti_attach __P((device_t));
156static int ti_detach __P((device_t));
157static void ti_txeof __P((struct ti_softc *));
158static void ti_rxeof __P((struct ti_softc *));
159
160static void ti_stats_update __P((struct ti_softc *));
161static int ti_encap __P((struct ti_softc *, struct mbuf *,
162 u_int32_t *));
163
164static void ti_intr __P((void *));
165static void ti_start __P((struct ifnet *));
166static int ti_ioctl __P((struct ifnet *, u_long, caddr_t));
167static void ti_init __P((void *));
168static void ti_init2 __P((struct ti_softc *));
169static void ti_stop __P((struct ti_softc *));
170static void ti_watchdog __P((struct ifnet *));
171static void ti_shutdown __P((device_t));
172static int ti_ifmedia_upd __P((struct ifnet *));
173static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
174
175static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int));
176static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *,
177 int, u_int8_t *));
178static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int));
179
180static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *));
181static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *));
182static void ti_setmulti __P((struct ti_softc *));
183
184static void ti_mem __P((struct ti_softc *, u_int32_t,
185 u_int32_t, caddr_t));
186static void ti_loadfw __P((struct ti_softc *));
187static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *));
188static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *,
189 caddr_t, int));
190static void ti_handle_events __P((struct ti_softc *));
191static int ti_alloc_jumbo_mem __P((struct ti_softc *));
192static void *ti_jalloc __P((struct ti_softc *));
193static void ti_jfree __P((caddr_t, u_int));
194static void ti_jref __P((caddr_t, u_int));
195static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *));
196static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *));
197static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *));
198static int ti_init_rx_ring_std __P((struct ti_softc *));
199static void ti_free_rx_ring_std __P((struct ti_softc *));
200static int ti_init_rx_ring_jumbo __P((struct ti_softc *));
201static void ti_free_rx_ring_jumbo __P((struct ti_softc *));
202static int ti_init_rx_ring_mini __P((struct ti_softc *));
203static void ti_free_rx_ring_mini __P((struct ti_softc *));
204static void ti_free_tx_ring __P((struct ti_softc *));
205static int ti_init_tx_ring __P((struct ti_softc *));
206
207static int ti_64bitslot_war __P((struct ti_softc *));
208static int ti_chipinit __P((struct ti_softc *));
209static int ti_gibinit __P((struct ti_softc *));
210
211static device_method_t ti_methods[] = {
212 /* Device interface */
213 DEVMETHOD(device_probe, ti_probe),
214 DEVMETHOD(device_attach, ti_attach),
215 DEVMETHOD(device_detach, ti_detach),
216 DEVMETHOD(device_shutdown, ti_shutdown),
217 { 0, 0 }
218};
219
220static driver_t ti_driver = {
221 "ti",
222 ti_methods,
223 sizeof(struct ti_softc)
224};
225
226static devclass_t ti_devclass;
227
228DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0);
229
230/*
231 * Send an instruction or address to the EEPROM, check for ACK.
232 */
233static u_int32_t ti_eeprom_putbyte(sc, byte)
234 struct ti_softc *sc;
235 int byte;
236{
237 register int i, ack = 0;
238
239 /*
240 * Make sure we're in TX mode.
241 */
242 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
243
244 /*
245 * Feed in each bit and stobe the clock.
246 */
247 for (i = 0x80; i; i >>= 1) {
248 if (byte & i) {
249 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
250 } else {
251 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
252 }
253 DELAY(1);
254 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
255 DELAY(1);
256 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
257 }
258
259 /*
260 * Turn off TX mode.
261 */
262 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
263
264 /*
265 * Check for ack.
266 */
267 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
268 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
269 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
270
271 return(ack);
272}
273
274/*
275 * Read a byte of data stored in the EEPROM at address 'addr.'
276 * We have to send two address bytes since the EEPROM can hold
277 * more than 256 bytes of data.
278 */
279static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
280 struct ti_softc *sc;
281 int addr;
282 u_int8_t *dest;
283{
284 register int i;
285 u_int8_t byte = 0;
286
287 EEPROM_START;
288
289 /*
290 * Send write control code to EEPROM.
291 */
292 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
293 printf("ti%d: failed to send write command, status: %x\n",
294 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
295 return(1);
296 }
297
298 /*
299 * Send first byte of address of byte we want to read.
300 */
301 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
302 printf("ti%d: failed to send address, status: %x\n",
303 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
304 return(1);
305 }
306 /*
307 * Send second byte address of byte we want to read.
308 */
309 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
310 printf("ti%d: failed to send address, status: %x\n",
311 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
312 return(1);
313 }
314
315 EEPROM_STOP;
316 EEPROM_START;
317 /*
318 * Send read control code to EEPROM.
319 */
320 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
321 printf("ti%d: failed to send read command, status: %x\n",
322 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
323 return(1);
324 }
325
326 /*
327 * Start reading bits from EEPROM.
328 */
329 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
330 for (i = 0x80; i; i >>= 1) {
331 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
332 DELAY(1);
333 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
334 byte |= i;
335 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
336 DELAY(1);
337 }
338
339 EEPROM_STOP;
340
341 /*
342 * No ACK generated for read, so just return byte.
343 */
344
345 *dest = byte;
346
347 return(0);
348}
349
350/*
351 * Read a sequence of bytes from the EEPROM.
352 */
353static int ti_read_eeprom(sc, dest, off, cnt)
354 struct ti_softc *sc;
355 caddr_t dest;
356 int off;
357 int cnt;
358{
359 int err = 0, i;
360 u_int8_t byte = 0;
361
362 for (i = 0; i < cnt; i++) {
363 err = ti_eeprom_getbyte(sc, off + i, &byte);
364 if (err)
365 break;
366 *(dest + i) = byte;
367 }
368
369 return(err ? 1 : 0);
370}
371
372/*
373 * NIC memory access function. Can be used to either clear a section
374 * of NIC local memory or (if buf is non-NULL) copy data into it.
375 */
376static void ti_mem(sc, addr, len, buf)
377 struct ti_softc *sc;
378 u_int32_t addr, len;
379 caddr_t buf;
380{
381 int segptr, segsize, cnt;
382 caddr_t ti_winbase, ptr;
383
384 segptr = addr;
385 cnt = len;
386 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
387 ptr = buf;
388
389 while(cnt) {
390 if (cnt < TI_WINLEN)
391 segsize = cnt;
392 else
393 segsize = TI_WINLEN - (segptr % TI_WINLEN);
394 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
395 if (buf == NULL)
396 bzero((char *)ti_winbase + (segptr &
397 (TI_WINLEN - 1)), segsize);
398 else {
399 bcopy((char *)ptr, (char *)ti_winbase +
400 (segptr & (TI_WINLEN - 1)), segsize);
401 ptr += segsize;
402 }
403 segptr += segsize;
404 cnt -= segsize;
405 }
406
407 return;
408}
409
410/*
411 * Load firmware image into the NIC. Check that the firmware revision
412 * is acceptable and see if we want the firmware for the Tigon 1 or
413 * Tigon 2.
414 */
415static void ti_loadfw(sc)
416 struct ti_softc *sc;
417{
418 switch(sc->ti_hwrev) {
419 case TI_HWREV_TIGON:
420 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
421 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
422 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
423 printf("ti%d: firmware revision mismatch; want "
424 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
425 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
426 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
427 tigonFwReleaseMinor, tigonFwReleaseFix);
428 return;
429 }
430 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
431 (caddr_t)tigonFwText);
432 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
433 (caddr_t)tigonFwData);
434 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
435 (caddr_t)tigonFwRodata);
436 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
437 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
438 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
439 break;
440 case TI_HWREV_TIGON_II:
441 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
442 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
443 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
444 printf("ti%d: firmware revision mismatch; want "
445 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
446 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
447 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
448 tigon2FwReleaseMinor, tigon2FwReleaseFix);
449 return;
450 }
451 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
452 (caddr_t)tigon2FwText);
453 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
454 (caddr_t)tigon2FwData);
455 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
456 (caddr_t)tigon2FwRodata);
457 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
458 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
459 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
460 break;
461 default:
462 printf("ti%d: can't load firmware: unknown hardware rev\n",
463 sc->ti_unit);
464 break;
465 }
466
467 return;
468}
469
470/*
471 * Send the NIC a command via the command ring.
472 */
473static void ti_cmd(sc, cmd)
474 struct ti_softc *sc;
475 struct ti_cmd_desc *cmd;
476{
477 u_int32_t index;
478
479 if (sc->ti_rdata->ti_cmd_ring == NULL)
480 return;
481
482 index = sc->ti_cmd_saved_prodidx;
483 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
484 TI_INC(index, TI_CMD_RING_CNT);
485 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
486 sc->ti_cmd_saved_prodidx = index;
487
488 return;
489}
490
491/*
492 * Send the NIC an extended command. The 'len' parameter specifies the
493 * number of command slots to include after the initial command.
494 */
495static void ti_cmd_ext(sc, cmd, arg, len)
496 struct ti_softc *sc;
497 struct ti_cmd_desc *cmd;
498 caddr_t arg;
499 int len;
500{
501 u_int32_t index;
502 register int i;
503
504 if (sc->ti_rdata->ti_cmd_ring == NULL)
505 return;
506
507 index = sc->ti_cmd_saved_prodidx;
508 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
509 TI_INC(index, TI_CMD_RING_CNT);
510 for (i = 0; i < len; i++) {
511 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
512 *(u_int32_t *)(&arg[i * 4]));
513 TI_INC(index, TI_CMD_RING_CNT);
514 }
515 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
516 sc->ti_cmd_saved_prodidx = index;
517
518 return;
519}
520
521/*
522 * Handle events that have triggered interrupts.
523 */
524static void ti_handle_events(sc)
525 struct ti_softc *sc;
526{
527 struct ti_event_desc *e;
528
529 if (sc->ti_rdata->ti_event_ring == NULL)
530 return;
531
532 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
533 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
534 switch(e->ti_event) {
535 case TI_EV_LINKSTAT_CHANGED:
536 sc->ti_linkstat = e->ti_code;
537 if (e->ti_code == TI_EV_CODE_LINK_UP)
538 printf("ti%d: 10/100 link up\n", sc->ti_unit);
539 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
540 printf("ti%d: gigabit link up\n", sc->ti_unit);
541 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
542 printf("ti%d: link down\n", sc->ti_unit);
543 break;
544 case TI_EV_ERROR:
545 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
546 printf("ti%d: invalid command\n", sc->ti_unit);
547 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
548 printf("ti%d: unknown command\n", sc->ti_unit);
549 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
550 printf("ti%d: bad config data\n", sc->ti_unit);
551 break;
552 case TI_EV_FIRMWARE_UP:
553 ti_init2(sc);
554 break;
555 case TI_EV_STATS_UPDATED:
556 ti_stats_update(sc);
557 break;
558 case TI_EV_RESET_JUMBO_RING:
559 case TI_EV_MCAST_UPDATED:
560 /* Who cares. */
561 break;
562 default:
563 printf("ti%d: unknown event: %d\n",
564 sc->ti_unit, e->ti_event);
565 break;
566 }
567 /* Advance the consumer index. */
568 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
569 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
570 }
571
572 return;
573}
574
575/*
576 * Memory management for the jumbo receive ring is a pain in the
577 * butt. We need to allocate at least 9018 bytes of space per frame,
578 * _and_ it has to be contiguous (unless you use the extended
579 * jumbo descriptor format). Using malloc() all the time won't
580 * work: malloc() allocates memory in powers of two, which means we
581 * would end up wasting a considerable amount of space by allocating
582 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
583 * to do our own memory management.
584 *
585 * The driver needs to allocate a contiguous chunk of memory at boot
586 * time. We then chop this up ourselves into 9K pieces and use them
587 * as external mbuf storage.
588 *
589 * One issue here is how much memory to allocate. The jumbo ring has
590 * 256 slots in it, but at 9K per slot than can consume over 2MB of
591 * RAM. This is a bit much, especially considering we also need
592 * RAM for the standard ring and mini ring (on the Tigon 2). To
593 * save space, we only actually allocate enough memory for 64 slots
594 * by default, which works out to between 500 and 600K. This can
595 * be tuned by changing a #define in if_tireg.h.
596 */
597
598static int ti_alloc_jumbo_mem(sc)
599 struct ti_softc *sc;
600{
601 caddr_t ptr;
602 register int i;
603 struct ti_jpool_entry *entry;
604
605 /* Grab a big chunk o' storage. */
606 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
607 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
608
609 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
610 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
611 return(ENOBUFS);
612 }
613
614 SLIST_INIT(&sc->ti_jfree_listhead);
615 SLIST_INIT(&sc->ti_jinuse_listhead);
616
617 /*
618 * Now divide it up into 9K pieces and save the addresses
619 * in an array. Note that we play an evil trick here by using
620 * the first few bytes in the buffer to hold the the address
621 * of the softc structure for this interface. This is because
622 * ti_jfree() needs it, but it is called by the mbuf management
623 * code which will not pass it to us explicitly.
624 */
625 ptr = sc->ti_cdata.ti_jumbo_buf;
626 for (i = 0; i < TI_JSLOTS; i++) {
627 u_int64_t **aptr;
628 aptr = (u_int64_t **)ptr;
629 aptr[0] = (u_int64_t *)sc;
630 ptr += sizeof(u_int64_t);
631 sc->ti_cdata.ti_jslots[i].ti_buf = ptr;
632 sc->ti_cdata.ti_jslots[i].ti_inuse = 0;
633 ptr += (TI_JLEN - sizeof(u_int64_t));
634 entry = malloc(sizeof(struct ti_jpool_entry),
635 M_DEVBUF, M_NOWAIT);
636 if (entry == NULL) {
637 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
638 M_DEVBUF);
639 sc->ti_cdata.ti_jumbo_buf = NULL;
640 printf("ti%d: no memory for jumbo "
641 "buffer queue!\n", sc->ti_unit);
642 return(ENOBUFS);
643 }
644 entry->slot = i;
645 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
646 }
647
648 return(0);
649}
650
651/*
652 * Allocate a jumbo buffer.
653 */
654static void *ti_jalloc(sc)
655 struct ti_softc *sc;
656{
657 struct ti_jpool_entry *entry;
658
659 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
660
661 if (entry == NULL) {
662 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
663 return(NULL);
664 }
665
666 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
667 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
668 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1;
669 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf);
670}
671
672/*
673 * Adjust usage count on a jumbo buffer. In general this doesn't
674 * get used much because our jumbo buffers don't get passed around
675 * too much, but it's implemented for correctness.
676 */
677static void ti_jref(buf, size)
678 caddr_t buf;
679 u_int size;
680{
681 struct ti_softc *sc;
682 u_int64_t **aptr;
683 register int i;
684
685 /* Extract the softc struct pointer. */
686 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
687 sc = (struct ti_softc *)(aptr[0]);
688
689 if (sc == NULL)
690 panic("ti_jref: can't find softc pointer!");
691
692 if (size != TI_JUMBO_FRAMELEN)
693 panic("ti_jref: adjusting refcount of buf of wrong size!");
694
695 /* calculate the slot this buffer belongs to */
696
697 i = ((vm_offset_t)aptr
698 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
699
700 if ((i < 0) || (i >= TI_JSLOTS))
701 panic("ti_jref: asked to reference buffer "
702 "that we don't manage!");
703 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
704 panic("ti_jref: buffer already free!");
705 else
706 sc->ti_cdata.ti_jslots[i].ti_inuse++;
707
708 return;
709}
710
711/*
712 * Release a jumbo buffer.
713 */
714static void ti_jfree(buf, size)
715 caddr_t buf;
716 u_int size;
717{
718 struct ti_softc *sc;
719 u_int64_t **aptr;
720 int i;
721 struct ti_jpool_entry *entry;
722
723 /* Extract the softc struct pointer. */
724 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
725 sc = (struct ti_softc *)(aptr[0]);
726
727 if (sc == NULL)
728 panic("ti_jfree: can't find softc pointer!");
729
730 if (size != TI_JUMBO_FRAMELEN)
731 panic("ti_jfree: freeing buffer of wrong size!");
732
733 /* calculate the slot this buffer belongs to */
734
735 i = ((vm_offset_t)aptr
736 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
737
738 if ((i < 0) || (i >= TI_JSLOTS))
739 panic("ti_jfree: asked to free buffer that we don't manage!");
740 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0)
741 panic("ti_jfree: buffer already free!");
742 else {
743 sc->ti_cdata.ti_jslots[i].ti_inuse--;
744 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) {
745 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
746 if (entry == NULL)
747 panic("ti_jfree: buffer not in use!");
748 entry->slot = i;
749 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead,
750 jpool_entries);
751 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead,
752 entry, jpool_entries);
753 }
754 }
755
756 return;
757}
758
759
760/*
761 * Intialize a standard receive ring descriptor.
762 */
763static int ti_newbuf_std(sc, i, m)
764 struct ti_softc *sc;
765 int i;
766 struct mbuf *m;
767{
768 struct mbuf *m_new = NULL;
769 struct ti_rx_desc *r;
770
771 if (m == NULL) {
772 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
773 if (m_new == NULL) {
774 printf("ti%d: mbuf allocation failed "
775 "-- packet dropped!\n", sc->ti_unit);
776 return(ENOBUFS);
777 }
778
779 MCLGET(m_new, M_DONTWAIT);
780 if (!(m_new->m_flags & M_EXT)) {
781 printf("ti%d: cluster allocation failed "
782 "-- packet dropped!\n", sc->ti_unit);
783 m_freem(m_new);
784 return(ENOBUFS);
785 }
786 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
787 } else {
788 m_new = m;
789 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
790 m_new->m_data = m_new->m_ext.ext_buf;
791 }
792
793 m_adj(m_new, ETHER_ALIGN);
794 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
795 r = &sc->ti_rdata->ti_rx_std_ring[i];
796 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
797 r->ti_type = TI_BDTYPE_RECV_BD;
798 r->ti_flags = 0;
799 if (sc->arpcom.ac_if.if_hwassist)
800 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
801 r->ti_len = m_new->m_len;
802 r->ti_idx = i;
803
804 return(0);
805}
806
807/*
808 * Intialize a mini receive ring descriptor. This only applies to
809 * the Tigon 2.
810 */
811static int ti_newbuf_mini(sc, i, m)
812 struct ti_softc *sc;
813 int i;
814 struct mbuf *m;
815{
816 struct mbuf *m_new = NULL;
817 struct ti_rx_desc *r;
818
819 if (m == NULL) {
820 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
821 if (m_new == NULL) {
822 printf("ti%d: mbuf allocation failed "
823 "-- packet dropped!\n", sc->ti_unit);
824 return(ENOBUFS);
825 }
826 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
827 } else {
828 m_new = m;
829 m_new->m_data = m_new->m_pktdat;
830 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
831 }
832
833 m_adj(m_new, ETHER_ALIGN);
834 r = &sc->ti_rdata->ti_rx_mini_ring[i];
835 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
836 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
837 r->ti_type = TI_BDTYPE_RECV_BD;
838 r->ti_flags = TI_BDFLAG_MINI_RING;
839 if (sc->arpcom.ac_if.if_hwassist)
840 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
841 r->ti_len = m_new->m_len;
842 r->ti_idx = i;
843
844 return(0);
845}
846
847/*
848 * Initialize a jumbo receive ring descriptor. This allocates
849 * a jumbo buffer from the pool managed internally by the driver.
850 */
851static int ti_newbuf_jumbo(sc, i, m)
852 struct ti_softc *sc;
853 int i;
854 struct mbuf *m;
855{
856 struct mbuf *m_new = NULL;
857 struct ti_rx_desc *r;
858
859 if (m == NULL) {
860 caddr_t *buf = NULL;
861
862 /* Allocate the mbuf. */
863 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
864 if (m_new == NULL) {
865 printf("ti%d: mbuf allocation failed "
866 "-- packet dropped!\n", sc->ti_unit);
867 return(ENOBUFS);
868 }
869
870 /* Allocate the jumbo buffer */
871 buf = ti_jalloc(sc);
872 if (buf == NULL) {
873 m_freem(m_new);
874 printf("ti%d: jumbo allocation failed "
875 "-- packet dropped!\n", sc->ti_unit);
876 return(ENOBUFS);
877 }
878
879 /* Attach the buffer to the mbuf. */
880 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
881 m_new->m_flags |= M_EXT;
882 m_new->m_len = m_new->m_pkthdr.len =
883 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
884 m_new->m_ext.ext_free = ti_jfree;
885 m_new->m_ext.ext_ref = ti_jref;
886 } else {
887 m_new = m;
888 m_new->m_data = m_new->m_ext.ext_buf;
889 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
890 }
891
892 m_adj(m_new, ETHER_ALIGN);
893 /* Set up the descriptor. */
894 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
895 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
896 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
897 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
898 r->ti_flags = TI_BDFLAG_JUMBO_RING;
899 if (sc->arpcom.ac_if.if_hwassist)
900 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
901 r->ti_len = m_new->m_len;
902 r->ti_idx = i;
903
904 return(0);
905}
906
907/*
908 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
909 * that's 1MB or memory, which is a lot. For now, we fill only the first
910 * 256 ring entries and hope that our CPU is fast enough to keep up with
911 * the NIC.
912 */
913static int ti_init_rx_ring_std(sc)
914 struct ti_softc *sc;
915{
916 register int i;
917 struct ti_cmd_desc cmd;
918
919 for (i = 0; i < TI_SSLOTS; i++) {
920 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
921 return(ENOBUFS);
922 };
923
924 TI_UPDATE_STDPROD(sc, i - 1);
925 sc->ti_std = i - 1;
926
927 return(0);
928}
929
930static void ti_free_rx_ring_std(sc)
931 struct ti_softc *sc;
932{
933 register int i;
934
935 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
936 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
937 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
938 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
939 }
940 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
941 sizeof(struct ti_rx_desc));
942 }
943
944 return;
945}
946
947static int ti_init_rx_ring_jumbo(sc)
948 struct ti_softc *sc;
949{
950 register int i;
951 struct ti_cmd_desc cmd;
952
953 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
954 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
955 return(ENOBUFS);
956 };
957
958 TI_UPDATE_JUMBOPROD(sc, i - 1);
959 sc->ti_jumbo = i - 1;
960
961 return(0);
962}
963
964static void ti_free_rx_ring_jumbo(sc)
965 struct ti_softc *sc;
966{
967 register int i;
968
969 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
970 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
971 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
972 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
973 }
974 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
975 sizeof(struct ti_rx_desc));
976 }
977
978 return;
979}
980
981static int ti_init_rx_ring_mini(sc)
982 struct ti_softc *sc;
983{
984 register int i;
985
986 for (i = 0; i < TI_MSLOTS; i++) {
987 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
988 return(ENOBUFS);
989 };
990
991 TI_UPDATE_MINIPROD(sc, i - 1);
992 sc->ti_mini = i - 1;
993
994 return(0);
995}
996
997static void ti_free_rx_ring_mini(sc)
998 struct ti_softc *sc;
999{
1000 register int i;
1001
1002 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
1003 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
1004 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
1005 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
1006 }
1007 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
1008 sizeof(struct ti_rx_desc));
1009 }
1010
1011 return;
1012}
1013
1014static void ti_free_tx_ring(sc)
1015 struct ti_softc *sc;
1016{
1017 register int i;
1018
1019 if (sc->ti_rdata->ti_tx_ring == NULL)
1020 return;
1021
1022 for (i = 0; i < TI_TX_RING_CNT; i++) {
1023 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1024 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1025 sc->ti_cdata.ti_tx_chain[i] = NULL;
1026 }
1027 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
1028 sizeof(struct ti_tx_desc));
1029 }
1030
1031 return;
1032}
1033
1034static int ti_init_tx_ring(sc)
1035 struct ti_softc *sc;
1036{
1037 sc->ti_txcnt = 0;
1038 sc->ti_tx_saved_considx = 0;
1039 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1040 return(0);
1041}
1042
1043/*
1044 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1045 * but we have to support the old way too so that Tigon 1 cards will
1046 * work.
1047 */
1048void ti_add_mcast(sc, addr)
1049 struct ti_softc *sc;
1050 struct ether_addr *addr;
1051{
1052 struct ti_cmd_desc cmd;
1053 u_int16_t *m;
1054 u_int32_t ext[2] = {0, 0};
1055
1056 m = (u_int16_t *)&addr->octet[0];
1057
1058 switch(sc->ti_hwrev) {
1059 case TI_HWREV_TIGON:
1060 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1061 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1062 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1063 break;
1064 case TI_HWREV_TIGON_II:
1065 ext[0] = htons(m[0]);
1066 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1067 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
1068 break;
1069 default:
1070 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1071 break;
1072 }
1073
1074 return;
1075}
1076
1077void ti_del_mcast(sc, addr)
1078 struct ti_softc *sc;
1079 struct ether_addr *addr;
1080{
1081 struct ti_cmd_desc cmd;
1082 u_int16_t *m;
1083 u_int32_t ext[2] = {0, 0};
1084
1085 m = (u_int16_t *)&addr->octet[0];
1086
1087 switch(sc->ti_hwrev) {
1088 case TI_HWREV_TIGON:
1089 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1090 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1091 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1092 break;
1093 case TI_HWREV_TIGON_II:
1094 ext[0] = htons(m[0]);
1095 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1096 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1097 break;
1098 default:
1099 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1100 break;
1101 }
1102
1103 return;
1104}
1105
1106/*
1107 * Configure the Tigon's multicast address filter.
1108 *
1109 * The actual multicast table management is a bit of a pain, thanks to
1110 * slight brain damage on the part of both Alteon and us. With our
1111 * multicast code, we are only alerted when the multicast address table
1112 * changes and at that point we only have the current list of addresses:
1113 * we only know the current state, not the previous state, so we don't
1114 * actually know what addresses were removed or added. The firmware has
1115 * state, but we can't get our grubby mits on it, and there is no 'delete
1116 * all multicast addresses' command. Hence, we have to maintain our own
1117 * state so we know what addresses have been programmed into the NIC at
1118 * any given time.
1119 */
1120static void ti_setmulti(sc)
1121 struct ti_softc *sc;
1122{
1123 struct ifnet *ifp;
1124 struct ifmultiaddr *ifma;
1125 struct ti_cmd_desc cmd;
1126 struct ti_mc_entry *mc;
1127 u_int32_t intrs;
1128
1129 ifp = &sc->arpcom.ac_if;
1130
1131 if (ifp->if_flags & IFF_ALLMULTI) {
1132 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1133 return;
1134 } else {
1135 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1136 }
1137
1138 /* Disable interrupts. */
1139 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1140 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1141
1142 /* First, zot all the existing filters. */
1143 while (sc->ti_mc_listhead.slh_first != NULL) {
1144 mc = sc->ti_mc_listhead.slh_first;
1145 ti_del_mcast(sc, &mc->mc_addr);
1146 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1147 free(mc, M_DEVBUF);
1148 }
1149
1150 /* Now program new ones. */
1151 for (ifma = ifp->if_multiaddrs.lh_first;
1152 ifma != NULL; ifma = ifma->ifma_link.le_next) {
1153 if (ifma->ifma_addr->sa_family != AF_LINK)
1154 continue;
1155 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1156 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1157 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1158 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1159 ti_add_mcast(sc, &mc->mc_addr);
1160 }
1161
1162 /* Re-enable interrupts. */
1163 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1164
1165 return;
1166}
1167
1168/*
1169 * Check to see if the BIOS has configured us for a 64 bit slot when
1170 * we aren't actually in one. If we detect this condition, we can work
1171 * around it on the Tigon 2 by setting a bit in the PCI state register,
1172 * but for the Tigon 1 we must give up and abort the interface attach.
1173 */
1174static int ti_64bitslot_war(sc)
1175 struct ti_softc *sc;
1176{
1177 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1178 CSR_WRITE_4(sc, 0x600, 0);
1179 CSR_WRITE_4(sc, 0x604, 0);
1180 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1181 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1182 if (sc->ti_hwrev == TI_HWREV_TIGON)
1183 return(EINVAL);
1184 else {
1185 TI_SETBIT(sc, TI_PCI_STATE,
1186 TI_PCISTATE_32BIT_BUS);
1187 return(0);
1188 }
1189 }
1190 }
1191
1192 return(0);
1193}
1194
1195/*
1196 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1197 * self-test results.
1198 */
1199static int ti_chipinit(sc)
1200 struct ti_softc *sc;
1201{
1202 u_int32_t cacheline;
1203 u_int32_t pci_writemax = 0;
1204
1205 /* Initialize link to down state. */
1206 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1207
1208 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES;
1209
1210 /* Set endianness before we access any non-PCI registers. */
1211#if BYTE_ORDER == BIG_ENDIAN
1212 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1213 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1214#else
1215 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1216 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1217#endif
1218
1219 /* Check the ROM failed bit to see if self-tests passed. */
1220 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1221 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1222 return(ENODEV);
1223 }
1224
1225 /* Halt the CPU. */
1226 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1227
1228 /* Figure out the hardware revision. */
1229 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1230 case TI_REV_TIGON_I:
1231 sc->ti_hwrev = TI_HWREV_TIGON;
1232 break;
1233 case TI_REV_TIGON_II:
1234 sc->ti_hwrev = TI_HWREV_TIGON_II;
1235 break;
1236 default:
1237 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1238 return(ENODEV);
1239 }
1240
1241 /* Do special setup for Tigon 2. */
1242 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1243 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1244 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K);
1245 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1246 }
1247
1248 /* Set up the PCI state register. */
1249 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1250 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1251 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1252 }
1253
1254 /* Clear the read/write max DMA parameters. */
1255 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1256 TI_PCISTATE_READ_MAXDMA));
1257
1258 /* Get cache line size. */
1259 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1260
1261 /*
1262 * If the system has set enabled the PCI memory write
1263 * and invalidate command in the command register, set
1264 * the write max parameter accordingly. This is necessary
1265 * to use MWI with the Tigon 2.
1266 */
1267 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1268 switch(cacheline) {
1269 case 1:
1270 case 4:
1271 case 8:
1272 case 16:
1273 case 32:
1274 case 64:
1275 break;
1276 default:
1277 /* Disable PCI memory write and invalidate. */
1278 if (bootverbose)
1279 printf("ti%d: cache line size %d not "
1280 "supported; disabling PCI MWI\n",
1281 sc->ti_unit, cacheline);
1282 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1283 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1284 break;
1285 }
1286 }
1287
1288#ifdef __brokenalpha__
1289 /*
1290 * From the Alteon sample driver:
1291 * Must insure that we do not cross an 8K (bytes) boundary
1292 * for DMA reads. Our highest limit is 1K bytes. This is a
1293 * restriction on some ALPHA platforms with early revision
1294 * 21174 PCI chipsets, such as the AlphaPC 164lx
1295 */
1296 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1297#else
1298 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1299#endif
1300
1301 /* This sets the min dma param all the way up (0xff). */
1302 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1303
1304 /* Configure DMA variables. */
1305#if BYTE_ORDER == BIG_ENDIAN
1306 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1307 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1308 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1309 TI_OPMODE_DONT_FRAG_JUMBO);
1310#else
1311 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1312 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1313 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1314#endif
1315
1316 /*
1317 * Only allow 1 DMA channel to be active at a time.
1318 * I don't think this is a good idea, but without it
1319 * the firmware racks up lots of nicDmaReadRingFull
1320 * errors. This is not compatible with hardware checksums.
1321 */
1322 if (sc->arpcom.ac_if.if_hwassist == 0)
1323 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1324
1325 /* Recommended settings from Tigon manual. */
1326 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1327 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1328
1329 if (ti_64bitslot_war(sc)) {
1330 printf("ti%d: bios thinks we're in a 64 bit slot, "
1331 "but we aren't", sc->ti_unit);
1332 return(EINVAL);
1333 }
1334
1335 return(0);
1336}
1337
1338/*
1339 * Initialize the general information block and firmware, and
1340 * start the CPU(s) running.
1341 */
1342static int ti_gibinit(sc)
1343 struct ti_softc *sc;
1344{
1345 struct ti_rcb *rcb;
1346 int i;
1347 struct ifnet *ifp;
1348
1349 ifp = &sc->arpcom.ac_if;
1350
1351 /* Disable interrupts for now. */
1352 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1353
1354 /* Tell the chip where to find the general information block. */
1355 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1356 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1357
1358 /* Load the firmware into SRAM. */
1359 ti_loadfw(sc);
1360
1361 /* Set up the contents of the general info and ring control blocks. */
1362
1363 /* Set up the event ring and producer pointer. */
1364 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1365
1366 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1367 rcb->ti_flags = 0;
1368 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1369 vtophys(&sc->ti_ev_prodidx);
1370 sc->ti_ev_prodidx.ti_idx = 0;
1371 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1372 sc->ti_ev_saved_considx = 0;
1373
1374 /* Set up the command ring and producer mailbox. */
1375 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1376
1377 sc->ti_rdata->ti_cmd_ring =
1378 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1379 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1380 rcb->ti_flags = 0;
1381 rcb->ti_max_len = 0;
1382 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1383 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1384 }
1385 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1386 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1387 sc->ti_cmd_saved_prodidx = 0;
1388
1389 /*
1390 * Assign the address of the stats refresh buffer.
1391 * We re-use the current stats buffer for this to
1392 * conserve memory.
1393 */
1394 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1395 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1396
1397 /* Set up the standard receive ring. */
1398 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1399 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1400 rcb->ti_max_len = TI_FRAMELEN;
1401 rcb->ti_flags = 0;
1402 if (sc->arpcom.ac_if.if_hwassist)
1403 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1404 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1405#if NVLAN > 0
1406 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1407#endif
1408
1409 /* Set up the jumbo receive ring. */
1410 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1411 TI_HOSTADDR(rcb->ti_hostaddr) =
1412 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1413 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1414 rcb->ti_flags = 0;
1415 if (sc->arpcom.ac_if.if_hwassist)
1416 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1417 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1418#if NVLAN > 0
1419 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1420#endif
1421
1422 /*
1423 * Set up the mini ring. Only activated on the
1424 * Tigon 2 but the slot in the config block is
1425 * still there on the Tigon 1.
1426 */
1427 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1428 TI_HOSTADDR(rcb->ti_hostaddr) =
1429 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
1430 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1431 if (sc->ti_hwrev == TI_HWREV_TIGON)
1432 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1433 else
1434 rcb->ti_flags = 0;
1435 if (sc->arpcom.ac_if.if_hwassist)
1436 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1437 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1438#if NVLAN > 0
1439 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1440#endif
1441
1442 /*
1443 * Set up the receive return ring.
1444 */
1445 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1446 TI_HOSTADDR(rcb->ti_hostaddr) =
1447 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1448 rcb->ti_flags = 0;
1449 rcb->ti_max_len = TI_RETURN_RING_CNT;
1450 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1451 vtophys(&sc->ti_return_prodidx);
1452
1453 /*
1454 * Set up the tx ring. Note: for the Tigon 2, we have the option
1455 * of putting the transmit ring in the host's address space and
1456 * letting the chip DMA it instead of leaving the ring in the NIC's
1457 * memory and accessing it through the shared memory region. We
1458 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1459 * so we have to revert to the shared memory scheme if we detect
1460 * a Tigon 1 chip.
1461 */
1462 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1463 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1464 sc->ti_rdata->ti_tx_ring_nic =
1465 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1466 }
1467 bzero((char *)sc->ti_rdata->ti_tx_ring,
1468 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1469 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1470 if (sc->ti_hwrev == TI_HWREV_TIGON)
1471 rcb->ti_flags = 0;
1472 else
1473 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1474#if NVLAN > 0
1475 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1476#endif
1477 if (sc->arpcom.ac_if.if_hwassist)
1478 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1479 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1480 rcb->ti_max_len = TI_TX_RING_CNT;
1481 if (sc->ti_hwrev == TI_HWREV_TIGON)
1482 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1483 else
1484 TI_HOSTADDR(rcb->ti_hostaddr) =
1485 vtophys(&sc->ti_rdata->ti_tx_ring);
1486 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1487 vtophys(&sc->ti_tx_considx);
1488
1489 /* Set up tuneables */
1490 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1491 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1492 (sc->ti_rx_coal_ticks / 10));
1493 else
1494 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1495 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1496 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1497 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1498 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1499 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1500
1501 /* Turn interrupts on. */
1502 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1503 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1504
1505 /* Start CPU. */
1506 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1507
1508 return(0);
1509}
1510
1511/*
1512 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1513 * against our list and return its name if we find a match.
1514 */
1515static int ti_probe(dev)
1516 device_t dev;
1517{
1518 struct ti_type *t;
1519
1520 t = ti_devs;
1521
1522 while(t->ti_name != NULL) {
1523 if ((pci_get_vendor(dev) == t->ti_vid) &&
1524 (pci_get_device(dev) == t->ti_did)) {
1525 device_set_desc(dev, t->ti_name);
1526 return(0);
1527 }
1528 t++;
1529 }
1530
1531 return(ENXIO);
1532}
1533
1534static int ti_attach(dev)
1535 device_t dev;
1536{
1537 int s;
1538 u_int32_t command;
1539 struct ifnet *ifp;
1540 struct ti_softc *sc;
1541 int unit, error = 0, rid;
1542
1543 s = splimp();
1544
1545 sc = device_get_softc(dev);
1546 unit = device_get_unit(dev);
1547 bzero(sc, sizeof(struct ti_softc));
1548
1549 /*
1550 * Map control/status registers.
1551 */
1552 command = pci_read_config(dev, PCIR_COMMAND, 4);
1553 command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
1554 pci_write_config(dev, PCIR_COMMAND, command, 4);
1555 command = pci_read_config(dev, PCIR_COMMAND, 4);
1556
1557 if (!(command & PCIM_CMD_MEMEN)) {
1558 printf("ti%d: failed to enable memory mapping!\n", unit);
1559 error = ENXIO;
1560 goto fail;
1561 }
1562
1563 rid = TI_PCI_LOMEM;
1564 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1565 0, ~0, 1, RF_ACTIVE);
1566
1567 if (sc->ti_res == NULL) {
1568 printf ("ti%d: couldn't map memory\n", unit);
1569 error = ENXIO;
1570 goto fail;
1571 }
1572
1573 sc->ti_btag = rman_get_bustag(sc->ti_res);
1574 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1575 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1576
1577 /*
1578 * XXX FIXME: rman_get_virtual() on the alpha is currently
1579 * broken and returns a physical address instead of a kernel
1580 * virtual address. Consequently, we need to do a little
1581 * extra mangling of the vhandle on the alpha. This should
1582 * eventually be fixed! The whole idea here is to get rid
1583 * of platform dependencies.
1584 */
1585#ifdef __alpha__
1586 if (pci_cvt_to_bwx(sc->ti_vhandle))
1587 sc->ti_vhandle = pci_cvt_to_bwx(sc->ti_vhandle);
1588 else
1589 sc->ti_vhandle = pci_cvt_to_dense(sc->ti_vhandle);
1590 sc->ti_vhandle = ALPHA_PHYS_TO_K0SEG(sc->ti_vhandle);
1591#endif
1592
1593 /* Allocate interrupt */
1594 rid = 0;
1595
1596 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1597 RF_SHAREABLE | RF_ACTIVE);
1598
1599 if (sc->ti_irq == NULL) {
1600 printf("ti%d: couldn't map interrupt\n", unit);
1601 error = ENXIO;
1602 goto fail;
1603 }
1604
1605 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
1606 ti_intr, sc, &sc->ti_intrhand);
1607
1608 if (error) {
1609 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1610 bus_release_resource(dev, SYS_RES_MEMORY,
1611 TI_PCI_LOMEM, sc->ti_res);
1612 printf("ti%d: couldn't set up irq\n", unit);
1613 goto fail;
1614 }
1615
1616 sc->ti_unit = unit;
1617
1618 if (ti_chipinit(sc)) {
1619 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1620 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1621 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1622 bus_release_resource(dev, SYS_RES_MEMORY,
1623 TI_PCI_LOMEM, sc->ti_res);
1624 error = ENXIO;
1625 goto fail;
1626 }
1627
1628 /* Zero out the NIC's on-board SRAM. */
1629 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1630
1631 /* Init again -- zeroing memory may have clobbered some registers. */
1632 if (ti_chipinit(sc)) {
1633 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1634 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1635 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1636 bus_release_resource(dev, SYS_RES_MEMORY,
1637 TI_PCI_LOMEM, sc->ti_res);
1638 error = ENXIO;
1639 goto fail;
1640 }
1641
1642 /*
1643 * Get station address from the EEPROM. Note: the manual states
1644 * that the MAC address is at offset 0x8c, however the data is
1645 * stored as two longwords (since that's how it's loaded into
1646 * the NIC). This means the MAC address is actually preceeded
1647 * by two zero bytes. We need to skip over those.
1648 */
1649 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1650 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1651 printf("ti%d: failed to read station address\n", unit);
1652 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1653 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1654 bus_release_resource(dev, SYS_RES_MEMORY,
1655 TI_PCI_LOMEM, sc->ti_res);
1656 error = ENXIO;
1657 goto fail;
1658 }
1659
1660 /*
1661 * A Tigon chip was detected. Inform the world.
1662 */
1663 printf("ti%d: Ethernet address: %6D\n", unit,
1664 sc->arpcom.ac_enaddr, ":");
1665
1666 /* Allocate the general information block and ring buffers. */
1667 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
1668 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1669
1670 if (sc->ti_rdata == NULL) {
1671 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1672 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1673 bus_release_resource(dev, SYS_RES_MEMORY,
1674 TI_PCI_LOMEM, sc->ti_res);
1675 error = ENXIO;
1676 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
1677 goto fail;
1678 }
1679
1680 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1681
1682 /* Try to allocate memory for jumbo buffers. */
1683 if (ti_alloc_jumbo_mem(sc)) {
1684 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
1685 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1686 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1687 bus_release_resource(dev, SYS_RES_MEMORY,
1688 TI_PCI_LOMEM, sc->ti_res);
1689 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data),
1690 M_DEVBUF);
1691 error = ENXIO;
1692 goto fail;
1693 }
1694
1695 /*
1696 * We really need a better way to tell a 1000baseTX card
1697 * from a 1000baseSX one, since in theory there could be
1698 * OEMed 1000baseTX cards from lame vendors who aren't
1699 * clever enough to change the PCI ID. For the moment
1700 * though, the AceNIC is the only copper card available.
1701 */
1702 if (pci_get_vendor(dev) == ALT_VENDORID &&
1703 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
1704 sc->ti_copper = 1;
1705 /* Ok, it's not the only copper card available. */
1706 if (pci_get_vendor(dev) == NG_VENDORID &&
1707 pci_get_device(dev) == NG_DEVICEID_GA620T)
1708 sc->ti_copper = 1;
1709
1710 /* Set default tuneable values. */
1711 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1712 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1713 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1714 sc->ti_rx_max_coal_bds = 64;
1715 sc->ti_tx_max_coal_bds = 128;
1716 sc->ti_tx_buf_ratio = 21;
1717
1718 /* Set up ifnet structure */
1719 ifp = &sc->arpcom.ac_if;
1720 ifp->if_softc = sc;
1721 ifp->if_unit = sc->ti_unit;
1722 ifp->if_name = "ti";
1723 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1724 ifp->if_ioctl = ti_ioctl;
1725 ifp->if_output = ether_output;
1726 ifp->if_start = ti_start;
1727 ifp->if_watchdog = ti_watchdog;
1728 ifp->if_init = ti_init;
1729 ifp->if_mtu = ETHERMTU;
1730 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
1731
1732 /* Set up ifmedia support. */
1733 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1734 if (sc->ti_copper) {
1735 /*
1736 * Copper cards allow manual 10/100 mode selection,
1737 * but not manual 1000baseTX mode selection. Why?
1738 * Becuase currently there's no way to specify the
1739 * master/slave setting through the firmware interface,
1740 * so Alteon decided to just bag it and handle it
1741 * via autonegotiation.
1742 */
1743 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1744 ifmedia_add(&sc->ifmedia,
1745 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1746 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1747 ifmedia_add(&sc->ifmedia,
1748 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
1749 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_TX, 0, NULL);
1750 ifmedia_add(&sc->ifmedia,
1751 IFM_ETHER|IFM_1000_TX|IFM_FDX, 0, NULL);
1752 } else {
1753 /* Fiber cards don't support 10/100 modes. */
1754 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1755 ifmedia_add(&sc->ifmedia,
1756 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1757 }
1758 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1759 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1760
1761 /*
1762 * Call MI attach routine.
1763 */
1764 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1765
1766fail:
1767 splx(s);
1768
1769 return(error);
1770}
1771
1772static int ti_detach(dev)
1773 device_t dev;
1774{
1775 struct ti_softc *sc;
1776 struct ifnet *ifp;
1777 int s;
1778
1779 s = splimp();
1780
1781 sc = device_get_softc(dev);
1782 ifp = &sc->arpcom.ac_if;
1783
1784 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1785 ti_stop(sc);
1786
1787 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1788 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1789 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res);
1790
1791 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
1792 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
1793 ifmedia_removeall(&sc->ifmedia);
1794
1795 splx(s);
1796
1797 return(0);
1798}
1799
1800/*
1801 * Frame reception handling. This is called if there's a frame
1802 * on the receive return list.
1803 *
1804 * Note: we have to be able to handle three possibilities here:
1805 * 1) the frame is from the mini receive ring (can only happen)
1806 * on Tigon 2 boards)
1807 * 2) the frame is from the jumbo recieve ring
1808 * 3) the frame is from the standard receive ring
1809 */
1810
1811static void ti_rxeof(sc)
1812 struct ti_softc *sc;
1813{
1814 struct ifnet *ifp;
1815 struct ti_cmd_desc cmd;
1816
1817 ifp = &sc->arpcom.ac_if;
1818
1819 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1820 struct ti_rx_desc *cur_rx;
1821 u_int32_t rxidx;
1822 struct ether_header *eh;
1823 struct mbuf *m = NULL;
1824#if NVLAN > 0
1825 u_int16_t vlan_tag = 0;
1826 int have_tag = 0;
1827#endif
1828
1829 cur_rx =
1830 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1831 rxidx = cur_rx->ti_idx;
1832 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1833
1834#if NVLAN > 0
1835 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1836 have_tag = 1;
1837 vlan_tag = cur_rx->ti_vlan_tag;
1838 }
1839#endif
1840
1841 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1842 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1843 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1844 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1845 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1846 ifp->if_ierrors++;
1847 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1848 continue;
1849 }
1850 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1851 ifp->if_ierrors++;
1852 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1853 continue;
1854 }
1855 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1856 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1857 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1858 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1859 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1860 ifp->if_ierrors++;
1861 ti_newbuf_mini(sc, sc->ti_mini, m);
1862 continue;
1863 }
1864 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1865 ifp->if_ierrors++;
1866 ti_newbuf_mini(sc, sc->ti_mini, m);
1867 continue;
1868 }
1869 } else {
1870 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1871 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1872 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1873 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1874 ifp->if_ierrors++;
1875 ti_newbuf_std(sc, sc->ti_std, m);
1876 continue;
1877 }
1878 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1879 ifp->if_ierrors++;
1880 ti_newbuf_std(sc, sc->ti_std, m);
1881 continue;
1882 }
1883 }
1884
1885 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1886 ifp->if_ipackets++;
1887 eh = mtod(m, struct ether_header *);
1888 m->m_pkthdr.rcvif = ifp;
1889
1890 /* Remove header from mbuf and pass it on. */
1891 m_adj(m, sizeof(struct ether_header));
1892
1893 if (ifp->if_hwassist) {
1894 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1895 CSUM_DATA_VALID;
1896 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
1897 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1898 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
1899 }
1900
1901#if NVLAN > 0
1902 /*
1903 * If we received a packet with a vlan tag, pass it
1904 * to vlan_input() instead of ether_input().
1905 */
1906 if (have_tag) {
1907 vlan_input_tag(eh, m, vlan_tag);
1908 have_tag = vlan_tag = 0;
1909 continue;
1910 }
1911#endif
1912 ether_input(ifp, eh, m);
1913 }
1914
1915 /* Only necessary on the Tigon 1. */
1916 if (sc->ti_hwrev == TI_HWREV_TIGON)
1917 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1918 sc->ti_rx_saved_considx);
1919
1920 TI_UPDATE_STDPROD(sc, sc->ti_std);
1921 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1922 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1923
1924 return;
1925}
1926
1927static void ti_txeof(sc)
1928 struct ti_softc *sc;
1929{
1930 struct ti_tx_desc *cur_tx = NULL;
1931 struct ifnet *ifp;
1932
1933 ifp = &sc->arpcom.ac_if;
1934
1935 /*
1936 * Go through our tx ring and free mbufs for those
1937 * frames that have been sent.
1938 */
1939 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1940 u_int32_t idx = 0;
1941
1942 idx = sc->ti_tx_saved_considx;
1943 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1944 if (idx > 383)
1945 CSR_WRITE_4(sc, TI_WINBASE,
1946 TI_TX_RING_BASE + 6144);
1947 else if (idx > 255)
1948 CSR_WRITE_4(sc, TI_WINBASE,
1949 TI_TX_RING_BASE + 4096);
1950 else if (idx > 127)
1951 CSR_WRITE_4(sc, TI_WINBASE,
1952 TI_TX_RING_BASE + 2048);
1953 else
1954 CSR_WRITE_4(sc, TI_WINBASE,
1955 TI_TX_RING_BASE);
1956 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1957 } else
1958 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1959 if (cur_tx->ti_flags & TI_BDFLAG_END)
1960 ifp->if_opackets++;
1961 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1962 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1963 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1964 }
1965 sc->ti_txcnt--;
1966 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1967 ifp->if_timer = 0;
1968 }
1969
1970 if (cur_tx != NULL)
1971 ifp->if_flags &= ~IFF_OACTIVE;
1972
1973 return;
1974}
1975
1976static void ti_intr(xsc)
1977 void *xsc;
1978{
1979 struct ti_softc *sc;
1980 struct ifnet *ifp;
1981
1982 sc = xsc;
1983 ifp = &sc->arpcom.ac_if;
1984
1985#ifdef notdef
1986 /* Avoid this for now -- checking this register is expensive. */
1987 /* Make sure this is really our interrupt. */
1988 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
1989 return;
1990#endif
1991
1992 /* Ack interrupt and stop others from occuring. */
1993 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1994
1995 if (ifp->if_flags & IFF_RUNNING) {
1996 /* Check RX return ring producer/consumer */
1997 ti_rxeof(sc);
1998
1999 /* Check TX ring producer/consumer */
2000 ti_txeof(sc);
2001 }
2002
2003 ti_handle_events(sc);
2004
2005 /* Re-enable interrupts. */
2006 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2007
2008 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
2009 ti_start(ifp);
2010
2011 return;
2012}
2013
2014static void ti_stats_update(sc)
2015 struct ti_softc *sc;
2016{
2017 struct ifnet *ifp;
2018
2019 ifp = &sc->arpcom.ac_if;
2020
2021 ifp->if_collisions +=
2022 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2023 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2024 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2025 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
2026 ifp->if_collisions;
2027
2028 return;
2029}
2030
2031/*
2032 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2033 * pointers to descriptors.
2034 */
2035static int ti_encap(sc, m_head, txidx)
2036 struct ti_softc *sc;
2037 struct mbuf *m_head;
2038 u_int32_t *txidx;
2039{
2040 struct ti_tx_desc *f = NULL;
2041 struct mbuf *m;
2042 u_int32_t frag, cur, cnt = 0;
2043 u_int16_t csum_flags = 0;
2044#if NVLAN > 0
2045 struct ifvlan *ifv = NULL;
2046
2047 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2048 m_head->m_pkthdr.rcvif != NULL &&
2049 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN)
2050 ifv = m_head->m_pkthdr.rcvif->if_softc;
2051#endif
2052
2053 m = m_head;
2054 cur = frag = *txidx;
2055
2056 if (m_head->m_pkthdr.csum_flags) {
2057 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2058 csum_flags |= TI_BDFLAG_IP_CKSUM;
2059 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2060 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2061 if (m_head->m_flags & M_LASTFRAG)
2062 csum_flags |= TI_BDFLAG_IP_FRAG_END;
2063 else if (m_head->m_flags & M_FRAG)
2064 csum_flags |= TI_BDFLAG_IP_FRAG;
2065 }
2066 /*
2067 * Start packing the mbufs in this chain into
2068 * the fragment pointers. Stop when we run out
2069 * of fragments or hit the end of the mbuf chain.
2070 */
2071 for (m = m_head; m != NULL; m = m->m_next) {
2072 if (m->m_len != 0) {
2073 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2074 if (frag > 383)
2075 CSR_WRITE_4(sc, TI_WINBASE,
2076 TI_TX_RING_BASE + 6144);
2077 else if (frag > 255)
2078 CSR_WRITE_4(sc, TI_WINBASE,
2079 TI_TX_RING_BASE + 4096);
2080 else if (frag > 127)
2081 CSR_WRITE_4(sc, TI_WINBASE,
2082 TI_TX_RING_BASE + 2048);
2083 else
2084 CSR_WRITE_4(sc, TI_WINBASE,
2085 TI_TX_RING_BASE);
2086 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
2087 } else
2088 f = &sc->ti_rdata->ti_tx_ring[frag];
2089 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2090 break;
2091 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
2092 f->ti_len = m->m_len;
2093 f->ti_flags = csum_flags;
2094#if NVLAN > 0
2095 if (ifv != NULL) {
2096 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2097 f->ti_vlan_tag = ifv->ifv_tag;
2098 } else {
2099 f->ti_vlan_tag = 0;
2100 }
2101#endif
2102 /*
2103 * Sanity check: avoid coming within 16 descriptors
2104 * of the end of the ring.
2105 */
2106 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2107 return(ENOBUFS);
2108 cur = frag;
2109 TI_INC(frag, TI_TX_RING_CNT);
2110 cnt++;
2111 }
2112 }
2113
2114 if (m != NULL)
2115 return(ENOBUFS);
2116
2117 if (frag == sc->ti_tx_saved_considx)
2118 return(ENOBUFS);
2119
2120 if (sc->ti_hwrev == TI_HWREV_TIGON)
2121 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2122 TI_BDFLAG_END;
2123 else
2124 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2125 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2126 sc->ti_txcnt += cnt;
2127
2128 *txidx = frag;
2129
2130 return(0);
2131}
2132
2133/*
2134 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2135 * to the mbuf data regions directly in the transmit descriptors.
2136 */
2137static void ti_start(ifp)
2138 struct ifnet *ifp;
2139{
2140 struct ti_softc *sc;
2141 struct mbuf *m_head = NULL;
2142 u_int32_t prodidx = 0;
2143
2144 sc = ifp->if_softc;
2145
2146 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2147
2148 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2149 IF_DEQUEUE(&ifp->if_snd, m_head);
2150 if (m_head == NULL)
2151 break;
2152
2153 /*
2154 * XXX
2155 * safety overkill. If this is a fragmented packet chain
2156 * with delayed TCP/UDP checksums, then only encapsulate
2157 * it if we have enough descriptors to handle the entire
2158 * chain at once.
2159 * (paranoia -- may not actually be needed)
2160 */
2161 if (m_head->m_flags & M_FIRSTFRAG &&
2162 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2163 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2164 m_head->m_pkthdr.csum_data + 16) {
2165 IF_PREPEND(&ifp->if_snd, m_head);
2166 ifp->if_flags |= IFF_OACTIVE;
2167 break;
2168 }
2169 }
2170
2171 /*
2172 * Pack the data into the transmit ring. If we
2173 * don't have room, set the OACTIVE flag and wait
2174 * for the NIC to drain the ring.
2175 */
2176 if (ti_encap(sc, m_head, &prodidx)) {
2177 IF_PREPEND(&ifp->if_snd, m_head);
2178 ifp->if_flags |= IFF_OACTIVE;
2179 break;
2180 }
2181
2182 /*
2183 * If there's a BPF listener, bounce a copy of this frame
2184 * to him.
2185 */
2186 if (ifp->if_bpf)
2187 bpf_mtap(ifp, m_head);
2188 }
2189
2190 /* Transmit */
2191 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2192
2193 /*
2194 * Set a timeout in case the chip goes out to lunch.
2195 */
2196 ifp->if_timer = 5;
2197
2198 return;
2199}
2200
2201static void ti_init(xsc)
2202 void *xsc;
2203{
2204 struct ti_softc *sc = xsc;
2205 int s;
2206
2207 s = splimp();
2208
2209 /* Cancel pending I/O and flush buffers. */
2210 ti_stop(sc);
2211
2212 /* Init the gen info block, ring control blocks and firmware. */
2213 if (ti_gibinit(sc)) {
2214 printf("ti%d: initialization failure\n", sc->ti_unit);
2215 splx(s);
2216 return;
2217 }
2218
2219 splx(s);
2220
2221 return;
2222}
2223
2224static void ti_init2(sc)
2225 struct ti_softc *sc;
2226{
2227 struct ti_cmd_desc cmd;
2228 struct ifnet *ifp;
2229 u_int16_t *m;
2230 struct ifmedia *ifm;
2231 int tmp;
2232
2233 ifp = &sc->arpcom.ac_if;
2234
2235 /* Specify MTU and interface index. */
2236 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit);
2237 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2238 ETHER_HDR_LEN + ETHER_CRC_LEN);
2239 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2240
2241 /* Load our MAC address. */
2242 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2243 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2244 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2245 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2246
2247 /* Enable or disable promiscuous mode as needed. */
2248 if (ifp->if_flags & IFF_PROMISC) {
2249 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2250 } else {
2251 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2252 }
2253
2254 /* Program multicast filter. */
2255 ti_setmulti(sc);
2256
2257 /*
2258 * If this is a Tigon 1, we should tell the
2259 * firmware to use software packet filtering.
2260 */
2261 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2262 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2263 }
2264
2265 /* Init RX ring. */
2266 ti_init_rx_ring_std(sc);
2267
2268 /* Init jumbo RX ring. */
2269 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2270 ti_init_rx_ring_jumbo(sc);
2271
2272 /*
2273 * If this is a Tigon 2, we can also configure the
2274 * mini ring.
2275 */
2276 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2277 ti_init_rx_ring_mini(sc);
2278
2279 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2280 sc->ti_rx_saved_considx = 0;
2281
2282 /* Init TX ring. */
2283 ti_init_tx_ring(sc);
2284
2285 /* Tell firmware we're alive. */
2286 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2287
2288 /* Enable host interrupts. */
2289 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2290
2291 ifp->if_flags |= IFF_RUNNING;
2292 ifp->if_flags &= ~IFF_OACTIVE;
2293
2294 /*
2295 * Make sure to set media properly. We have to do this
2296 * here since we have to issue commands in order to set
2297 * the link negotiation and we can't issue commands until
2298 * the firmware is running.
2299 */
2300 ifm = &sc->ifmedia;
2301 tmp = ifm->ifm_media;
2302 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2303 ti_ifmedia_upd(ifp);
2304 ifm->ifm_media = tmp;
2305
2306 return;
2307}
2308
2309/*
2310 * Set media options.
2311 */
2312static int ti_ifmedia_upd(ifp)
2313 struct ifnet *ifp;
2314{
2315 struct ti_softc *sc;
2316 struct ifmedia *ifm;
2317 struct ti_cmd_desc cmd;
2318
2319 sc = ifp->if_softc;
2320 ifm = &sc->ifmedia;
2321
2322 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2323 return(EINVAL);
2324
2325 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2326 case IFM_AUTO:
2327 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2328 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
2329 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2330 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2331 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
2332 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2333 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2334 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2335 break;
2336 case IFM_1000_SX:
2337 case IFM_1000_TX:
2338 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2339 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
2340 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2341 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2342 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2343 }
2344 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2345 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2346 break;
2347 case IFM_100_FX:
2348 case IFM_10_FL:
2349 case IFM_100_TX:
2350 case IFM_10_T:
2351 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2352 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
2353 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2354 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
2355 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2356 } else {
2357 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2358 }
2359 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2360 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2361 } else {
2362 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2363 }
2364 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2365 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2366 break;
2367 }
2368
2369 return(0);
2370}
2371
2372/*
2373 * Report current media status.
2374 */
2375static void ti_ifmedia_sts(ifp, ifmr)
2376 struct ifnet *ifp;
2377 struct ifmediareq *ifmr;
2378{
2379 struct ti_softc *sc;
2380 u_int32_t media = 0;
2381
2382 sc = ifp->if_softc;
2383
2384 ifmr->ifm_status = IFM_AVALID;
2385 ifmr->ifm_active = IFM_ETHER;
2386
2387 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2388 return;
2389
2390 ifmr->ifm_status |= IFM_ACTIVE;
2391
2392 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2393 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2394 if (sc->ti_copper)
2395 ifmr->ifm_active |= IFM_1000_TX;
2396 else
2397 ifmr->ifm_active |= IFM_1000_SX;
2398 if (media & TI_GLNK_FULL_DUPLEX)
2399 ifmr->ifm_active |= IFM_FDX;
2400 else
2401 ifmr->ifm_active |= IFM_HDX;
2402 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2403 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2404 if (sc->ti_copper) {
2405 if (media & TI_LNK_100MB)
2406 ifmr->ifm_active |= IFM_100_TX;
2407 if (media & TI_LNK_10MB)
2408 ifmr->ifm_active |= IFM_10_T;
2409 } else {
2410 if (media & TI_LNK_100MB)
2411 ifmr->ifm_active |= IFM_100_FX;
2412 if (media & TI_LNK_10MB)
2413 ifmr->ifm_active |= IFM_10_FL;
2414 }
2415 if (media & TI_LNK_FULL_DUPLEX)
2416 ifmr->ifm_active |= IFM_FDX;
2417 if (media & TI_LNK_HALF_DUPLEX)
2418 ifmr->ifm_active |= IFM_HDX;
2419 }
2420
2421 return;
2422}
2423
2424static int ti_ioctl(ifp, command, data)
2425 struct ifnet *ifp;
2426 u_long command;
2427 caddr_t data;
2428{
2429 struct ti_softc *sc = ifp->if_softc;
2430 struct ifreq *ifr = (struct ifreq *) data;
2431 int s, error = 0;
2432 struct ti_cmd_desc cmd;
2433
2434 s = splimp();
2435
2436 switch(command) {
2437 case SIOCSIFADDR:
2438 case SIOCGIFADDR:
2439 error = ether_ioctl(ifp, command, data);
2440 break;
2441 case SIOCSIFMTU:
2442 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2443 error = EINVAL;
2444 else {
2445 ifp->if_mtu = ifr->ifr_mtu;
2446 ti_init(sc);
2447 }
2448 break;
2449 case SIOCSIFFLAGS:
2450 if (ifp->if_flags & IFF_UP) {
2451 /*
2452 * If only the state of the PROMISC flag changed,
2453 * then just use the 'set promisc mode' command
2454 * instead of reinitializing the entire NIC. Doing
2455 * a full re-init means reloading the firmware and
2456 * waiting for it to start up, which may take a
2457 * second or two.
2458 */
2459 if (ifp->if_flags & IFF_RUNNING &&
2460 ifp->if_flags & IFF_PROMISC &&
2461 !(sc->ti_if_flags & IFF_PROMISC)) {
2462 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2463 TI_CMD_CODE_PROMISC_ENB, 0);
2464 } else if (ifp->if_flags & IFF_RUNNING &&
2465 !(ifp->if_flags & IFF_PROMISC) &&
2466 sc->ti_if_flags & IFF_PROMISC) {
2467 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2468 TI_CMD_CODE_PROMISC_DIS, 0);
2469 } else
2470 ti_init(sc);
2471 } else {
2472 if (ifp->if_flags & IFF_RUNNING) {
2473 ti_stop(sc);
2474 }
2475 }
2476 sc->ti_if_flags = ifp->if_flags;
2477 error = 0;
2478 break;
2479 case SIOCADDMULTI:
2480 case SIOCDELMULTI:
2481 if (ifp->if_flags & IFF_RUNNING) {
2482 ti_setmulti(sc);
2483 error = 0;
2484 }
2485 break;
2486 case SIOCSIFMEDIA:
2487 case SIOCGIFMEDIA:
2488 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2489 break;
2490 default:
2491 error = EINVAL;
2492 break;
2493 }
2494
2495 (void)splx(s);
2496
2497 return(error);
2498}
2499
2500static void ti_watchdog(ifp)
2501 struct ifnet *ifp;
2502{
2503 struct ti_softc *sc;
2504
2505 sc = ifp->if_softc;
2506
2507 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
2508 ti_stop(sc);
2509 ti_init(sc);
2510
2511 ifp->if_oerrors++;
2512
2513 return;
2514}
2515
2516/*
2517 * Stop the adapter and free any mbufs allocated to the
2518 * RX and TX lists.
2519 */
2520static void ti_stop(sc)
2521 struct ti_softc *sc;
2522{
2523 struct ifnet *ifp;
2524 struct ti_cmd_desc cmd;
2525
2526 ifp = &sc->arpcom.ac_if;
2527
2528 /* Disable host interrupts. */
2529 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2530 /*
2531 * Tell firmware we're shutting down.
2532 */
2533 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2534
2535 /* Halt and reinitialize. */
2536 ti_chipinit(sc);
2537 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2538 ti_chipinit(sc);
2539
2540 /* Free the RX lists. */
2541 ti_free_rx_ring_std(sc);
2542
2543 /* Free jumbo RX list. */
2544 ti_free_rx_ring_jumbo(sc);
2545
2546 /* Free mini RX list. */
2547 ti_free_rx_ring_mini(sc);
2548
2549 /* Free TX buffers. */
2550 ti_free_tx_ring(sc);
2551
2552 sc->ti_ev_prodidx.ti_idx = 0;
2553 sc->ti_return_prodidx.ti_idx = 0;
2554 sc->ti_tx_considx.ti_idx = 0;
2555 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2556
2557 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2558
2559 return;
2560}
2561
2562/*
2563 * Stop all chip I/O so that the kernel's probe routines don't
2564 * get confused by errant DMAs when rebooting.
2565 */
2566static void ti_shutdown(dev)
2567 device_t dev;
2568{
2569 struct ti_softc *sc;
2570
2571 sc = device_get_softc(dev);
2572
2573 ti_chipinit(sc);
2574
2575 return;
2576}