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ppcreg.h (28259) ppcreg.h (38061)
1/*-
2 * Copyright (c) 1997 Nicolas Souchu
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
1/*-
2 * Copyright (c) 1997 Nicolas Souchu
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $Id: ppcreg.h,v 1.1 1997/08/14 14:01:36 msmith Exp $
26 * $Id: ppcreg.h,v 1.2 1997/08/16 14:07:26 msmith Exp $
27 *
28 */
27 *
28 */
29#ifndef __PPC_H
30#define __PPC_H
29#ifndef __PPCREG_H
30#define __PPCREG_H
31
32/*
33 * Parallel Port Chipset type.
34 */
31
32/*
33 * Parallel Port Chipset type.
34 */
35#define SMC_UNKNOWN 0x0
35#define SMC_LIKE 0x0
36#define SMC_37C665GT 0x1
37#define SMC_37C666GT 0x2
36#define SMC_37C665GT 0x1
37#define SMC_37C666GT 0x2
38#define NS_UNKNOWN 0x3
39#define NS_PC87332 0x4
40#define NS_PC87306 0x5
41#define INTEL_820191AA 0x6
42#define GENERIC 0x7
38#define NS_PC87332 0x3
39#define NS_PC87306 0x4
40#define INTEL_820191AA 0x5 /* XXX not implemented */
41#define GENERIC 0x6
42#define WINB_W83877F 0x7
43#define WINB_W83877AF 0x8
44#define WINB_UNKNOWN 0x9
43
44/*
45 * Generic structure to hold parallel port chipset info.
46 */
47struct ppc_data {
48
49 int ppc_unit;
50 int ppc_type;
51
45
46/*
47 * Generic structure to hold parallel port chipset info.
48 */
49struct ppc_data {
50
51 int ppc_unit;
52 int ppc_type;
53
54 int ppc_mode; /* chipset current mode */
55 int ppc_avm; /* chipset available modes */
56
52#define ppc_base ppc_link.base
57#define ppc_base ppc_link.base
53#define ppc_mode ppc_link.mode
54#define ppc_epp ppc_link.epp_protocol
55#define ppc_irq ppc_link.id_irq
58#define ppc_epp ppc_link.epp_protocol
59#define ppc_irq ppc_link.id_irq
60#define ppc_subm ppc_link.submicroseq
56
57 unsigned char ppc_flags;
58
59 struct ppb_link ppc_link;
60};
61
62/*
61
62 unsigned char ppc_flags;
63
64 struct ppb_link ppc_link;
65};
66
67/*
63 * Parallel Port Chipset errors. XXX
64 */
65#define PPC_ENOPORT 9
66
67/*
68 * Parallel Port Chipset registers.
69 */
70#define PPC_SPP_DTR 0 /* SPP data register */
71#define PPC_SPP_STR 1 /* SPP status register */
72#define PPC_SPP_CTR 2 /* SPP control register */
73#define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */
74#define PPC_ECP_FIFO 0x400 /* ECP fifo register */
75#define PPC_ECP_ECR 0x402 /* ECP extended control register */
76
68 * Parallel Port Chipset registers.
69 */
70#define PPC_SPP_DTR 0 /* SPP data register */
71#define PPC_SPP_STR 1 /* SPP status register */
72#define PPC_SPP_CTR 2 /* SPP control register */
73#define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */
74#define PPC_ECP_FIFO 0x400 /* ECP fifo register */
75#define PPC_ECP_ECR 0x402 /* ECP extended control register */
76
77#define r_dtr(ppc) inb((ppc)->ppc_base + PPC_SPP_DTR)
78#define r_str(ppc) inb((ppc)->ppc_base + PPC_SPP_STR)
79#define r_ctr(ppc) inb((ppc)->ppc_base + PPC_SPP_CTR)
80#define r_epp(ppc) inb((ppc)->ppc_base + PPC_EPP_DATA)
81#define r_ecr(ppc) inb((ppc)->ppc_base + PPC_ECP_ECR)
82#define r_fifo(ppc) inb((ppc)->ppc_base + PPC_ECP_FIFO)
77#define r_dtr(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_DTR))
78#define r_str(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_STR))
79#define r_ctr(ppc) ((char)inb((ppc)->ppc_base + PPC_SPP_CTR))
80#define r_epp(ppc) ((char)inb((ppc)->ppc_base + PPC_EPP_DATA))
81#define r_ecr(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_ECR))
82#define r_fifo(ppc) ((char)inb((ppc)->ppc_base + PPC_ECP_FIFO))
83
84#define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte)
85#define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte)
86#define w_ctr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_CTR, byte)
87#define w_epp(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_DATA, byte)
88#define w_ecr(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_ECR, byte)
89#define w_fifo(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_FIFO, byte)
90

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106#define PC873_EPP19 (1<<1)
107#define PC873_ECPEN (1<<2)
108#define PC873_ECPCLK (1<<3)
109#define PC873_PMC 0x06
110#define PC873_TUP 0x07
111#define PC873_SID 0x08
112
113/*
83
84#define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte)
85#define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte)
86#define w_ctr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_CTR, byte)
87#define w_epp(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_DATA, byte)
88#define w_ecr(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_ECR, byte)
89#define w_fifo(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_FIFO, byte)
90

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106#define PC873_EPP19 (1<<1)
107#define PC873_ECPEN (1<<2)
108#define PC873_ECPCLK (1<<3)
109#define PC873_PMC 0x06
110#define PC873_TUP 0x07
111#define PC873_SID 0x08
112
113/*
114 * Register defines for the SMC FDC37C66xGT parts.
114 * Register defines for the SMC FDC37C66xGT parts
115 */
116
117/* Init codes */
118#define SMC665_iCODE 0x55
119#define SMC666_iCODE 0x44
120
121/* Base configuration ports */
122#define SMC66x_CSR 0x3F0
123#define SMC666_CSR 0x370 /* hard-configured value for 666 */
124
125/* Bits */
126#define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */
115 */
116
117/* Init codes */
118#define SMC665_iCODE 0x55
119#define SMC666_iCODE 0x44
120
121/* Base configuration ports */
122#define SMC66x_CSR 0x3F0
123#define SMC666_CSR 0x370 /* hard-configured value for 666 */
124
125/* Bits */
126#define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */
127#define SMC_CR1_MODE 0x8 /* bit 3 */
127#define SMC_CR1_MODE (1<<3) /* bit 3 */
128#define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */
128#define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */
129#define SMC_CR4_EPPTYPE 0x40 /* bit 6 */
129#define SMC_CR4_EPPTYPE (1<<6) /* bit 6 */
130
131/* Extended modes */
132#define SMC_SPP 0x0 /* SPP */
133#define SMC_EPPSPP 0x1 /* EPP and SPP */
134#define SMC_ECP 0x2 /* ECP */
135#define SMC_ECPEPP 0x3 /* ECP and EPP */
136
130
131/* Extended modes */
132#define SMC_SPP 0x0 /* SPP */
133#define SMC_EPPSPP 0x1 /* EPP and SPP */
134#define SMC_ECP 0x2 /* ECP */
135#define SMC_ECPEPP 0x3 /* ECP and EPP */
136
137#endif
137/*
138 * Register defines for the Winbond W83877F parts
139 */
138
140
141#define WINB_W83877F_ID 0xa
142#define WINB_W83877AF_ID 0xb
143
144/* Configuration bits */
145#define WINB_HEFERE (1<<5) /* CROC bit 5 */
146#define WINB_HEFRAS (1<<0) /* CR16 bit 0 */
147
148#define WINB_PNPCVS (1<<2) /* CR16 bit 2 */
149#define WINB_CHIPID 0xf /* CR9 bits 0-3 */
150
151#define WINB_PRTMODS0 (1<<2) /* CR0 bit 2 */
152#define WINB_PRTMODS1 (1<<3) /* CR0 bit 3 */
153#define WINB_PRTMODS2 (1<<7) /* CR9 bit 7 */
154
155/* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */
156#define WINB_W83757 0x0
157#define WINB_EXTFDC 0x4
158#define WINB_EXTADP 0x8
159#define WINB_EXT2FDD 0xc
160#define WINB_JOYSTICK 0x80
161
162#define WINB_PARALLEL 0x80
163#define WINB_EPP_SPP 0x4
164#define WINB_ECP 0x8
165#define WINB_ECP_EPP 0xc
166
167#endif