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pci.c (123794) pci.c (128058)
1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 11 unchanged lines hidden (view full) ---

20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000, BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 11 unchanged lines hidden (view full) ---

20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/dev/pci/pci.c 123794 2003-12-24 02:01:22Z imp $
28 * $FreeBSD: head/sys/dev/pci/pci.c 128058 2004-04-09 15:44:34Z imp $
29 *
30 */
31
32#include "opt_bus.h"
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/malloc.h>

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63static uint32_t pci_mapbase(unsigned mapreg);
64static int pci_maptype(unsigned mapreg);
65static int pci_mapsize(unsigned testval);
66static int pci_maprange(unsigned mapreg);
67static void pci_fixancient(pcicfgregs *cfg);
68
69static int pci_porten(device_t pcib, int b, int s, int f);
70static int pci_memen(device_t pcib, int b, int s, int f);
29 *
30 */
31
32#include "opt_bus.h"
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/malloc.h>

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63static uint32_t pci_mapbase(unsigned mapreg);
64static int pci_maptype(unsigned mapreg);
65static int pci_mapsize(unsigned testval);
66static int pci_maprange(unsigned mapreg);
67static void pci_fixancient(pcicfgregs *cfg);
68
69static int pci_porten(device_t pcib, int b, int s, int f);
70static int pci_memen(device_t pcib, int b, int s, int f);
71static int pci_add_map(device_t pcib, int b, int s, int f, int reg,
71static int pci_add_map(device_t pcib, device_t bus, device_t dev,
72 int b, int s, int f, int reg,
72 struct resource_list *rl);
73static void pci_add_resources(device_t pcib, device_t bus,
74 device_t dev);
75static int pci_probe(device_t dev);
76static int pci_attach(device_t dev);
77static void pci_load_vendor_data(void);
78static int pci_describe_parse_line(char **ptr, int *vendor,
79 int *device, char **desc);
80static char *pci_describe_device(device_t dev);
81static int pci_modevent(module_t mod, int what, void *arg);
82static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
83 pcicfgregs *cfg);
84static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
73 struct resource_list *rl);
74static void pci_add_resources(device_t pcib, device_t bus,
75 device_t dev);
76static int pci_probe(device_t dev);
77static int pci_attach(device_t dev);
78static void pci_load_vendor_data(void);
79static int pci_describe_parse_line(char **ptr, int *vendor,
80 int *device, char **desc);
81static char *pci_describe_device(device_t dev);
82static int pci_modevent(module_t mod, int what, void *arg);
83static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
84 pcicfgregs *cfg);
85static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
86static void pci_cfg_restore(device_t, struct pci_devinfo *);
87static void pci_cfg_save(device_t, struct pci_devinfo *, int);
85
86static device_method_t pci_methods[] = {
87 /* Device interface */
88 DEVMETHOD(device_probe, pci_probe),
89 DEVMETHOD(device_attach, pci_attach),
90 DEVMETHOD(device_shutdown, bus_generic_shutdown),
88
89static device_method_t pci_methods[] = {
90 /* Device interface */
91 DEVMETHOD(device_probe, pci_probe),
92 DEVMETHOD(device_attach, pci_attach),
93 DEVMETHOD(device_shutdown, bus_generic_shutdown),
91 DEVMETHOD(device_suspend, bus_generic_suspend),
94 DEVMETHOD(device_suspend, pci_suspend),
92 DEVMETHOD(device_resume, pci_resume),
93
94 /* Bus interface */
95 DEVMETHOD(bus_print_child, pci_print_child),
96 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
97 DEVMETHOD(bus_read_ivar, pci_read_ivar),
98 DEVMETHOD(bus_write_ivar, pci_write_ivar),
95 DEVMETHOD(device_resume, pci_resume),
96
97 /* Bus interface */
98 DEVMETHOD(bus_print_child, pci_print_child),
99 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
100 DEVMETHOD(bus_read_ivar, pci_read_ivar),
101 DEVMETHOD(bus_write_ivar, pci_write_ivar),
99 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
102 DEVMETHOD(bus_driver_added, pci_driver_added),
100 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
101 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
102
103 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
104 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
105 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
106 DEVMETHOD(bus_delete_resource, pci_delete_resource),
107 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),

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608 case SYS_RES_MEMORY:
609 bit = PCIM_CMD_MEMEN;
610 error = "memory";
611 break;
612 default:
613 return (EINVAL);
614 }
615 pci_set_command_bit(dev, child, bit);
103 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
104 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
105
106 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
107 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
108 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
109 DEVMETHOD(bus_delete_resource, pci_delete_resource),
110 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),

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611 case SYS_RES_MEMORY:
612 bit = PCIM_CMD_MEMEN;
613 error = "memory";
614 break;
615 default:
616 return (EINVAL);
617 }
618 pci_set_command_bit(dev, child, bit);
619 /* Some devices seem to need a brief stall here, what do to? */
616 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
617 if (command & bit)
618 return (0);
619 device_printf(child, "failed to enable %s mapping!\n", error);
620 return (ENXIO);
621}
622
623int

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714 & PCIM_CMD_MEMEN) != 0;
715}
716
717/*
718 * Add a resource based on a pci map register. Return 1 if the map
719 * register is a 32bit map register or 2 if it is a 64bit register.
720 */
721static int
620 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
621 if (command & bit)
622 return (0);
623 device_printf(child, "failed to enable %s mapping!\n", error);
624 return (ENXIO);
625}
626
627int

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718 & PCIM_CMD_MEMEN) != 0;
719}
720
721/*
722 * Add a resource based on a pci map register. Return 1 if the map
723 * register is a 32bit map register or 2 if it is a 64bit register.
724 */
725static int
722pci_add_map(device_t pcib, int b, int s, int f, int reg,
723 struct resource_list *rl)
726pci_add_map(device_t pcib, device_t bus, device_t dev,
727 int b, int s, int f, int reg, struct resource_list *rl)
724{
725 uint32_t map;
726 uint64_t base;
728{
729 uint32_t map;
730 uint64_t base;
731 uint64_t start, end, count;
727 uint8_t ln2size;
728 uint8_t ln2range;
729 uint32_t testval;
730 uint16_t cmd;
731 int type;
732
733 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
732 uint8_t ln2size;
733 uint8_t ln2range;
734 uint32_t testval;
735 uint16_t cmd;
736 int type;
737
738 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
734
735 if (map == 0 || map == 0xffffffff)
736 return (1); /* skip invalid entry */
737
738 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
739 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
740 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
741
739 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
740 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
741 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
742
742 base = pci_mapbase(map);
743 if (pci_maptype(map) & PCI_MAPMEM)
744 type = SYS_RES_MEMORY;
745 else
746 type = SYS_RES_IOPORT;
747 ln2size = pci_mapsize(testval);
748 ln2range = pci_maprange(testval);
743 if (pci_maptype(map) & PCI_MAPMEM)
744 type = SYS_RES_MEMORY;
745 else
746 type = SYS_RES_IOPORT;
747 ln2size = pci_mapsize(testval);
748 ln2range = pci_maprange(testval);
749 if (ln2range == 64) {
749 base = pci_mapbase(map);
750
751 /*
752 * For I/O registers, if bottom bit is set, and the next bit up
753 * isn't clear, we know we have a BAR that doesn't conform to the
754 * spec, so ignore it. Also, sanity check the size of the data
755 * areas to the type of memory involved.
756 */
757 if ((testval & 0x1) == 0x1 &&
758 (testval & 0x2) != 0)
759 return (1);
760 if ((type == SYS_RES_MEMORY && ln2size < 5) ||
761 (type == SYS_RES_IOPORT && ln2size < 3))
762 return (1);
763
764 if (ln2range == 64)
750 /* Read the other half of a 64bit map register */
751 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
765 /* Read the other half of a 64bit map register */
766 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
752 }
753
754 if (bootverbose) {
755 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d",
756 reg, pci_maptype(map), ln2range,
757 (unsigned int) base, ln2size);
758 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
759 printf(", port disabled\n");
760 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
761 printf(", memory disabled\n");
762 else
763 printf(", enabled\n");
764 }
765
766 /*
767 * This code theoretically does the right thing, but has
767
768 if (bootverbose) {
769 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d",
770 reg, pci_maptype(map), ln2range,
771 (unsigned int) base, ln2size);
772 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
773 printf(", port disabled\n");
774 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
775 printf(", memory disabled\n");
776 else
777 printf(", enabled\n");
778 }
779
780 /*
781 * This code theoretically does the right thing, but has
768 * undesirable side effects in some cases where
769 * peripherals respond oddly to having these bits
770 * enabled. Leave them alone by default.
782 * undesirable side effects in some cases where peripherals
783 * respond oddly to having these bits enabled. Let the user
784 * be able to turn them off (since pci_enable_io_modes is 1 by
785 * default).
771 */
772 if (pci_enable_io_modes) {
773 /* Turn on resources that have been left off by a lazy BIOS */
774 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
775 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
776 cmd |= PCIM_CMD_PORTEN;
777 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
778 }
779 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
780 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
781 cmd |= PCIM_CMD_MEMEN;
782 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
783 }
784 } else {
785 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
786 return (1);
787 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
788 return (1);
789 }
786 */
787 if (pci_enable_io_modes) {
788 /* Turn on resources that have been left off by a lazy BIOS */
789 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
790 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
791 cmd |= PCIM_CMD_PORTEN;
792 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
793 }
794 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
795 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
796 cmd |= PCIM_CMD_MEMEN;
797 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
798 }
799 } else {
800 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
801 return (1);
802 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
803 return (1);
804 }
790 resource_list_add(rl, type, reg, base, base + (1 << ln2size) - 1,
791 (1 << ln2size));
805 /*
806 * If base is 0, then we have problems. It is best to ignore
807 * such entires for the moment. These will be allocated later if
808 * the driver specifically requests them.
809 */
810 if (base == 0)
811 return 1;
812 start = base;
813 end = base + (1 << ln2size) - 1;
814 count = 1 << ln2size;
815 resource_list_add(rl, type, reg, start, end, count);
792
816
817 /*
818 * Not quite sure what to do on failure of allocating the resource
819 * since I can postulate several right answers.
820 */
821 resource_list_alloc(rl, bus, dev, type, &reg, start, end, count, 0);
793 return ((ln2range == 64) ? 2 : 1);
794}
795
796static void
797pci_add_resources(device_t pcib, device_t bus, device_t dev)
798{
799 struct pci_devinfo *dinfo = device_get_ivars(dev);
800 pcicfgregs *cfg = &dinfo->cfg;
801 struct resource_list *rl = &dinfo->resources;
802 struct pci_quirk *q;
803 int b, i, irq, f, s;
804
805 b = cfg->bus;
806 s = cfg->slot;
807 f = cfg->func;
822 return ((ln2range == 64) ? 2 : 1);
823}
824
825static void
826pci_add_resources(device_t pcib, device_t bus, device_t dev)
827{
828 struct pci_devinfo *dinfo = device_get_ivars(dev);
829 pcicfgregs *cfg = &dinfo->cfg;
830 struct resource_list *rl = &dinfo->resources;
831 struct pci_quirk *q;
832 int b, i, irq, f, s;
833
834 b = cfg->bus;
835 s = cfg->slot;
836 f = cfg->func;
808 for (i = 0; i < cfg->nummaps;) {
809 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i), rl);
810 }
837 for (i = 0; i < cfg->nummaps;)
838 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i), rl);
811
812 for (q = &pci_quirks[0]; q->devid; q++) {
813 if (q->devid == ((cfg->device << 16) | cfg->vendor)
814 && q->type == PCI_QUIRK_MAP_REG)
839
840 for (q = &pci_quirks[0]; q->devid; q++) {
841 if (q->devid == ((cfg->device << 16) | cfg->vendor)
842 && q->type == PCI_QUIRK_MAP_REG)
815 pci_add_map(pcib, b, s, f, q->arg1, rl);
843 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl);
816 }
817
818 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
819#if defined(__ia64__) || defined(__i386__) || defined(__amd64__)
820 /*
821 * Try to re-route interrupts. Sometimes the BIOS or
822 * firmware may leave bogus values in these registers.
823 * If the re-route fails, then just stick with what we

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868void
869pci_add_child(device_t bus, struct pci_devinfo *dinfo)
870{
871 device_t pcib;
872
873 pcib = device_get_parent(bus);
874 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
875 device_set_ivars(dinfo->cfg.dev, dinfo);
844 }
845
846 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
847#if defined(__ia64__) || defined(__i386__) || defined(__amd64__)
848 /*
849 * Try to re-route interrupts. Sometimes the BIOS or
850 * firmware may leave bogus values in these registers.
851 * If the re-route fails, then just stick with what we

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896void
897pci_add_child(device_t bus, struct pci_devinfo *dinfo)
898{
899 device_t pcib;
900
901 pcib = device_get_parent(bus);
902 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
903 device_set_ivars(dinfo->cfg.dev, dinfo);
904 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
905 pci_cfg_restore(dinfo->cfg.dev, dinfo);
876 pci_add_resources(pcib, bus, dinfo->cfg.dev);
877 pci_print_verbose(dinfo);
878}
879
880static int
881pci_probe(device_t dev)
882{
883

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902 if (bootverbose)
903 device_printf(dev, "physical bus=%d\n", busno);
904
905 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
906
907 return (bus_generic_attach(dev));
908}
909
906 pci_add_resources(pcib, bus, dinfo->cfg.dev);
907 pci_print_verbose(dinfo);
908}
909
910static int
911pci_probe(device_t dev)
912{
913

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932 if (bootverbose)
933 device_printf(dev, "physical bus=%d\n", busno);
934
935 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
936
937 return (bus_generic_attach(dev));
938}
939
940int
941pci_suspend(device_t dev)
942{
943 int numdevs;
944 device_t *devlist;
945 device_t child;
946 struct pci_devinfo *dinfo;
947 int i;
948
949 /*
950 * Save the pci configuration space for each child. We don't need
951 * to do this, unless the BIOS suspend code powers down the bus and
952 * the devices on the bus.
953 */
954 device_get_children(dev, &devlist, &numdevs);
955 for (i = 0; i < numdevs; i++) {
956 child = devlist[i];
957 dinfo = (struct pci_devinfo *) device_get_ivars(child);
958 pci_cfg_save(child, dinfo, 0);
959 }
960 free(devlist, M_TEMP);
961 return (bus_generic_suspend(dev));
962}
963
964int
965pci_resume(device_t dev)
966{
967 int numdevs;
968 device_t *devlist;
969 device_t child;
970 struct pci_devinfo *dinfo;
971 int i;
972
973 /*
974 * Restore the pci configuration space for each child.
975 */
976 device_get_children(dev, &devlist, &numdevs);
977 for (i = 0; i < numdevs; i++) {
978 child = devlist[i];
979 dinfo = (struct pci_devinfo *) device_get_ivars(child);
980 pci_cfg_restore(child, dinfo);
981 }
982 free(devlist, M_TEMP);
983 return (bus_generic_resume(dev));
984}
985
910static void
911pci_load_vendor_data(void)
912{
913 caddr_t vendordata, info;
914
915 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
916 info = preload_search_info(vendordata, MODINFO_ADDR);
917 pci_vendordata = *(char **)info;
918 info = preload_search_info(vendordata, MODINFO_SIZE);
919 pci_vendordata_size = *(size_t *)info;
920 /* terminate the database */
921 pci_vendordata[pci_vendordata_size] = '\n';
922 }
923}
924
986static void
987pci_load_vendor_data(void)
988{
989 caddr_t vendordata, info;
990
991 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
992 info = preload_search_info(vendordata, MODINFO_ADDR);
993 pci_vendordata = *(char **)info;
994 info = preload_search_info(vendordata, MODINFO_SIZE);
995 pci_vendordata_size = *(size_t *)info;
996 /* terminate the database */
997 pci_vendordata[pci_vendordata_size] = '\n';
998 }
999}
1000
1001void
1002pci_driver_added(device_t dev, driver_t *driver)
1003{
1004 int numdevs;
1005 device_t *devlist;
1006 device_t child;
1007 struct pci_devinfo *dinfo;
1008 int i;
1009
1010 device_printf(dev, "driver added\n");
1011 DEVICE_IDENTIFY(driver, dev);
1012 device_get_children(dev, &devlist, &numdevs);
1013 for (i = 0; i < numdevs; i++) {
1014 child = devlist[i];
1015 if (device_get_state(child) != DS_NOTPRESENT)
1016 continue;
1017 dinfo = device_get_ivars(child);
1018 pci_print_verbose(dinfo);
1019/*XXX???*/ /* resource_list_init(&dinfo->cfg.resources); */
1020 printf("pci%d:%d:%d: reprobing on driver added\n",
1021 dinfo->cfg.bus, dinfo->cfg.slot, dinfo->cfg.func);
1022 pci_cfg_restore(child, dinfo);
1023 if (device_probe_and_attach(child) != 0)
1024 pci_cfg_save(child, dinfo, 1);
1025 }
1026 free(devlist, M_TEMP);
1027}
1028
925int
926pci_print_child(device_t dev, device_t child)
927{
928 struct pci_devinfo *dinfo;
929 struct resource_list *rl;
930 int retval = 0;
931
932 dinfo = device_get_ivars(child);

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1042 }
1043 device_printf(dev, "<%s%s%s>",
1044 cp ? cp : "",
1045 ((cp != NULL) && (scp != NULL)) ? ", " : "",
1046 scp ? scp : "");
1047 }
1048 printf(" at device %d.%d (no driver attached)\n",
1049 pci_get_slot(child), pci_get_function(child));
1029int
1030pci_print_child(device_t dev, device_t child)
1031{
1032 struct pci_devinfo *dinfo;
1033 struct resource_list *rl;
1034 int retval = 0;
1035
1036 dinfo = device_get_ivars(child);

--- 109 unchanged lines hidden (view full) ---

1146 }
1147 device_printf(dev, "<%s%s%s>",
1148 cp ? cp : "",
1149 ((cp != NULL) && (scp != NULL)) ? ", " : "",
1150 scp ? scp : "");
1151 }
1152 printf(" at device %d.%d (no driver attached)\n",
1153 pci_get_slot(child), pci_get_function(child));
1154 pci_cfg_save(child, (struct pci_devinfo *) device_get_ivars(child), 1);
1050 return;
1051}
1052
1053/*
1054 * Parse the PCI device database, if loaded, and return a pointer to a
1055 * description of the device.
1056 *
1057 * The database is flat text formatted as follows:

--- 263 unchanged lines hidden (view full) ---

1321 (p->pc_subclass << 8) | p->pc_progif,
1322 (p->pc_subdevice << 16) | p->pc_subvendor,
1323 (p->pc_device << 16) | p->pc_vendor,
1324 p->pc_revid, p->pc_hdr);
1325 }
1326}
1327#endif /* DDB */
1328
1155 return;
1156}
1157
1158/*
1159 * Parse the PCI device database, if loaded, and return a pointer to a
1160 * description of the device.
1161 *
1162 * The database is flat text formatted as follows:

--- 263 unchanged lines hidden (view full) ---

1426 (p->pc_subclass << 8) | p->pc_progif,
1427 (p->pc_subdevice << 16) | p->pc_subvendor,
1428 (p->pc_device << 16) | p->pc_vendor,
1429 p->pc_revid, p->pc_hdr);
1430 }
1431}
1432#endif /* DDB */
1433
1434/*
1435 * XXX I'm not sure the following is good for 64-bit bars.
1436 */
1437static struct resource *
1438pci_alloc_map(device_t dev, device_t child, int type, int *rid,
1439 u_long start, u_long end, u_long count, u_int flags)
1440{
1441 struct pci_devinfo *dinfo = device_get_ivars(child);
1442 struct resource_list *rl = &dinfo->resources;
1443 struct resource_list_entry *rle;
1444 struct resource *res;
1445 uint32_t map, testval;
1446 int mapsize;
1447
1448 /*
1449 * Weed out the bogons, and figure out how large the BAR/map is.
1450 */
1451 map = pci_read_config(child, *rid, 4);
1452 if (pci_maptype(map) & PCI_MAPMEM) {
1453 if (type != SYS_RES_MEMORY) {
1454 device_printf(child, "rid %#x says memory, driver wants %d failed.\n", *rid, type);
1455 return (NULL);
1456 }
1457 } else {
1458 if (type != SYS_RES_IOPORT) {
1459 device_printf(child, "rid %#x says ioport, driver wants %d failed.\n", *rid, type);
1460 return (NULL);
1461 }
1462 }
1463 pci_write_config(child, *rid, 0xffffffff, 4);
1464 testval = pci_read_config(child, *rid, 4);
1465
1466 /*
1467 * Allocate enough resource, and then write back the
1468 * appropriate bar for that resource (this is the part
1469 * I'm not sure is good for 64-bit bars).
1470 */
1471 mapsize = pci_mapsize(testval);
1472 count = 1 << mapsize;
1473 if (RF_ALIGNMENT(flags) < mapsize)
1474 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
1475 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
1476 start, end, count, flags);
1477 if (res == NULL) {
1478 device_printf(child, "%#lx bytes of rid %#x res %d failed.\n",
1479 count, *rid, type);
1480 pci_write_config(child, *rid, map, 4);
1481 return (NULL);
1482 }
1483 resource_list_add(rl, type, *rid, start, end, count);
1484 rle = resource_list_find(rl, type, *rid);
1485 if (rle == NULL)
1486 panic("pci_alloc_map: unexpedly can't find resource.");
1487 rle->res = res;
1488 device_printf(child, "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
1489 count, *rid, type, rman_get_start(res));
1490 pci_write_config(child, *rid, rman_get_start(res), 4);
1491 return (res);
1492}
1493
1494
1329struct resource *
1330pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1331 u_long start, u_long end, u_long count, u_int flags)
1332{
1333 struct pci_devinfo *dinfo = device_get_ivars(child);
1334 struct resource_list *rl = &dinfo->resources;
1495struct resource *
1496pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1497 u_long start, u_long end, u_long count, u_int flags)
1498{
1499 struct pci_devinfo *dinfo = device_get_ivars(child);
1500 struct resource_list *rl = &dinfo->resources;
1501 struct resource_list_entry *rle;
1335 pcicfgregs *cfg = &dinfo->cfg;
1336
1337 /*
1338 * Perform lazy resource allocation
1502 pcicfgregs *cfg = &dinfo->cfg;
1503
1504 /*
1505 * Perform lazy resource allocation
1339 *
1340 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1341 */
1342 if (device_get_parent(child) == dev) {
1343 switch (type) {
1344 case SYS_RES_IRQ:
1345 /*
1346 * If the child device doesn't have an
1347 * interrupt routed and is deserving of an
1348 * interrupt, try to assign it one.

--- 9 unchanged lines hidden (view full) ---

1358 }
1359 }
1360 break;
1361 case SYS_RES_IOPORT:
1362 case SYS_RES_MEMORY:
1363 if (*rid < PCIR_BAR(cfg->nummaps)) {
1364 /*
1365 * Enable the I/O mode. We should
1506 */
1507 if (device_get_parent(child) == dev) {
1508 switch (type) {
1509 case SYS_RES_IRQ:
1510 /*
1511 * If the child device doesn't have an
1512 * interrupt routed and is deserving of an
1513 * interrupt, try to assign it one.

--- 9 unchanged lines hidden (view full) ---

1523 }
1524 }
1525 break;
1526 case SYS_RES_IOPORT:
1527 case SYS_RES_MEMORY:
1528 if (*rid < PCIR_BAR(cfg->nummaps)) {
1529 /*
1530 * Enable the I/O mode. We should
1366 * also be allocating resources
1367 * too. XXX
1531 * also be assigning resources too
1532 * when none are present. The
1533 * resource_list_alloc kind of sorta does
1534 * this...
1368 */
1369 if (PCI_ENABLE_IO(dev, child, type))
1370 return (NULL);
1371 }
1535 */
1536 if (PCI_ENABLE_IO(dev, child, type))
1537 return (NULL);
1538 }
1539 rle = resource_list_find(rl, type, *rid);
1540 if (rle == NULL)
1541 return (pci_alloc_map(dev, child, type, rid,
1542 start, end, count, flags));
1372 break;
1373 }
1543 break;
1544 }
1545 /*
1546 * If we've already allocated the resource, then
1547 * return it now. But first we may need to activate
1548 * it, since we don't allocate the resource as active
1549 * above. Normally this would be done down in the
1550 * nexus, but since we short-circuit that path we have
1551 * to do its job here. Not sure if we should free the
1552 * resource if it fails to activate.
1553 */
1554 rle = resource_list_find(rl, type, *rid);
1555 if (rle != NULL && rle->res != NULL) {
1556 device_printf(child, "Bus reserved %#lx bytes for rid %#x type %d at %#lx\n", rman_get_size(rle->res), *rid, type, rman_get_start(rle->res));
1557 if ((flags & RF_ACTIVE) &&
1558 bus_generic_activate_resource(dev, child, type,
1559 *rid, rle->res) != 0)
1560 return NULL;
1561 return (rle->res);
1562 }
1374 }
1563 }
1375
1376 return (resource_list_alloc(rl, dev, child, type, rid,
1377 start, end, count, flags));
1378}
1379
1380void
1381pci_delete_resource(device_t dev, device_t child, int type, int rid)
1382{
1383 struct pci_devinfo *dinfo;

--- 27 unchanged lines hidden (view full) ---

1411 */
1412 pci_write_config(child, rid, 0, 4);
1413 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
1414}
1415
1416struct resource_list *
1417pci_get_resource_list (device_t dev, device_t child)
1418{
1564 return (resource_list_alloc(rl, dev, child, type, rid,
1565 start, end, count, flags));
1566}
1567
1568void
1569pci_delete_resource(device_t dev, device_t child, int type, int rid)
1570{
1571 struct pci_devinfo *dinfo;

--- 27 unchanged lines hidden (view full) ---

1599 */
1600 pci_write_config(child, rid, 0, 4);
1601 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
1602}
1603
1604struct resource_list *
1605pci_get_resource_list (device_t dev, device_t child)
1606{
1419 struct pci_devinfo * dinfo = device_get_ivars(child);
1420 struct resource_list * rl = &dinfo->resources;
1607 struct pci_devinfo *dinfo = device_get_ivars(child);
1421
1608
1422 if (!rl)
1423 return (NULL);
1424
1425 return (rl);
1609 return (&dinfo->resources);
1426}
1427
1428uint32_t
1429pci_read_config_method(device_t dev, device_t child, int reg, int width)
1430{
1431 struct pci_devinfo *dinfo = device_get_ivars(child);
1432 pcicfgregs *cfg = &dinfo->cfg;
1433

--- 8 unchanged lines hidden (view full) ---

1442 struct pci_devinfo *dinfo = device_get_ivars(child);
1443 pcicfgregs *cfg = &dinfo->cfg;
1444
1445 PCIB_WRITE_CONFIG(device_get_parent(dev),
1446 cfg->bus, cfg->slot, cfg->func, reg, val, width);
1447}
1448
1449int
1610}
1611
1612uint32_t
1613pci_read_config_method(device_t dev, device_t child, int reg, int width)
1614{
1615 struct pci_devinfo *dinfo = device_get_ivars(child);
1616 pcicfgregs *cfg = &dinfo->cfg;
1617

--- 8 unchanged lines hidden (view full) ---

1626 struct pci_devinfo *dinfo = device_get_ivars(child);
1627 pcicfgregs *cfg = &dinfo->cfg;
1628
1629 PCIB_WRITE_CONFIG(device_get_parent(dev),
1630 cfg->bus, cfg->slot, cfg->func, reg, val, width);
1631}
1632
1633int
1450pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
1634pci_child_location_str_method(device_t dev, device_t child, char *buf,
1451 size_t buflen)
1452{
1453 struct pci_devinfo *dinfo;
1454
1455 dinfo = device_get_ivars(child);
1456 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
1457 pci_get_function(child));
1458 return (0);
1459}
1460
1461int
1635 size_t buflen)
1636{
1637 struct pci_devinfo *dinfo;
1638
1639 dinfo = device_get_ivars(child);
1640 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
1641 pci_get_function(child));
1642 return (0);
1643}
1644
1645int
1462pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
1646pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
1463 size_t buflen)
1464{
1465 struct pci_devinfo *dinfo;
1466 pcicfgregs *cfg;
1467
1468 dinfo = device_get_ivars(child);
1469 cfg = &dinfo->cfg;
1470 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "

--- 30 unchanged lines hidden (view full) ---

1501 case MOD_UNLOAD:
1502 destroy_dev(pci_cdev);
1503 break;
1504 }
1505
1506 return (0);
1507}
1508
1647 size_t buflen)
1648{
1649 struct pci_devinfo *dinfo;
1650 pcicfgregs *cfg;
1651
1652 dinfo = device_get_ivars(child);
1653 cfg = &dinfo->cfg;
1654 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "

--- 30 unchanged lines hidden (view full) ---

1685 case MOD_UNLOAD:
1686 destroy_dev(pci_cdev);
1687 break;
1688 }
1689
1690 return (0);
1691}
1692
1509int
1510pci_resume(device_t dev)
1693static void
1694pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
1511{
1695{
1512 int numdevs;
1513 int i;
1514 device_t *children;
1515 device_t child;
1516 struct pci_devinfo *dinfo;
1517 pcicfgregs *cfg;
1696 int i;
1518
1697
1519 device_get_children(dev, &children, &numdevs);
1698 /*
1699 * Only do header type 0 devices. Type 1 devices are bridges, which
1700 * we know need special treatment. Type 2 devices are cardbus bridges
1701 * which also require special treatment. Other types are unknown, and
1702 * we err on the side of safety by ignoring them.
1703 */
1704 if (dinfo->cfg.hdrtype != 0)
1705 return;
1706 printf("pci%d:%d:%d: setting power state D0\n", dinfo->cfg.bus,
1707 dinfo->cfg.slot, dinfo->cfg.func);
1708 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1709 for (i = 0; i < dinfo->cfg.nummaps; i++)
1710 pci_write_config(dev, PCIR_MAPS + i * 4, dinfo->cfg.bar[i], 4);
1711 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
1712 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
1713 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
1714 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
1715 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
1716 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
1717 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
1718 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
1719}
1520
1720
1521 for (i = 0; i < numdevs; i++) {
1522 child = children[i];
1721static void
1722pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
1723{
1724 int i;
1725 uint32_t cls;
1523
1726
1524 dinfo = device_get_ivars(child);
1525 cfg = &dinfo->cfg;
1526 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
1527 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
1528 if (PCI_INTERRUPT_VALID(cfg->intline)) {
1529 pci_write_config(child, PCIR_INTLINE,
1530 cfg->intline, 1);
1531 }
1532 }
1533 }
1727 /*
1728 * Only do header type 0 devices. Type 1 devices are bridges, which
1729 * we know need special treatment. Type 2 devices are cardbus bridges
1730 * which also require special treatment. Other types are unknown, and
1731 * we err on the side of safety by ignoring them. Powering down
1732 * bridges should not be undertaken lightly.
1733 */
1734 if (dinfo->cfg.hdrtype != 0)
1735 return;
1736 for (i = 0; i < dinfo->cfg.nummaps; i++)
1737 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
1738 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
1534
1739
1535 free(children, M_TEMP);
1740 /*
1741 * Some drivers apparently write to these registers w/o
1742 * updating our cahced copy. No harm happens if we update the
1743 * copy, so do so here so we can restore them. The COMMAND
1744 * register is modified by the bus w/o updating the cache. This
1745 * should represent the normally writable portion of the 'defined'
1746 * part of type 0 headers. In theory we also need to save/restore
1747 * the PCI capability structures we know about, but apart from power
1748 * we don't know any that are writable.
1749 */
1750 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
1751 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
1752 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
1753 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
1754 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
1755 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1756 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1536
1757
1537 return (bus_generic_resume(dev));
1758 /*
1759 * don't set the state for display devices and for memory devices
1760 * since bad things happen. we should (a) have drivers that can easily
1761 * detach and (b) use generic drivers for these devices so that some
1762 * device actually attaches. We need to make sure that when we
1763 * implement (a) we don't power the device down on a reattach.
1764 *
1765 * John and Nate also tell me that we should be running the power up
1766 * and power down hooks when we change power state for those nodes
1767 * that have ACPI hooks in the tree.
1768 */
1769 cls = pci_get_class(dev);
1770 if (setstate && cls != PCIC_DISPLAY && cls != PCIC_MEMORY) {
1771 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
1772 printf("pci%d:%d:%d: setting power state D3\n", dinfo->cfg.bus,
1773 dinfo->cfg.slot, dinfo->cfg.func);
1774 }
1538}
1775}
1539