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ixgbe_82598.c (225736) ixgbe_82598.c (235528)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/9/sys/dev/ixgbe/ixgbe_82598.c 215911 2010-11-26 22:46:32Z jfv $*/
33/*$FreeBSD: stable/9/sys/dev/ixgbe/ixgbe_82598.c 235528 2012-05-17 00:06:54Z jfv $*/
34
35#include "ixgbe_type.h"
34
35#include "ixgbe_type.h"
36#include "ixgbe_82598.h"
36#include "ixgbe_api.h"
37#include "ixgbe_common.h"
38#include "ixgbe_phy.h"
39
37#include "ixgbe_api.h"
38#include "ixgbe_common.h"
39#include "ixgbe_phy.h"
40
40u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);
41s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
42static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
41static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
43 ixgbe_link_speed *speed,
44 bool *autoneg);
42 ixgbe_link_speed *speed,
43 bool *autoneg);
45static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
44static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
46s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
47static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
45static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
48 bool autoneg_wait_to_complete);
46 bool autoneg_wait_to_complete);
49static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
47static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
50 ixgbe_link_speed *speed, bool *link_up,
51 bool link_up_wait_to_complete);
48 ixgbe_link_speed *speed, bool *link_up,
49 bool link_up_wait_to_complete);
52static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
50static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
53 ixgbe_link_speed speed,
54 bool autoneg,
55 bool autoneg_wait_to_complete);
51 ixgbe_link_speed speed,
52 bool autoneg,
53 bool autoneg_wait_to_complete);
56static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
54static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
58 bool autoneg,
59 bool autoneg_wait_to_complete);
55 ixgbe_link_speed speed,
56 bool autoneg,
57 bool autoneg_wait_to_complete);
60static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
58static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
61s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw);
62void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw);
63s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
64static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
59static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
65s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan,
66 u32 vind, bool vlan_on);
67static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
60static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
68s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
69s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
70s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
71 u8 *eeprom_data);
72u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
73s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
74void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
75void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);
61static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
62 u32 headroom, int strategy);
76
77/**
78 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
79 * @hw: pointer to the HW structure
80 *
81 * The defaults for 82598 should be in the range of 50us to 50ms,
82 * however the hardware default for these parts is 500us to 1ms which is less
83 * than the 10ms recommended by the pci-e spec. To address this we need to

--- 42 unchanged lines hidden (view full) ---

126u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
127{
128 u32 msix_count = 18;
129
130 DEBUGFUNC("ixgbe_get_pcie_msix_count_82598");
131
132 if (hw->mac.msix_vectors_from_pcie) {
133 msix_count = IXGBE_READ_PCIE_WORD(hw,
63
64/**
65 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
66 * @hw: pointer to the HW structure
67 *
68 * The defaults for 82598 should be in the range of 50us to 50ms,
69 * however the hardware default for these parts is 500us to 1ms which is less
70 * than the 10ms recommended by the pci-e spec. To address this we need to

--- 42 unchanged lines hidden (view full) ---

113u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
114{
115 u32 msix_count = 18;
116
117 DEBUGFUNC("ixgbe_get_pcie_msix_count_82598");
118
119 if (hw->mac.msix_vectors_from_pcie) {
120 msix_count = IXGBE_READ_PCIE_WORD(hw,
134 IXGBE_PCIE_MSIX_82598_CAPS);
121 IXGBE_PCIE_MSIX_82598_CAPS);
135 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
136
137 /* MSI-X count is zero-based in HW, so increment to give
138 * proper value */
139 msix_count++;
140 }
141 return msix_count;
142}

--- 20 unchanged lines hidden (view full) ---

163 phy->ops.init = &ixgbe_init_phy_ops_82598;
164
165 /* MAC */
166 mac->ops.start_hw = &ixgbe_start_hw_82598;
167 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82598;
168 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
169 mac->ops.get_media_type = &ixgbe_get_media_type_82598;
170 mac->ops.get_supported_physical_layer =
122 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
123
124 /* MSI-X count is zero-based in HW, so increment to give
125 * proper value */
126 msix_count++;
127 }
128 return msix_count;
129}

--- 20 unchanged lines hidden (view full) ---

150 phy->ops.init = &ixgbe_init_phy_ops_82598;
151
152 /* MAC */
153 mac->ops.start_hw = &ixgbe_start_hw_82598;
154 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82598;
155 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
156 mac->ops.get_media_type = &ixgbe_get_media_type_82598;
157 mac->ops.get_supported_physical_layer =
171 &ixgbe_get_supported_physical_layer_82598;
158 &ixgbe_get_supported_physical_layer_82598;
172 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
173 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
174 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
175
176 /* RAR, Multicast, VLAN */
177 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
178 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
179 mac->ops.set_vfta = &ixgbe_set_vfta_82598;
159 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
160 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
161 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
162
163 /* RAR, Multicast, VLAN */
164 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
165 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
166 mac->ops.set_vfta = &ixgbe_set_vfta_82598;
167 mac->ops.set_vlvf = NULL;
180 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
181
182 /* Flow Control */
183 mac->ops.fc_enable = &ixgbe_fc_enable_82598;
184
168 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
169
170 /* Flow Control */
171 mac->ops.fc_enable = &ixgbe_fc_enable_82598;
172
185 mac->mcft_size = 128;
186 mac->vft_size = 128;
187 mac->num_rar_entries = 16;
188 mac->rx_pb_size = 512;
189 mac->max_tx_queues = 32;
190 mac->max_rx_queues = 64;
191 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
173 mac->mcft_size = 128;
174 mac->vft_size = 128;
175 mac->num_rar_entries = 16;
176 mac->rx_pb_size = 512;
177 mac->max_tx_queues = 32;
178 mac->max_rx_queues = 64;
179 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
192
193 /* SFP+ Module */
194 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
195
196 /* Link */
197 mac->ops.check_link = &ixgbe_check_mac_link_82598;
198 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
199 mac->ops.flap_tx_laser = NULL;
180
181 /* SFP+ Module */
182 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
183
184 /* Link */
185 mac->ops.check_link = &ixgbe_check_mac_link_82598;
186 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
187 mac->ops.flap_tx_laser = NULL;
200 mac->ops.get_link_capabilities =
201 &ixgbe_get_link_capabilities_82598;
188 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598;
189 mac->ops.setup_rxpba = &ixgbe_set_rxpba_82598;
202
190
191 /* Manageability interface */
192 mac->ops.set_fw_drv_ver = NULL;
193
203 return ret_val;
204}
205
206/**
207 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
208 * @hw: pointer to hardware structure
209 *
210 * Initialize any function pointers that were not able to be

--- 12 unchanged lines hidden (view full) ---

223
224 /* Identify the PHY */
225 phy->ops.identify(hw);
226
227 /* Overwrite the link function pointers if copper PHY */
228 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
229 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
230 mac->ops.get_link_capabilities =
194 return ret_val;
195}
196
197/**
198 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
199 * @hw: pointer to hardware structure
200 *
201 * Initialize any function pointers that were not able to be

--- 12 unchanged lines hidden (view full) ---

214
215 /* Identify the PHY */
216 phy->ops.identify(hw);
217
218 /* Overwrite the link function pointers if copper PHY */
219 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
220 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
221 mac->ops.get_link_capabilities =
231 &ixgbe_get_copper_link_capabilities_generic;
222 &ixgbe_get_copper_link_capabilities_generic;
232 }
233
234 switch (hw->phy.type) {
235 case ixgbe_phy_tn:
236 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
237 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
238 phy->ops.get_firmware_version =
223 }
224
225 switch (hw->phy.type) {
226 case ixgbe_phy_tn:
227 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
228 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
229 phy->ops.get_firmware_version =
239 &ixgbe_get_phy_firmware_version_tnx;
230 &ixgbe_get_phy_firmware_version_tnx;
240 break;
231 break;
241 case ixgbe_phy_aq:
242 phy->ops.get_firmware_version =
243 &ixgbe_get_phy_firmware_version_generic;
244 break;
245 case ixgbe_phy_nl:
246 phy->ops.reset = &ixgbe_reset_phy_nl;
247
248 /* Call SFP+ identify routine to get the SFP+ module type */
249 ret_val = phy->ops.identify_sfp(hw);
250 if (ret_val != IXGBE_SUCCESS)
251 goto out;
252 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
253 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
254 goto out;
255 }
256
257 /* Check to see if SFP+ module is supported */
258 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
232 case ixgbe_phy_nl:
233 phy->ops.reset = &ixgbe_reset_phy_nl;
234
235 /* Call SFP+ identify routine to get the SFP+ module type */
236 ret_val = phy->ops.identify_sfp(hw);
237 if (ret_val != IXGBE_SUCCESS)
238 goto out;
239 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
240 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
241 goto out;
242 }
243
244 /* Check to see if SFP+ module is supported */
245 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
259 &list_offset,
260 &data_offset);
246 &list_offset,
247 &data_offset);
261 if (ret_val != IXGBE_SUCCESS) {
262 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
263 goto out;
264 }
265 break;
266 default:
267 break;
268 }

--- 27 unchanged lines hidden (view full) ---

296 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
297 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
298 }
299
300 for (i = 0; ((i < hw->mac.max_rx_queues) &&
301 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
302 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
303 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
248 if (ret_val != IXGBE_SUCCESS) {
249 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
250 goto out;
251 }
252 break;
253 default:
254 break;
255 }

--- 27 unchanged lines hidden (view full) ---

283 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
284 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
285 }
286
287 for (i = 0; ((i < hw->mac.max_rx_queues) &&
288 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
289 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
290 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
304 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
291 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
305 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
306 }
307
308 /* set the completion timeout for interface */
309 if (ret_val == IXGBE_SUCCESS)
310 ixgbe_set_pcie_completion_timeout(hw);
311
312 return ret_val;
313}
314
315/**
316 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
317 * @hw: pointer to hardware structure
318 * @speed: pointer to link speed
319 * @autoneg: boolean auto-negotiation value
320 *
321 * Determines the link capabilities by reading the AUTOC register.
322 **/
323static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
292 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
293 }
294
295 /* set the completion timeout for interface */
296 if (ret_val == IXGBE_SUCCESS)
297 ixgbe_set_pcie_completion_timeout(hw);
298
299 return ret_val;
300}
301
302/**
303 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
304 * @hw: pointer to hardware structure
305 * @speed: pointer to link speed
306 * @autoneg: boolean auto-negotiation value
307 *
308 * Determines the link capabilities by reading the AUTOC register.
309 **/
310static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
324 ixgbe_link_speed *speed,
325 bool *autoneg)
311 ixgbe_link_speed *speed,
312 bool *autoneg)
326{
327 s32 status = IXGBE_SUCCESS;
328 u32 autoc = 0;
329
330 DEBUGFUNC("ixgbe_get_link_capabilities_82598");
331
332 /*
333 * Determine link capabilities based on the stored value of AUTOC,

--- 50 unchanged lines hidden (view full) ---

384 enum ixgbe_media_type media_type;
385
386 DEBUGFUNC("ixgbe_get_media_type_82598");
387
388 /* Detect if there is a copper PHY attached. */
389 switch (hw->phy.type) {
390 case ixgbe_phy_cu_unknown:
391 case ixgbe_phy_tn:
313{
314 s32 status = IXGBE_SUCCESS;
315 u32 autoc = 0;
316
317 DEBUGFUNC("ixgbe_get_link_capabilities_82598");
318
319 /*
320 * Determine link capabilities based on the stored value of AUTOC,

--- 50 unchanged lines hidden (view full) ---

371 enum ixgbe_media_type media_type;
372
373 DEBUGFUNC("ixgbe_get_media_type_82598");
374
375 /* Detect if there is a copper PHY attached. */
376 switch (hw->phy.type) {
377 case ixgbe_phy_cu_unknown:
378 case ixgbe_phy_tn:
392 case ixgbe_phy_aq:
393 media_type = ixgbe_media_type_copper;
394 goto out;
395 default:
396 break;
397 }
398
399 /* Media type for I82598 is based on device ID */
400 switch (hw->device_id) {

--- 34 unchanged lines hidden (view full) ---

435 * Enable flow control according to the current settings.
436 **/
437s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
438{
439 s32 ret_val = IXGBE_SUCCESS;
440 u32 fctrl_reg;
441 u32 rmcs_reg;
442 u32 reg;
379 media_type = ixgbe_media_type_copper;
380 goto out;
381 default:
382 break;
383 }
384
385 /* Media type for I82598 is based on device ID */
386 switch (hw->device_id) {

--- 34 unchanged lines hidden (view full) ---

421 * Enable flow control according to the current settings.
422 **/
423s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
424{
425 s32 ret_val = IXGBE_SUCCESS;
426 u32 fctrl_reg;
427 u32 rmcs_reg;
428 u32 reg;
443 u32 rx_pba_size;
444 u32 link_speed = 0;
445 bool link_up;
446
447 DEBUGFUNC("ixgbe_fc_enable_82598");
448
449 /*
450 * On 82598 having Rx FC on causes resets while doing 1G
451 * so if it's on turn it off once we know link_speed. For

--- 75 unchanged lines hidden (view full) ---

527
528 /* Set 802.3x based flow control settings. */
529 fctrl_reg |= IXGBE_FCTRL_DPF;
530 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
531 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
532
533 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
534 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
429 u32 link_speed = 0;
430 bool link_up;
431
432 DEBUGFUNC("ixgbe_fc_enable_82598");
433
434 /*
435 * On 82598 having Rx FC on causes resets while doing 1G
436 * so if it's on turn it off once we know link_speed. For

--- 75 unchanged lines hidden (view full) ---

512
513 /* Set 802.3x based flow control settings. */
514 fctrl_reg |= IXGBE_FCTRL_DPF;
515 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
516 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
517
518 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
519 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
535 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
536 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
537
538 reg = (rx_pba_size - hw->fc.low_water) << 6;
520 reg = hw->fc.low_water << 6;
539 if (hw->fc.send_xon)
540 reg |= IXGBE_FCRTL_XONE;
541
542 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
543
521 if (hw->fc.send_xon)
522 reg |= IXGBE_FCRTL_XONE;
523
524 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
525
544 reg = (rx_pba_size - hw->fc.high_water) << 6;
526 reg = hw->fc.high_water[packetbuf_num] << 6;
545 reg |= IXGBE_FCRTH_FCEN;
546
547 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
548 }
549
550 /* Configure pause time (2 TCs per register) */
551 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
552 if ((packetbuf_num & 1) == 0)

--- 11 unchanged lines hidden (view full) ---

564/**
565 * ixgbe_start_mac_link_82598 - Configures MAC link settings
566 * @hw: pointer to hardware structure
567 *
568 * Configures link settings based on values in the ixgbe_hw struct.
569 * Restarts the link. Performs autonegotiation if needed.
570 **/
571static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
527 reg |= IXGBE_FCRTH_FCEN;
528
529 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
530 }
531
532 /* Configure pause time (2 TCs per register) */
533 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
534 if ((packetbuf_num & 1) == 0)

--- 11 unchanged lines hidden (view full) ---

546/**
547 * ixgbe_start_mac_link_82598 - Configures MAC link settings
548 * @hw: pointer to hardware structure
549 *
550 * Configures link settings based on values in the ixgbe_hw struct.
551 * Restarts the link. Performs autonegotiation if needed.
552 **/
553static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
572 bool autoneg_wait_to_complete)
554 bool autoneg_wait_to_complete)
573{
574 u32 autoc_reg;
575 u32 links_reg;
576 u32 i;
577 s32 status = IXGBE_SUCCESS;
578
579 DEBUGFUNC("ixgbe_start_mac_link_82598");
580

--- 41 unchanged lines hidden (view full) ---

622 u16 an_reg;
623
624 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
625 return IXGBE_SUCCESS;
626
627 for (timeout = 0;
628 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
629 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
555{
556 u32 autoc_reg;
557 u32 links_reg;
558 u32 i;
559 s32 status = IXGBE_SUCCESS;
560
561 DEBUGFUNC("ixgbe_start_mac_link_82598");
562

--- 41 unchanged lines hidden (view full) ---

604 u16 an_reg;
605
606 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
607 return IXGBE_SUCCESS;
608
609 for (timeout = 0;
610 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
611 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
630 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);
612 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);
631
632 if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&
633 (an_reg & IXGBE_MII_AUTONEG_LINK_UP))
634 break;
635
636 msec_delay(100);
637 }
638

--- 10 unchanged lines hidden (view full) ---

649 * @hw: pointer to hardware structure
650 * @speed: pointer to link speed
651 * @link_up: TRUE is link is up, FALSE otherwise
652 * @link_up_wait_to_complete: bool used to wait for link up or not
653 *
654 * Reads the links register to determine if link is up and the current speed
655 **/
656static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
613
614 if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&
615 (an_reg & IXGBE_MII_AUTONEG_LINK_UP))
616 break;
617
618 msec_delay(100);
619 }
620

--- 10 unchanged lines hidden (view full) ---

631 * @hw: pointer to hardware structure
632 * @speed: pointer to link speed
633 * @link_up: TRUE is link is up, FALSE otherwise
634 * @link_up_wait_to_complete: bool used to wait for link up or not
635 *
636 * Reads the links register to determine if link is up and the current speed
637 **/
638static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
657 ixgbe_link_speed *speed, bool *link_up,
658 bool link_up_wait_to_complete)
639 ixgbe_link_speed *speed, bool *link_up,
640 bool link_up_wait_to_complete)
659{
660 u32 links_reg;
661 u32 i;
662 u16 link_reg, adapt_comp_reg;
663
664 DEBUGFUNC("ixgbe_check_mac_link_82598");
665
666 /*
667 * SERDES PHY requires us to read link status from undocumented
668 * register 0xC79F. Bit 0 set indicates link is up/ready; clear
669 * indicates link down. OxC00C is read to check that the XAUI lanes
670 * are active. Bit 0 clear indicates active; set indicates inactive.
671 */
672 if (hw->phy.type == ixgbe_phy_nl) {
673 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
674 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
675 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
641{
642 u32 links_reg;
643 u32 i;
644 u16 link_reg, adapt_comp_reg;
645
646 DEBUGFUNC("ixgbe_check_mac_link_82598");
647
648 /*
649 * SERDES PHY requires us to read link status from undocumented
650 * register 0xC79F. Bit 0 set indicates link is up/ready; clear
651 * indicates link down. OxC00C is read to check that the XAUI lanes
652 * are active. Bit 0 clear indicates active; set indicates inactive.
653 */
654 if (hw->phy.type == ixgbe_phy_nl) {
655 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
656 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
657 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
676 &adapt_comp_reg);
658 &adapt_comp_reg);
677 if (link_up_wait_to_complete) {
678 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
679 if ((link_reg & 1) &&
680 ((adapt_comp_reg & 1) == 0)) {
681 *link_up = TRUE;
682 break;
683 } else {
684 *link_up = FALSE;
685 }
686 msec_delay(100);
687 hw->phy.ops.read_reg(hw, 0xC79F,
659 if (link_up_wait_to_complete) {
660 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
661 if ((link_reg & 1) &&
662 ((adapt_comp_reg & 1) == 0)) {
663 *link_up = TRUE;
664 break;
665 } else {
666 *link_up = FALSE;
667 }
668 msec_delay(100);
669 hw->phy.ops.read_reg(hw, 0xC79F,
688 IXGBE_TWINAX_DEV,
689 &link_reg);
670 IXGBE_TWINAX_DEV,
671 &link_reg);
690 hw->phy.ops.read_reg(hw, 0xC00C,
672 hw->phy.ops.read_reg(hw, 0xC00C,
691 IXGBE_TWINAX_DEV,
692 &adapt_comp_reg);
673 IXGBE_TWINAX_DEV,
674 &adapt_comp_reg);
693 }
694 } else {
695 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
696 *link_up = TRUE;
697 else
698 *link_up = FALSE;
699 }
700

--- 24 unchanged lines hidden (view full) ---

725 *speed = IXGBE_LINK_SPEED_10GB_FULL;
726 else
727 *speed = IXGBE_LINK_SPEED_1GB_FULL;
728
729 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) &&
730 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
731 *link_up = FALSE;
732
675 }
676 } else {
677 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
678 *link_up = TRUE;
679 else
680 *link_up = FALSE;
681 }
682

--- 24 unchanged lines hidden (view full) ---

707 *speed = IXGBE_LINK_SPEED_10GB_FULL;
708 else
709 *speed = IXGBE_LINK_SPEED_1GB_FULL;
710
711 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) &&
712 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
713 *link_up = FALSE;
714
733 /* if link is down, zero out the current_mode */
734 if (*link_up == FALSE) {
735 hw->fc.current_mode = ixgbe_fc_none;
736 hw->fc.fc_was_autonegged = FALSE;
737 }
738out:
739 return IXGBE_SUCCESS;
740}
741
742/**
743 * ixgbe_setup_mac_link_82598 - Set MAC link speed
744 * @hw: pointer to hardware structure
745 * @speed: new link speed
746 * @autoneg: TRUE if autonegotiation enabled
747 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
748 *
749 * Set the link speed in the AUTOC register and restarts link.
750 **/
751static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
715out:
716 return IXGBE_SUCCESS;
717}
718
719/**
720 * ixgbe_setup_mac_link_82598 - Set MAC link speed
721 * @hw: pointer to hardware structure
722 * @speed: new link speed
723 * @autoneg: TRUE if autonegotiation enabled
724 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
725 *
726 * Set the link speed in the AUTOC register and restarts link.
727 **/
728static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
752 ixgbe_link_speed speed, bool autoneg,
753 bool autoneg_wait_to_complete)
729 ixgbe_link_speed speed, bool autoneg,
730 bool autoneg_wait_to_complete)
754{
731{
755 s32 status = IXGBE_SUCCESS;
732 s32 status = IXGBE_SUCCESS;
756 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
733 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
757 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
758 u32 autoc = curr_autoc;
759 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
734 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
735 u32 autoc = curr_autoc;
736 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
760
761 DEBUGFUNC("ixgbe_setup_mac_link_82598");
762
763 /* Check to see if speed passed in is supported. */
764 ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
765 speed &= link_capabilities;
766
767 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
768 status = IXGBE_ERR_LINK_SETUP;
769
770 /* Set KX4/KX support according to speed requested */
771 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
737
738 DEBUGFUNC("ixgbe_setup_mac_link_82598");
739
740 /* Check to see if speed passed in is supported. */
741 ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
742 speed &= link_capabilities;
743
744 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
745 status = IXGBE_ERR_LINK_SETUP;
746
747 /* Set KX4/KX support according to speed requested */
748 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
772 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
749 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
773 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
774 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
775 autoc |= IXGBE_AUTOC_KX4_SUPP;
776 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
777 autoc |= IXGBE_AUTOC_KX_SUPP;
778 if (autoc != curr_autoc)
779 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
780 }
781
782 if (status == IXGBE_SUCCESS) {
783 /*
784 * Setup and restart the link based on the new values in
785 * ixgbe_hw This will write the AUTOC register based on the new
786 * stored values
787 */
788 status = ixgbe_start_mac_link_82598(hw,
750 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
751 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
752 autoc |= IXGBE_AUTOC_KX4_SUPP;
753 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
754 autoc |= IXGBE_AUTOC_KX_SUPP;
755 if (autoc != curr_autoc)
756 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
757 }
758
759 if (status == IXGBE_SUCCESS) {
760 /*
761 * Setup and restart the link based on the new values in
762 * ixgbe_hw This will write the AUTOC register based on the new
763 * stored values
764 */
765 status = ixgbe_start_mac_link_82598(hw,
789 autoneg_wait_to_complete);
766 autoneg_wait_to_complete);
790 }
791
792 return status;
793}
794
795
796/**
797 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
798 * @hw: pointer to hardware structure
799 * @speed: new link speed
800 * @autoneg: TRUE if autonegotiation enabled
801 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
802 *
803 * Sets the link speed in the AUTOC register in the MAC and restarts link.
804 **/
805static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
767 }
768
769 return status;
770}
771
772
773/**
774 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
775 * @hw: pointer to hardware structure
776 * @speed: new link speed
777 * @autoneg: TRUE if autonegotiation enabled
778 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
779 *
780 * Sets the link speed in the AUTOC register in the MAC and restarts link.
781 **/
782static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
806 ixgbe_link_speed speed,
807 bool autoneg,
808 bool autoneg_wait_to_complete)
783 ixgbe_link_speed speed,
784 bool autoneg,
785 bool autoneg_wait_to_complete)
809{
810 s32 status;
811
812 DEBUGFUNC("ixgbe_setup_copper_link_82598");
813
814 /* Setup the PHY according to input speed */
815 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
786{
787 s32 status;
788
789 DEBUGFUNC("ixgbe_setup_copper_link_82598");
790
791 /* Setup the PHY according to input speed */
792 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
816 autoneg_wait_to_complete);
793 autoneg_wait_to_complete);
817 /* Set up MAC */
818 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
819
820 return status;
821}
822
823/**
824 * ixgbe_reset_hw_82598 - Performs hardware reset

--- 11 unchanged lines hidden (view full) ---

836 u32 gheccr;
837 u32 i;
838 u32 autoc;
839 u8 analog_val;
840
841 DEBUGFUNC("ixgbe_reset_hw_82598");
842
843 /* Call adapter stop to disable tx/rx and clear interrupts */
794 /* Set up MAC */
795 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
796
797 return status;
798}
799
800/**
801 * ixgbe_reset_hw_82598 - Performs hardware reset

--- 11 unchanged lines hidden (view full) ---

813 u32 gheccr;
814 u32 i;
815 u32 autoc;
816 u8 analog_val;
817
818 DEBUGFUNC("ixgbe_reset_hw_82598");
819
820 /* Call adapter stop to disable tx/rx and clear interrupts */
844 hw->mac.ops.stop_adapter(hw);
821 status = hw->mac.ops.stop_adapter(hw);
822 if (status != IXGBE_SUCCESS)
823 goto reset_hw_out;
845
846 /*
847 * Power up the Atlas Tx lanes if they are currently powered down.
848 * Atlas Tx lanes are powered down for MAC loopback tests, but
849 * they are not automatically restored on reset.
850 */
851 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
852 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
853 /* Enable Tx Atlas so packets can be transmitted again */
854 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
824
825 /*
826 * Power up the Atlas Tx lanes if they are currently powered down.
827 * Atlas Tx lanes are powered down for MAC loopback tests, but
828 * they are not automatically restored on reset.
829 */
830 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
831 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
832 /* Enable Tx Atlas so packets can be transmitted again */
833 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
855 &analog_val);
834 &analog_val);
856 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
857 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
835 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
836 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
858 analog_val);
837 analog_val);
859
860 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
838
839 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
861 &analog_val);
840 &analog_val);
862 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
863 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
841 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
842 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
864 analog_val);
843 analog_val);
865
866 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
844
845 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
867 &analog_val);
846 &analog_val);
868 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
869 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
847 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
848 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
870 analog_val);
849 analog_val);
871
872 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
850
851 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
873 &analog_val);
852 &analog_val);
874 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
875 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
853 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
854 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
876 analog_val);
855 analog_val);
877 }
878
879 /* Reset PHY */
880 if (hw->phy.reset_disable == FALSE) {
881 /* PHY ops must be identified and initialized prior to reset */
882
883 /* Init PHY and function pointers, perform SFP setup */
884 phy_status = hw->phy.ops.init(hw);
885 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
886 goto reset_hw_out;
856 }
857
858 /* Reset PHY */
859 if (hw->phy.reset_disable == FALSE) {
860 /* PHY ops must be identified and initialized prior to reset */
861
862 /* Init PHY and function pointers, perform SFP setup */
863 phy_status = hw->phy.ops.init(hw);
864 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
865 goto reset_hw_out;
887 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
888 goto no_phy_reset;
866 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
867 goto mac_reset_top;
889
890 hw->phy.ops.reset(hw);
891 }
892
868
869 hw->phy.ops.reset(hw);
870 }
871
893no_phy_reset:
894 /*
895 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
896 * access and verify no pending requests before reset
897 */
898 ixgbe_disable_pcie_master(hw);
899
900mac_reset_top:
901 /*
902 * Issue global reset to the MAC. This needs to be a SW reset.
903 * If link reset is used, it might reset the MAC when mng is using it
904 */
872mac_reset_top:
873 /*
874 * Issue global reset to the MAC. This needs to be a SW reset.
875 * If link reset is used, it might reset the MAC when mng is using it
876 */
905 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
906 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
877 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
878 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
907 IXGBE_WRITE_FLUSH(hw);
908
909 /* Poll for reset bit to self-clear indicating reset is complete */
910 for (i = 0; i < 10; i++) {
911 usec_delay(1);
912 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
913 if (!(ctrl & IXGBE_CTRL_RST))
914 break;
915 }
916 if (ctrl & IXGBE_CTRL_RST) {
917 status = IXGBE_ERR_RESET_FAILED;
918 DEBUGOUT("Reset polling failed to complete.\n");
919 }
920
879 IXGBE_WRITE_FLUSH(hw);
880
881 /* Poll for reset bit to self-clear indicating reset is complete */
882 for (i = 0; i < 10; i++) {
883 usec_delay(1);
884 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
885 if (!(ctrl & IXGBE_CTRL_RST))
886 break;
887 }
888 if (ctrl & IXGBE_CTRL_RST) {
889 status = IXGBE_ERR_RESET_FAILED;
890 DEBUGOUT("Reset polling failed to complete.\n");
891 }
892
893 msec_delay(50);
894
921 /*
922 * Double resets are required for recovery from certain error
923 * conditions. Between resets, it is necessary to stall to allow time
895 /*
896 * Double resets are required for recovery from certain error
897 * conditions. Between resets, it is necessary to stall to allow time
924 * for any pending HW events to complete. We use 1usec since that is
925 * what is needed for ixgbe_disable_pcie_master(). The second reset
926 * then clears out any effects of those events.
898 * for any pending HW events to complete.
927 */
928 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
929 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
899 */
900 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
901 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
930 usec_delay(1);
931 goto mac_reset_top;
932 }
933
902 goto mac_reset_top;
903 }
904
934 msec_delay(50);
935
936 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
937 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
938 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
939
940 /*
941 * Store the original AUTOC value if it has not been
942 * stored off yet. Otherwise restore the stored original
943 * AUTOC value since the reset operation sets back to deaults.

--- 54 unchanged lines hidden (view full) ---

998 * @rar: receive address register index to associate with a VMDq index
999 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
1000 **/
1001static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
1002{
1003 u32 rar_high;
1004 u32 rar_entries = hw->mac.num_rar_entries;
1005
905 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
906 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
907 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
908
909 /*
910 * Store the original AUTOC value if it has not been
911 * stored off yet. Otherwise restore the stored original
912 * AUTOC value since the reset operation sets back to deaults.

--- 54 unchanged lines hidden (view full) ---

967 * @rar: receive address register index to associate with a VMDq index
968 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
969 **/
970static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
971{
972 u32 rar_high;
973 u32 rar_entries = hw->mac.num_rar_entries;
974
1006 UNREFERENCED_PARAMETER(vmdq);
975 UNREFERENCED_1PARAMETER(vmdq);
1007
1008 /* Make sure we are using a valid rar index range */
1009 if (rar >= rar_entries) {
1010 DEBUGOUT1("RAR index %d is out of range.\n", rar);
1011 return IXGBE_ERR_INVALID_ARGUMENT;
1012 }
1013
1014 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));

--- 10 unchanged lines hidden (view full) ---

1025 * @hw: pointer to hardware structure
1026 * @vlan: VLAN id to write to VLAN filter
1027 * @vind: VMDq output index that maps queue to VLAN id in VFTA
1028 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
1029 *
1030 * Turn on/off specified VLAN in the VLAN filter table.
1031 **/
1032s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
976
977 /* Make sure we are using a valid rar index range */
978 if (rar >= rar_entries) {
979 DEBUGOUT1("RAR index %d is out of range.\n", rar);
980 return IXGBE_ERR_INVALID_ARGUMENT;
981 }
982
983 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));

--- 10 unchanged lines hidden (view full) ---

994 * @hw: pointer to hardware structure
995 * @vlan: VLAN id to write to VLAN filter
996 * @vind: VMDq output index that maps queue to VLAN id in VFTA
997 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
998 *
999 * Turn on/off specified VLAN in the VLAN filter table.
1000 **/
1001s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1033 bool vlan_on)
1002 bool vlan_on)
1034{
1035 u32 regindex;
1036 u32 bitindex;
1037 u32 bits;
1038 u32 vftabyte;
1039
1040 DEBUGFUNC("ixgbe_set_vfta_82598");
1041

--- 42 unchanged lines hidden (view full) ---

1084 DEBUGFUNC("ixgbe_clear_vfta_82598");
1085
1086 for (offset = 0; offset < hw->mac.vft_size; offset++)
1087 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1088
1089 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
1090 for (offset = 0; offset < hw->mac.vft_size; offset++)
1091 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
1003{
1004 u32 regindex;
1005 u32 bitindex;
1006 u32 bits;
1007 u32 vftabyte;
1008
1009 DEBUGFUNC("ixgbe_set_vfta_82598");
1010

--- 42 unchanged lines hidden (view full) ---

1053 DEBUGFUNC("ixgbe_clear_vfta_82598");
1054
1055 for (offset = 0; offset < hw->mac.vft_size; offset++)
1056 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1057
1058 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
1059 for (offset = 0; offset < hw->mac.vft_size; offset++)
1060 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
1092 0);
1061 0);
1093
1094 return IXGBE_SUCCESS;
1095}
1096
1097/**
1098 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
1099 * @hw: pointer to hardware structure
1100 * @reg: analog register to read
1101 * @val: read value
1102 *
1103 * Performs read operation to Atlas analog register specified.
1104 **/
1105s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
1106{
1107 u32 atlas_ctl;
1108
1109 DEBUGFUNC("ixgbe_read_analog_reg8_82598");
1110
1111 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1062
1063 return IXGBE_SUCCESS;
1064}
1065
1066/**
1067 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
1068 * @hw: pointer to hardware structure
1069 * @reg: analog register to read
1070 * @val: read value
1071 *
1072 * Performs read operation to Atlas analog register specified.
1073 **/
1074s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
1075{
1076 u32 atlas_ctl;
1077
1078 DEBUGFUNC("ixgbe_read_analog_reg8_82598");
1079
1080 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1112 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1081 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1113 IXGBE_WRITE_FLUSH(hw);
1114 usec_delay(10);
1115 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1116 *val = (u8)atlas_ctl;
1117
1118 return IXGBE_SUCCESS;
1119}
1120

--- 23 unchanged lines hidden (view full) ---

1144 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1145 * @hw: pointer to hardware structure
1146 * @byte_offset: EEPROM byte offset to read
1147 * @eeprom_data: value read
1148 *
1149 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1150 **/
1151s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1082 IXGBE_WRITE_FLUSH(hw);
1083 usec_delay(10);
1084 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1085 *val = (u8)atlas_ctl;
1086
1087 return IXGBE_SUCCESS;
1088}
1089

--- 23 unchanged lines hidden (view full) ---

1113 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1114 * @hw: pointer to hardware structure
1115 * @byte_offset: EEPROM byte offset to read
1116 * @eeprom_data: value read
1117 *
1118 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1119 **/
1120s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1152 u8 *eeprom_data)
1121 u8 *eeprom_data)
1153{
1154 s32 status = IXGBE_SUCCESS;
1155 u16 sfp_addr = 0;
1156 u16 sfp_data = 0;
1157 u16 sfp_stat = 0;
1158 u32 i;
1159
1160 DEBUGFUNC("ixgbe_read_i2c_eeprom_82598");
1161
1162 if (hw->phy.type == ixgbe_phy_nl) {
1163 /*
1164 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1165 * 0xC30D. These registers are used to talk to the SFP+
1166 * module's EEPROM through the SDA/SCL (I2C) interface.
1167 */
1168 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1169 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1170 hw->phy.ops.write_reg(hw,
1122{
1123 s32 status = IXGBE_SUCCESS;
1124 u16 sfp_addr = 0;
1125 u16 sfp_data = 0;
1126 u16 sfp_stat = 0;
1127 u32 i;
1128
1129 DEBUGFUNC("ixgbe_read_i2c_eeprom_82598");
1130
1131 if (hw->phy.type == ixgbe_phy_nl) {
1132 /*
1133 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1134 * 0xC30D. These registers are used to talk to the SFP+
1135 * module's EEPROM through the SDA/SCL (I2C) interface.
1136 */
1137 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1138 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1139 hw->phy.ops.write_reg(hw,
1171 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1172 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1173 sfp_addr);
1140 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1141 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1142 sfp_addr);
1174
1175 /* Poll status */
1176 for (i = 0; i < 100; i++) {
1177 hw->phy.ops.read_reg(hw,
1143
1144 /* Poll status */
1145 for (i = 0; i < 100; i++) {
1146 hw->phy.ops.read_reg(hw,
1178 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1179 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1180 &sfp_stat);
1147 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1148 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1149 &sfp_stat);
1181 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1182 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1183 break;
1184 msec_delay(10);
1185 }
1186
1187 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1188 DEBUGOUT("EEPROM read did not pass.\n");
1189 status = IXGBE_ERR_SFP_NOT_PRESENT;
1190 goto out;
1191 }
1192
1193 /* Read data */
1194 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1150 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1151 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1152 break;
1153 msec_delay(10);
1154 }
1155
1156 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1157 DEBUGOUT("EEPROM read did not pass.\n");
1158 status = IXGBE_ERR_SFP_NOT_PRESENT;
1159 goto out;
1160 }
1161
1162 /* Read data */
1163 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1195 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1164 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1196
1197 *eeprom_data = (u8)(sfp_data >> 8);
1198 } else {
1199 status = IXGBE_ERR_PHY;
1200 goto out;
1201 }
1202
1203out:

--- 17 unchanged lines hidden (view full) ---

1221 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");
1222
1223 hw->phy.ops.identify(hw);
1224
1225 /* Copper PHY must be checked before AUTOC LMS to determine correct
1226 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1227 switch (hw->phy.type) {
1228 case ixgbe_phy_tn:
1165
1166 *eeprom_data = (u8)(sfp_data >> 8);
1167 } else {
1168 status = IXGBE_ERR_PHY;
1169 goto out;
1170 }
1171
1172out:

--- 17 unchanged lines hidden (view full) ---

1190 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");
1191
1192 hw->phy.ops.identify(hw);
1193
1194 /* Copper PHY must be checked before AUTOC LMS to determine correct
1195 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1196 switch (hw->phy.type) {
1197 case ixgbe_phy_tn:
1229 case ixgbe_phy_aq:
1230 case ixgbe_phy_cu_unknown:
1231 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1232 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1233 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1234 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1235 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1236 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1237 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)

--- 122 unchanged lines hidden (view full) ---

1360 regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1361 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
1362 }
1363
1364 for (i = 0; ((i < hw->mac.max_rx_queues) &&
1365 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1366 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
1367 regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
1198 case ixgbe_phy_cu_unknown:
1199 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1200 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1201 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1202 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1203 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1204 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1205 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)

--- 122 unchanged lines hidden (view full) ---

1328 regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1329 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
1330 }
1331
1332 for (i = 0; ((i < hw->mac.max_rx_queues) &&
1333 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1334 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
1335 regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
1368 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
1336 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
1369 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
1370 }
1371
1372}
1337 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
1338 }
1339
1340}
1341
1342/**
1343 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1344 * @hw: pointer to hardware structure
1345 * @num_pb: number of packet buffers to allocate
1346 * @headroom: reserve n KB of headroom
1347 * @strategy: packet buffer allocation strategy
1348 **/
1349static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
1350 u32 headroom, int strategy)
1351{
1352 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1353 u8 i = 0;
1354 UNREFERENCED_1PARAMETER(headroom);
1355
1356 if (!num_pb)
1357 return;
1358
1359 /* Setup Rx packet buffer sizes */
1360 switch (strategy) {
1361 case PBA_STRATEGY_WEIGHTED:
1362 /* Setup the first four at 80KB */
1363 rxpktsize = IXGBE_RXPBSIZE_80KB;
1364 for (; i < 4; i++)
1365 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1366 /* Setup the last four at 48KB...don't re-init i */
1367 rxpktsize = IXGBE_RXPBSIZE_48KB;
1368 /* Fall Through */
1369 case PBA_STRATEGY_EQUAL:
1370 default:
1371 /* Divide the remaining Rx packet buffer evenly among the TCs */
1372 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1373 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1374 break;
1375 }
1376
1377 /* Setup Tx packet buffer sizes */
1378 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1379 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
1380
1381 return;
1382}