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if_igb.h (190872) if_igb.h (194865)
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/if_igb.h 190872 2009-04-10 00:05:46Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/if_igb.h 194865 2009-06-24 17:41:29Z jfv $*/
34
35#ifndef _IGB_H_DEFINED_
36#define _IGB_H_DEFINED_
37
38/* Tunables */
39
40/*
41 * IGB_TXD: Maximum number of Transmit Descriptors

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179
180#define MAX_NUM_MULTICAST_ADDRESSES 128
181#define PCI_ANY_ID (~0U)
182#define ETHER_ALIGN 2
183#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514)
184#define IGB_FC_PAUSE_TIME 0x0680
185#define IGB_EEPROM_APME 0x400;
186
34
35#ifndef _IGB_H_DEFINED_
36#define _IGB_H_DEFINED_
37
38/* Tunables */
39
40/*
41 * IGB_TXD: Maximum number of Transmit Descriptors

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179
180#define MAX_NUM_MULTICAST_ADDRESSES 128
181#define PCI_ANY_ID (~0U)
182#define ETHER_ALIGN 2
183#define IGB_TX_BUFFER_SIZE ((uint32_t) 1514)
184#define IGB_FC_PAUSE_TIME 0x0680
185#define IGB_EEPROM_APME 0x400;
186
187/* Code compatilbility between 6 and 7 */
188#ifndef ETHER_BPF_MTAP
189#define ETHER_BPF_MTAP BPF_MTAP
190#endif
191
192#if __FreeBSD_version < 700000
193#define CSUM_TSO 0
194#define IFCAP_TSO4 0
195#define FILTER_STRAY
196#define FILTER_HANDLED
197#endif
198
199/*
200 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
201 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
202 * also optimize cache line size effect. H/W supports up to cache line size 128.
203 */
204#define IGB_DBA_ALIGN 128
205
206#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */

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227#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
228#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
229#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
230#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
231#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
232#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
233
234#define IGB_MAX_SCATTER 64
187/*
188 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
189 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
190 * also optimize cache line size effect. H/W supports up to cache line size 128.
191 */
192#define IGB_DBA_ALIGN 128
193
194#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */

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215#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
216#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
217#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
218#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
219#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
220#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
221
222#define IGB_MAX_SCATTER 64
223#define IGB_VFTA_SIZE 128
224#define IGB_BR_SIZE 4096 /* ring buf size */
235#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
236#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */
237#define IGB_HDR_BUF 128
238#define ETH_ZLEN 60
239#define ETH_ADDR_LEN 6
240
241/* Offload bits in mbuf flag */
242#if __FreeBSD_version >= 800000

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253/*
254 * Interrupt Moderation parameters
255 */
256#define IGB_LOW_LATENCY 128
257#define IGB_AVE_LATENCY 450
258#define IGB_BULK_LATENCY 1200
259#define IGB_LINK_ITR 2000
260
225#define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
226#define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */
227#define IGB_HDR_BUF 128
228#define ETH_ZLEN 60
229#define ETH_ADDR_LEN 6
230
231/* Offload bits in mbuf flag */
232#if __FreeBSD_version >= 800000

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243/*
244 * Interrupt Moderation parameters
245 */
246#define IGB_LOW_LATENCY 128
247#define IGB_AVE_LATENCY 450
248#define IGB_BULK_LATENCY 1200
249#define IGB_LINK_ITR 2000
250
261#ifdef IGB_TIMESYNC
262/* Precision Time Sync (IEEE 1588) defines */
263#define ETHERTYPE_IEEE1588 0x88F7
264#define PICOSECS_PER_TICK 20833
265#define TSYNC_PORT 319 /* UDP port for the protocol */
266
251/* Precision Time Sync (IEEE 1588) defines */
252#define ETHERTYPE_IEEE1588 0x88F7
253#define PICOSECS_PER_TICK 20833
254#define TSYNC_PORT 319 /* UDP port for the protocol */
255
267/* TIMESYNC IOCTL defines */
268#define IGB_TIMESYNC_READTS _IOWR('i', 127, struct igb_tsync_read)
269#define IGB_TIMESTAMP 5 /* A unique return value */
270
271/* Used in the READTS IOCTL */
272struct igb_tsync_read {
273 int read_current_time;
274 struct timespec system_time;
275 u64 network_time;
276 u64 rx_stamp;
277 u64 tx_stamp;
278 u16 seqid;
279 unsigned char srcid[6];
280 int rx_valid;
281 int tx_valid;
282};
283
284#endif /* IGB_TIMESYNC */
285
286struct adapter; /* forward reference */
287
288struct igb_int_delay_info {
289 struct adapter *adapter; /* Back-pointer to the adapter struct */
290 int offset; /* Register offset to read/write */
291 int value; /* Current value in usecs */
292};
293
294/*
295 * Bus dma allocation structure used by
296 * e1000_dma_malloc and e1000_dma_free.
297 */
298struct igb_dma_alloc {
299 bus_addr_t dma_paddr;
300 caddr_t dma_vaddr;
301 bus_dma_tag_t dma_tag;

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317 char mtx_name[16];
318 struct igb_dma_alloc txdma; /* bus_dma glue for tx desc */
319 struct e1000_tx_desc *tx_base;
320 struct task tx_task; /* cleanup tasklet */
321 u32 next_avail_desc;
322 u32 next_to_clean;
323 volatile u16 tx_avail;
324 struct igb_tx_buffer *tx_buffers;
256/*
257 * Bus dma allocation structure used by
258 * e1000_dma_malloc and e1000_dma_free.
259 */
260struct igb_dma_alloc {
261 bus_addr_t dma_paddr;
262 caddr_t dma_vaddr;
263 bus_dma_tag_t dma_tag;

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279 char mtx_name[16];
280 struct igb_dma_alloc txdma; /* bus_dma glue for tx desc */
281 struct e1000_tx_desc *tx_base;
282 struct task tx_task; /* cleanup tasklet */
283 u32 next_avail_desc;
284 u32 next_to_clean;
285 volatile u16 tx_avail;
286 struct igb_tx_buffer *tx_buffers;
287#if __FreeBSD_version >= 800000
288 struct buf_ring *br;
289#endif
325 bus_dma_tag_t txtag; /* dma tag for tx */
290 bus_dma_tag_t txtag; /* dma tag for tx */
291 struct resource *res;
292 void *tag;
293
326 u32 watchdog_timer;
327 u64 no_desc_avail;
328 u64 tx_irq;
329 u64 tx_packets;
330};
331
332/*
333 * Receive ring: one per rx queue
334 */
335struct rx_ring {
336 struct adapter *adapter;
337 u32 me;
338 u32 msix; /* This ring's MSIX vector */
339 u32 eims; /* This ring's EIMS bit */
340 struct igb_dma_alloc rxdma; /* bus_dma glue for tx desc */
341 union e1000_adv_rx_desc *rx_base;
342 struct lro_ctrl lro;
294 u32 watchdog_timer;
295 u64 no_desc_avail;
296 u64 tx_irq;
297 u64 tx_packets;
298};
299
300/*
301 * Receive ring: one per rx queue
302 */
303struct rx_ring {
304 struct adapter *adapter;
305 u32 me;
306 u32 msix; /* This ring's MSIX vector */
307 u32 eims; /* This ring's EIMS bit */
308 struct igb_dma_alloc rxdma; /* bus_dma glue for tx desc */
309 union e1000_adv_rx_desc *rx_base;
310 struct lro_ctrl lro;
311 bool lro_enabled;
312 bool hdr_split;
343 struct task rx_task; /* cleanup tasklet */
344 struct mtx rx_mtx;
345 char mtx_name[16];
346 u32 last_cleaned;
347 u32 next_to_check;
348 struct igb_rx_buffer *rx_buffers;
349 bus_dma_tag_t rxtag; /* dma tag for tx */
350 bus_dmamap_t rx_spare_map;
351 /*
352 * First/last mbuf pointers, for
353 * collecting multisegment RX packets.
354 */
355 struct mbuf *fmp;
356 struct mbuf *lmp;
357
358 u32 bytes;
359 u32 eitr_setting;
360
313 struct task rx_task; /* cleanup tasklet */
314 struct mtx rx_mtx;
315 char mtx_name[16];
316 u32 last_cleaned;
317 u32 next_to_check;
318 struct igb_rx_buffer *rx_buffers;
319 bus_dma_tag_t rxtag; /* dma tag for tx */
320 bus_dmamap_t rx_spare_map;
321 /*
322 * First/last mbuf pointers, for
323 * collecting multisegment RX packets.
324 */
325 struct mbuf *fmp;
326 struct mbuf *lmp;
327
328 u32 bytes;
329 u32 eitr_setting;
330
331 struct resource *res;
332 void *tag;
333
361 /* Soft stats */
362 u64 rx_irq;
363 u64 rx_split_packets;
364 u64 rx_packets;
365 u64 rx_bytes;
366};
367
368struct adapter {
369 struct ifnet *ifp;
370 struct e1000_hw hw;
371
372 /* FreeBSD operating-system-specific structures. */
373 struct e1000_osdep osdep;
374 struct device *dev;
375
376 struct resource *pci_mem;
377 struct resource *msix_mem;
334 /* Soft stats */
335 u64 rx_irq;
336 u64 rx_split_packets;
337 u64 rx_packets;
338 u64 rx_bytes;
339};
340
341struct adapter {
342 struct ifnet *ifp;
343 struct e1000_hw hw;
344
345 /* FreeBSD operating-system-specific structures. */
346 struct e1000_osdep osdep;
347 struct device *dev;
348
349 struct resource *pci_mem;
350 struct resource *msix_mem;
378 struct resource *res[IGB_MSIX_VEC];
379 void *tag[IGB_MSIX_VEC];
380 int rid[IGB_MSIX_VEC];
351 struct resource *res;
352 void *tag;
381 u32 eims_mask;
382
383 int linkvec;
384 int link_mask;
385 int link_irq;
386
387 struct ifmedia media;
388 struct callout timer;
389 int msix; /* total vectors allocated */
390 int if_flags;
391 int max_frame_size;
392 int min_frame_size;
393 struct mtx core_mtx;
394 int igb_insert_vlan_header;
395 struct task link_task;
396 struct task rxtx_task;
397 struct taskqueue *tq; /* private task queue */
353 u32 eims_mask;
354
355 int linkvec;
356 int link_mask;
357 int link_irq;
358
359 struct ifmedia media;
360 struct callout timer;
361 int msix; /* total vectors allocated */
362 int if_flags;
363 int max_frame_size;
364 int min_frame_size;
365 struct mtx core_mtx;
366 int igb_insert_vlan_header;
367 struct task link_task;
368 struct task rxtx_task;
369 struct taskqueue *tq; /* private task queue */
370 u16 num_queues;
371
398 eventhandler_tag vlan_attach;
399 eventhandler_tag vlan_detach;
372 eventhandler_tag vlan_attach;
373 eventhandler_tag vlan_detach;
374 u32 num_vlans;
400
401 /* Management and WOL features */
402 int wol;
403 int has_manage;
404
405 /* Info about the board itself */
406 u8 link_active;
407 u16 link_speed;
408 u16 link_duplex;
409 u32 smartspeed;
410
411 /*
412 * Transmit rings
413 */
414 struct tx_ring *tx_rings;
415 u16 num_tx_desc;
375
376 /* Management and WOL features */
377 int wol;
378 int has_manage;
379
380 /* Info about the board itself */
381 u8 link_active;
382 u16 link_speed;
383 u16 link_duplex;
384 u32 smartspeed;
385
386 /*
387 * Transmit rings
388 */
389 struct tx_ring *tx_rings;
390 u16 num_tx_desc;
416 u16 num_tx_queues;
417 u32 txd_cmd;
418
419 /*
420 * Receive rings
421 */
422 struct rx_ring *rx_rings;
423 bool rx_hdr_split;
424 u16 num_rx_desc;
391 u32 txd_cmd;
392
393 /*
394 * Receive rings
395 */
396 struct rx_ring *rx_rings;
397 bool rx_hdr_split;
398 u16 num_rx_desc;
425 u16 num_rx_queues;
426 int rx_process_limit;
427 u32 rx_mbuf_sz;
428 u32 rx_mask;
429
430 /* Misc stats maintained by the driver */
431 unsigned long dropped_pkts;
432 unsigned long mbuf_defrag_failed;
433 unsigned long mbuf_header_failed;
434 unsigned long mbuf_packet_failed;
435 unsigned long no_tx_map_avail;
436 unsigned long no_tx_dma_setup;
437 unsigned long watchdog_events;
438 unsigned long rx_overruns;
439
440 boolean_t in_detach;
441
399 int rx_process_limit;
400 u32 rx_mbuf_sz;
401 u32 rx_mask;
402
403 /* Misc stats maintained by the driver */
404 unsigned long dropped_pkts;
405 unsigned long mbuf_defrag_failed;
406 unsigned long mbuf_header_failed;
407 unsigned long mbuf_packet_failed;
408 unsigned long no_tx_map_avail;
409 unsigned long no_tx_dma_setup;
410 unsigned long watchdog_events;
411 unsigned long rx_overruns;
412
413 boolean_t in_detach;
414
442#ifdef IGB_TIMESYNC
443 u64 last_stamp;
444 u64 last_sec;
445 u32 last_ns;
415#ifdef IGB_IEEE1588
416 /* IEEE 1588 precision time support */
417 struct cyclecounter cycles;
418 struct nettimer clock;
419 struct nettime_compare compare;
420 struct hwtstamp_ctrl hwtstamp;
446#endif
447
448 struct e1000_hw_stats stats;
449};
450
451/* ******************************************************************************
452 * vendor_info_array
453 *

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478
479#define IGB_CORE_LOCK_INIT(_sc, _name) \
480 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF)
481#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
482#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
483#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
484#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
485#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
421#endif
422
423 struct e1000_hw_stats stats;
424};
425
426/* ******************************************************************************
427 * vendor_info_array
428 *

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453
454#define IGB_CORE_LOCK_INIT(_sc, _name) \
455 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF)
456#define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
457#define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)
458#define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx)
459#define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx)
460#define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx)
461#define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
486#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
487#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
488#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
489#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
490#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
491#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
492
493#endif /* _IGB_H_DEFINED_ */
494
495
462#define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
463#define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
464#define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
465#define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
466#define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
467#define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
468
469#endif /* _IGB_H_DEFINED_ */
470
471