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if_em.h (203083) if_em.h (205869)
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/if_em.h 203083 2010-01-27 18:00:24Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/if_em.h 205869 2010-03-29 23:36:34Z jfv $*/
34
35
36#ifndef _EM_H_DEFINED_
37#define _EM_H_DEFINED_
38
39
40/* Tunables */
41

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47 * This value is the number of transmit descriptors allocated by the driver.
48 * Increasing this value allows the driver to queue more transmits. Each
49 * descriptor is 16 bytes.
50 * Since TDLEN should be multiple of 128bytes, the number of transmit
51 * desscriptors should meet the following condition.
52 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
53 */
54#define EM_MIN_TXD 80
34
35
36#ifndef _EM_H_DEFINED_
37#define _EM_H_DEFINED_
38
39
40/* Tunables */
41

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47 * This value is the number of transmit descriptors allocated by the driver.
48 * Increasing this value allows the driver to queue more transmits. Each
49 * descriptor is 16 bytes.
50 * Since TDLEN should be multiple of 128bytes, the number of transmit
51 * desscriptors should meet the following condition.
52 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
53 */
54#define EM_MIN_TXD 80
55#define EM_MAX_TXD_82543 256
56#define EM_MAX_TXD 4096
57#define EM_DEFAULT_TXD 1024
58
59/*
60 * EM_RXD - Maximum number of receive Descriptors
61 * Valid Range: 80-256 for 82542 and 82543-based adapters
62 * 80-4096 for others
63 * Default Value: 256
64 * This value is the number of receive descriptors allocated by the driver.
65 * Increasing this value allows the driver to buffer more incoming packets.
66 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
67 * descriptor. The maximum MTU size is 16110.
68 * Since TDLEN should be multiple of 128bytes, the number of transmit
69 * desscriptors should meet the following condition.
70 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
71 */
72#define EM_MIN_RXD 80
55#define EM_MAX_TXD 4096
56#define EM_DEFAULT_TXD 1024
57
58/*
59 * EM_RXD - Maximum number of receive Descriptors
60 * Valid Range: 80-256 for 82542 and 82543-based adapters
61 * 80-4096 for others
62 * Default Value: 256
63 * This value is the number of receive descriptors allocated by the driver.
64 * Increasing this value allows the driver to buffer more incoming packets.
65 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
66 * descriptor. The maximum MTU size is 16110.
67 * Since TDLEN should be multiple of 128bytes, the number of transmit
68 * desscriptors should meet the following condition.
69 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
70 */
71#define EM_MIN_RXD 80
73#define EM_MAX_RXD_82543 256
74#define EM_MAX_RXD 4096
75#define EM_DEFAULT_RXD 1024
76
77/*
78 * EM_TIDV - Transmit Interrupt Delay Value
79 * Valid Range: 0-65535 (0=off)
80 * Default Value: 64
81 * This value delays the generation of transmit interrupts in units of

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139 */
140#define EM_WATCHDOG (10 * hz)
141
142/*
143 * This parameter controls when the driver calls the routine to reclaim
144 * transmit descriptors.
145 */
146#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
72#define EM_MAX_RXD 4096
73#define EM_DEFAULT_RXD 1024
74
75/*
76 * EM_TIDV - Transmit Interrupt Delay Value
77 * Valid Range: 0-65535 (0=off)
78 * Default Value: 64
79 * This value delays the generation of transmit interrupts in units of

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137 */
138#define EM_WATCHDOG (10 * hz)
139
140/*
141 * This parameter controls when the driver calls the routine to reclaim
142 * transmit descriptors.
143 */
144#define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
147#define EM_TX_OP_THRESHOLD (adapter->num_tx_desc / 32)
148
149/*
150 * This parameter controls whether or not autonegotation is enabled.
151 * 0 - Disable autonegotiation
152 * 1 - Enable autonegotiation
153 */
154#define DO_AUTO_NEG 1
155

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177 */
178#define EM_VENDOR_ID 0x8086
179#define EM_FLASH 0x0014
180
181#define EM_JUMBO_PBA 0x00000028
182#define EM_DEFAULT_PBA 0x00000030
183#define EM_SMARTSPEED_DOWNSHIFT 3
184#define EM_SMARTSPEED_MAX 15
145
146/*
147 * This parameter controls whether or not autonegotation is enabled.
148 * 0 - Disable autonegotiation
149 * 1 - Enable autonegotiation
150 */
151#define DO_AUTO_NEG 1
152

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174 */
175#define EM_VENDOR_ID 0x8086
176#define EM_FLASH 0x0014
177
178#define EM_JUMBO_PBA 0x00000028
179#define EM_DEFAULT_PBA 0x00000030
180#define EM_SMARTSPEED_DOWNSHIFT 3
181#define EM_SMARTSPEED_MAX 15
185#define EM_MAX_INTR 10
182#define EM_MAX_LOOP 10
186
187#define MAX_NUM_MULTICAST_ADDRESSES 128
188#define PCI_ANY_ID (~0U)
189#define ETHER_ALIGN 2
190#define EM_FC_PAUSE_TIME 0x0680
191#define EM_EEPROM_APME 0x400;
192#define EM_82544_APME 0x0004;
193
183
184#define MAX_NUM_MULTICAST_ADDRESSES 128
185#define PCI_ANY_ID (~0U)
186#define ETHER_ALIGN 2
187#define EM_FC_PAUSE_TIME 0x0680
188#define EM_EEPROM_APME 0x400;
189#define EM_82544_APME 0x0004;
190
194/* Code compatilbility between 6 and 7 */
195#ifndef ETHER_BPF_MTAP
196#define ETHER_BPF_MTAP BPF_MTAP
197#endif
198
199/*
200 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
201 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
202 * also optimize cache line size effect. H/W supports up to cache line size 128.
203 */
204#define EM_DBA_ALIGN 128
205
206#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
207
208/* PCI Config defines */
209#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
210#define EM_BAR_TYPE_MASK 0x00000001
211#define EM_BAR_TYPE_MMEM 0x00000000
191/*
192 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
193 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
194 * also optimize cache line size effect. H/W supports up to cache line size 128.
195 */
196#define EM_DBA_ALIGN 128
197
198#define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */
199
200/* PCI Config defines */
201#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK)
202#define EM_BAR_TYPE_MASK 0x00000001
203#define EM_BAR_TYPE_MMEM 0x00000000
212#define EM_BAR_TYPE_IO 0x00000001
213#define EM_BAR_TYPE_FLASH 0x0014
214#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
215#define EM_BAR_MEM_TYPE_MASK 0x00000006
216#define EM_BAR_MEM_TYPE_32BIT 0x00000000
217#define EM_BAR_MEM_TYPE_64BIT 0x00000004
218#define EM_MSIX_BAR 3 /* On 82575 */
219
220/* Defines for printing debug information */

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232#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
233#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
234
235#define EM_MAX_SCATTER 64
236#define EM_VFTA_SIZE 128
237#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
238#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
239#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
204#define EM_BAR_TYPE_FLASH 0x0014
205#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK)
206#define EM_BAR_MEM_TYPE_MASK 0x00000006
207#define EM_BAR_MEM_TYPE_32BIT 0x00000000
208#define EM_BAR_MEM_TYPE_64BIT 0x00000004
209#define EM_MSIX_BAR 3 /* On 82575 */
210
211/* Defines for printing debug information */

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223#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
224#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
225
226#define EM_MAX_SCATTER 64
227#define EM_VFTA_SIZE 128
228#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
229#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
230#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
231#define EM_MSIX_LINK 0x01000000 /* For 82574 use */
240#define ETH_ZLEN 60
241#define ETH_ADDR_LEN 6
242#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
243
244/*
245 * 82574 has a nonstandard address for EIAC
246 * and since its only used in MSIX, and in
247 * the em driver only 82574 uses MSIX we can
248 * solve it just using this define.
249 */
250#define EM_EIAC 0x000DC
251
232#define ETH_ZLEN 60
233#define ETH_ADDR_LEN 6
234#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
235
236/*
237 * 82574 has a nonstandard address for EIAC
238 * and since its only used in MSIX, and in
239 * the em driver only 82574 uses MSIX we can
240 * solve it just using this define.
241 */
242#define EM_EIAC 0x000DC
243
252/* Used in for 82547 10Mb Half workaround */
253#define EM_PBA_BYTES_SHIFT 0xA
254#define EM_TX_HEAD_ADDR_SHIFT 7
255#define EM_PBA_TX_MASK 0xFFFF0000
256#define EM_FIFO_HDR 0x10
257#define EM_82547_PKT_THRESH 0x3e0
258
259/* Precision Time Sync (IEEE 1588) defines */
260#define ETHERTYPE_IEEE1588 0x88F7
261#define PICOSECS_PER_TICK 20833
262#define TSYNC_PORT 319 /* UDP port for the protocol */
263
264/*
265 * Bus dma allocation structure used by
266 * e1000_dma_malloc and e1000_dma_free.
267 */
268struct em_dma_alloc {
269 bus_addr_t dma_paddr;
270 caddr_t dma_vaddr;
271 bus_dma_tag_t dma_tag;

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277struct adapter;
278
279struct em_int_delay_info {
280 struct adapter *adapter; /* Back-pointer to the adapter struct */
281 int offset; /* Register offset to read/write */
282 int value; /* Current value in usecs */
283};
284
244/*
245 * Bus dma allocation structure used by
246 * e1000_dma_malloc and e1000_dma_free.
247 */
248struct em_dma_alloc {
249 bus_addr_t dma_paddr;
250 caddr_t dma_vaddr;
251 bus_dma_tag_t dma_tag;

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257struct adapter;
258
259struct em_int_delay_info {
260 struct adapter *adapter; /* Back-pointer to the adapter struct */
261 int offset; /* Register offset to read/write */
262 int value; /* Current value in usecs */
263};
264
265/*
266 * The transmit ring, one per tx queue
267 */
268struct tx_ring {
269 struct adapter *adapter;
270 struct mtx tx_mtx;
271 char mtx_name[16];
272 u32 me;
273 u32 msix;
274 u32 ims;
275 bool watchdog_check;
276 int watchdog_time;
277 struct em_dma_alloc txdma;
278 struct e1000_tx_desc *tx_base;
279 struct task tx_task;
280 struct taskqueue *tq;
281 u32 next_avail_desc;
282 u32 next_to_clean;
283 struct em_buffer *tx_buffers;
284 volatile u16 tx_avail;
285 u32 tx_tso; /* last tx was tso */
286 u16 last_hw_offload;
287#if __FreeBSD_version >= 800000
288 struct buf_ring *br;
289#endif
290 /* Interrupt resources */
291 bus_dma_tag_t txtag;
292 void *tag;
293 struct resource *res;
294 u64 tx_irq;
295 u64 no_desc_avail;
296};
297
298/*
299 * The Receive ring, one per rx queue
300 */
301struct rx_ring {
302 struct adapter *adapter;
303 u32 me;
304 u32 msix;
305 u32 ims;
306 struct mtx rx_mtx;
307 char mtx_name[16];
308 u32 payload;
309 struct task rx_task;
310 struct taskqueue *tq;
311 struct e1000_rx_desc *rx_base;
312 struct em_dma_alloc rxdma;
313 unsigned int next_to_refresh;
314 unsigned int next_to_check;
315 struct em_buffer *rx_buffers;
316 struct mbuf *fmp;
317 struct mbuf *lmp;
318
319 /* Interrupt resources */
320 void *tag;
321 struct resource *res;
322 bus_dma_tag_t rxtag;
323 bus_dmamap_t rx_sparemap;
324
325 /* Soft stats */
326 u64 rx_irq;
327 u64 rx_packets;
328 u64 rx_bytes;
329};
330
331
285/* Our adapter structure */
286struct adapter {
287 struct ifnet *ifp;
332/* Our adapter structure */
333struct adapter {
334 struct ifnet *ifp;
288#if __FreeBSD_version >= 800000
289 struct buf_ring *br;
290#endif
291 struct e1000_hw hw;
292
293 /* FreeBSD operating-system-specific structures. */
294 struct e1000_osdep osdep;
295 struct device *dev;
296
297 struct resource *memory;
298 struct resource *flash;
335 struct e1000_hw hw;
336
337 /* FreeBSD operating-system-specific structures. */
338 struct e1000_osdep osdep;
339 struct device *dev;
340
341 struct resource *memory;
342 struct resource *flash;
299 struct resource *msix;
343 struct resource *msix_mem;
300
344
301 struct resource *ioport;
302 int io_rid;
345 struct resource *res;
346 void *tag;
347 u32 linkvec;
348 u32 ivars;
303
349
304 /* 82574 may use 3 int vectors */
305 struct resource *res[3];
306 void *tag[3];
307 int rid[3];
308
309 struct ifmedia media;
310 struct callout timer;
350 struct ifmedia media;
351 struct callout timer;
311 struct callout tx_fifo_timer;
312 bool watchdog_check;
313 int watchdog_time;
314 int msi;
352 int msix;
315 int if_flags;
316 int max_frame_size;
317 int min_frame_size;
318 struct mtx core_mtx;
353 int if_flags;
354 int max_frame_size;
355 int min_frame_size;
356 struct mtx core_mtx;
319 struct mtx tx_mtx;
320 struct mtx rx_mtx;
321 int em_insert_vlan_header;
357 int em_insert_vlan_header;
358 u32 ims;
359 bool in_detach;
322
323 /* Task for FAST handling */
324 struct task link_task;
360
361 /* Task for FAST handling */
362 struct task link_task;
325 struct task rxtx_task;
326 struct task rx_task;
327 struct task tx_task;
363 struct task que_task;
328 struct taskqueue *tq; /* private task queue */
329
364 struct taskqueue *tq; /* private task queue */
365
330#if __FreeBSD_version >= 700029
331 eventhandler_tag vlan_attach;
332 eventhandler_tag vlan_detach;
366 eventhandler_tag vlan_attach;
367 eventhandler_tag vlan_detach;
333 u32 num_vlans;
334#endif
335
368
369 u16 num_vlans;
370 u16 num_queues;
371
372 /*
373 * Transmit rings:
374 * Allocated at run time, an array of rings.
375 */
376 struct tx_ring *tx_rings;
377 int num_tx_desc;
378 u32 txd_cmd;
379
380 /*
381 * Receive rings:
382 * Allocated at run time, an array of rings.
383 */
384 struct rx_ring *rx_rings;
385 int num_rx_desc;
386 u32 rx_process_limit;
387
336 /* Management and WOL features */
337 u32 wol;
338 bool has_manage;
339 bool has_amt;
340
341 /* Info about the board itself */
342 uint8_t link_active;
343 uint16_t link_speed;
344 uint16_t link_duplex;
345 uint32_t smartspeed;
346 struct em_int_delay_info tx_int_delay;
347 struct em_int_delay_info tx_abs_int_delay;
348 struct em_int_delay_info rx_int_delay;
349 struct em_int_delay_info rx_abs_int_delay;
350
388 /* Management and WOL features */
389 u32 wol;
390 bool has_manage;
391 bool has_amt;
392
393 /* Info about the board itself */
394 uint8_t link_active;
395 uint16_t link_speed;
396 uint16_t link_duplex;
397 uint32_t smartspeed;
398 struct em_int_delay_info tx_int_delay;
399 struct em_int_delay_info tx_abs_int_delay;
400 struct em_int_delay_info rx_int_delay;
401 struct em_int_delay_info rx_abs_int_delay;
402
351 /*
352 * Transmit definitions
353 *
354 * We have an array of num_tx_desc descriptors (handled
355 * by the controller) paired with an array of tx_buffers
356 * (at tx_buffer_area).
357 * The index of the next available descriptor is next_avail_tx_desc.
358 * The number of remaining tx_desc is num_tx_desc_avail.
359 */
360 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
361 struct e1000_tx_desc *tx_desc_base;
362 uint32_t next_avail_tx_desc;
363 uint32_t next_tx_to_clean;
364 volatile uint16_t num_tx_desc_avail;
365 uint16_t num_tx_desc;
366 uint16_t last_hw_offload;
367 uint32_t txd_cmd;
368 struct em_buffer *tx_buffer_area;
369 bus_dma_tag_t txtag; /* dma tag for tx */
370 uint32_t tx_tso; /* last tx was tso */
371
372 /*
373 * Receive definitions
374 *
375 * we have an array of num_rx_desc rx_desc (handled by the
376 * controller), and paired with an array of rx_buffers
377 * (at rx_buffer_area).
378 * The next pair to check on receive is at offset next_rx_desc_to_check
379 */
380 struct em_dma_alloc rxdma; /* bus_dma glue for rx desc */
381 struct e1000_rx_desc *rx_desc_base;
382 uint32_t next_rx_desc_to_check;
383 uint32_t rx_buffer_len;
384 uint16_t num_rx_desc;
385 int rx_process_limit;
386 struct em_buffer *rx_buffer_area;
387 bus_dma_tag_t rxtag;
388 bus_dmamap_t rx_sparemap;
389
390 /*
391 * First/last mbuf pointers, for
392 * collecting multisegment RX packets.
393 */
394 struct mbuf *fmp;
395 struct mbuf *lmp;
396
397 /* Misc stats maintained by the driver */
398 unsigned long dropped_pkts;
399 unsigned long mbuf_alloc_failed;
400 unsigned long mbuf_cluster_failed;
403 /* Misc stats maintained by the driver */
404 unsigned long dropped_pkts;
405 unsigned long mbuf_alloc_failed;
406 unsigned long mbuf_cluster_failed;
401 unsigned long no_tx_desc_avail1;
402 unsigned long no_tx_desc_avail2;
403 unsigned long no_tx_map_avail;
404 unsigned long no_tx_dma_setup;
407 unsigned long no_tx_map_avail;
408 unsigned long no_tx_dma_setup;
405 unsigned long watchdog_events;
406 unsigned long rx_overruns;
409 unsigned long rx_overruns;
407 unsigned long rx_irq;
408 unsigned long tx_irq;
410 unsigned long watchdog_events;
409 unsigned long link_irq;
410
411 unsigned long link_irq;
412
411 /* 82547 workaround */
412 uint32_t tx_fifo_size;
413 uint32_t tx_fifo_head;
414 uint32_t tx_fifo_head_addr;
415 uint64_t tx_fifo_reset_cnt;
416 uint64_t tx_fifo_wrk_cnt;
417 uint32_t tx_head_addr;
418
419 /* For 82544 PCIX Workaround */
420 boolean_t pcix_82544;
421 boolean_t in_detach;
422
423#ifdef EM_IEEE1588
424 /* IEEE 1588 precision time support */
425 struct cyclecounter cycles;
426 struct nettimer clock;
427 struct nettime_compare compare;
428 struct hwtstamp_ctrl hwtstamp;
429#endif
430
431 struct e1000_hw_stats stats;
432};
433
413 struct e1000_hw_stats stats;
414};
415
434/* ******************************************************************************
416/********************************************************************************
435 * vendor_info_array
436 *
437 * This array contains the list of Subvendor/Subdevice IDs on which the driver
438 * should load.
439 *
417 * vendor_info_array
418 *
419 * This array contains the list of Subvendor/Subdevice IDs on which the driver
420 * should load.
421 *
440 * ******************************************************************************/
422 ********************************************************************************/
441typedef struct _em_vendor_info_t {
442 unsigned int vendor_id;
443 unsigned int device_id;
444 unsigned int subvendor_id;
445 unsigned int subdevice_id;
446 unsigned int index;
447} em_vendor_info_t;
448
449struct em_buffer {
450 int next_eop; /* Index of the desc to watch */
451 struct mbuf *m_head;
452 bus_dmamap_t map; /* bus_dma map for packet */
453};
454
423typedef struct _em_vendor_info_t {
424 unsigned int vendor_id;
425 unsigned int device_id;
426 unsigned int subvendor_id;
427 unsigned int subdevice_id;
428 unsigned int index;
429} em_vendor_info_t;
430
431struct em_buffer {
432 int next_eop; /* Index of the desc to watch */
433 struct mbuf *m_head;
434 bus_dmamap_t map; /* bus_dma map for packet */
435};
436
455/* For 82544 PCIX Workaround */
456typedef struct _ADDRESS_LENGTH_PAIR
457{
458 uint64_t address;
459 uint32_t length;
460} ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
461
462typedef struct _DESCRIPTOR_PAIR
463{
464 ADDRESS_LENGTH_PAIR descriptor[4];
465 uint32_t elements;
466} DESC_ARRAY, *PDESC_ARRAY;
467
468#define EM_CORE_LOCK_INIT(_sc, _name) \
469 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
470#define EM_TX_LOCK_INIT(_sc, _name) \
471 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
472#define EM_RX_LOCK_INIT(_sc, _name) \
473 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
474#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
475#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)

--- 12 unchanged lines hidden --- 		437#define EM_CORE_LOCK_INIT(_sc, _name) \
438 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
439#define EM_TX_LOCK_INIT(_sc, _name) \
440 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
441#define EM_RX_LOCK_INIT(_sc, _name) \
442 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
443#define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx)
444#define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx)

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