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if_em.h (191611) if_em.h (194865)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/if_em.h 191611 2009-04-27 22:55:48Z kmacy $*/
33/*$FreeBSD: head/sys/dev/e1000/if_em.h 194865 2009-06-24 17:41:29Z jfv $*/
34
35
36#ifndef _EM_H_DEFINED_
37#define _EM_H_DEFINED_
38
34
35
36#ifndef _EM_H_DEFINED_
37#define _EM_H_DEFINED_
38
39#define IFNET_BUF_RING
39
40/* Tunables */
41
42/*
43 * EM_TXD: Maximum number of Transmit Descriptors
44 * Valid Range: 80-256 for 82542 and 82543-based adapters
45 * 80-4096 for others
46 * Default Value: 256
47 * This value is the number of transmit descriptors allocated by the driver.

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227#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
228#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
229#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
230#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
231#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
232#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
233
234#define EM_MAX_SCATTER 64
40/* Tunables */
41
42/*
43 * EM_TXD: Maximum number of Transmit Descriptors
44 * Valid Range: 80-256 for 82542 and 82543-based adapters
45 * 80-4096 for others
46 * Default Value: 256
47 * This value is the number of transmit descriptors allocated by the driver.

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227#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
228#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
229#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
230#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
231#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
232#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
233
234#define EM_MAX_SCATTER 64
235#define EM_VFTA_SIZE 128
235#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
236#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
237#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
238#define ETH_ZLEN 60
239#define ETH_ADDR_LEN 6
240#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
241
242/*

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249
250/* Used in for 82547 10Mb Half workaround */
251#define EM_PBA_BYTES_SHIFT 0xA
252#define EM_TX_HEAD_ADDR_SHIFT 7
253#define EM_PBA_TX_MASK 0xFFFF0000
254#define EM_FIFO_HDR 0x10
255#define EM_82547_PKT_THRESH 0x3e0
256
236#define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header))
237#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
238#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */
239#define ETH_ZLEN 60
240#define ETH_ADDR_LEN 6
241#define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */
242
243/*

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250
251/* Used in for 82547 10Mb Half workaround */
252#define EM_PBA_BYTES_SHIFT 0xA
253#define EM_TX_HEAD_ADDR_SHIFT 7
254#define EM_PBA_TX_MASK 0xFFFF0000
255#define EM_FIFO_HDR 0x10
256#define EM_82547_PKT_THRESH 0x3e0
257
257#ifdef EM_TIMESYNC
258/* Precision Time Sync (IEEE 1588) defines */
259#define ETHERTYPE_IEEE1588 0x88F7
260#define PICOSECS_PER_TICK 20833
261#define TSYNC_PORT 319 /* UDP port for the protocol */
262
258/* Precision Time Sync (IEEE 1588) defines */
259#define ETHERTYPE_IEEE1588 0x88F7
260#define PICOSECS_PER_TICK 20833
261#define TSYNC_PORT 319 /* UDP port for the protocol */
262
263/* TIMESYNC IOCTL defines */
264#define EM_TIMESYNC_READTS _IOWR('i', 127, struct em_tsync_read)
265
266/* Used in the READTS IOCTL */
267struct em_tsync_read {
268 int read_current_time;
269 struct timespec system_time;
270 u64 network_time;
271 u64 rx_stamp;
272 u64 tx_stamp;
273 u16 seqid;
274 unsigned char srcid[6];
275 int rx_valid;
276 int tx_valid;
277};
278
279#endif /* EM_TIMESYNC */
280
281struct adapter;
282
283struct em_int_delay_info {
284 struct adapter *adapter; /* Back-pointer to the adapter struct */
285 int offset; /* Register offset to read/write */
286 int value; /* Current value in usecs */
287};
288
289/*
290 * Bus dma allocation structure used by
291 * e1000_dma_malloc and e1000_dma_free.
292 */
293struct em_dma_alloc {
294 bus_addr_t dma_paddr;
295 caddr_t dma_vaddr;
296 bus_dma_tag_t dma_tag;
297 bus_dmamap_t dma_map;
298 bus_dma_segment_t dma_seg;
299 int dma_nseg;
300};
301
263/*
264 * Bus dma allocation structure used by
265 * e1000_dma_malloc and e1000_dma_free.
266 */
267struct em_dma_alloc {
268 bus_addr_t dma_paddr;
269 caddr_t dma_vaddr;
270 bus_dma_tag_t dma_tag;
271 bus_dmamap_t dma_map;
272 bus_dma_segment_t dma_seg;
273 int dma_nseg;
274};
275
276struct adapter;
277
278struct em_int_delay_info {
279 struct adapter *adapter; /* Back-pointer to the adapter struct */
280 int offset; /* Register offset to read/write */
281 int value; /* Current value in usecs */
282};
283
302/* Our adapter structure */
303struct adapter {
304 struct ifnet *ifp;
284/* Our adapter structure */
285struct adapter {
286 struct ifnet *ifp;
305#ifdef IFNET_BUF_RING
287#if __FreeBSD_version >= 800000
306 struct buf_ring *br;
288 struct buf_ring *br;
307#else
308 void *br;
309#endif
310 struct e1000_hw hw;
311
312 /* FreeBSD operating-system-specific structures. */
313 struct e1000_osdep osdep;
314 struct device *dev;
315
316 struct resource *memory;
317 struct resource *flash;
318 struct resource *msix;
319
320 struct resource *ioport;
321 int io_rid;
322
289#endif
290 struct e1000_hw hw;
291
292 /* FreeBSD operating-system-specific structures. */
293 struct e1000_osdep osdep;
294 struct device *dev;
295
296 struct resource *memory;
297 struct resource *flash;
298 struct resource *msix;
299
300 struct resource *ioport;
301 int io_rid;
302
323 /* 82574 uses 3 int vectors */
303 /* 82574 may use 3 int vectors */
324 struct resource *res[3];
325 void *tag[3];
326 int rid[3];
327
328 struct ifmedia media;
329 struct callout timer;
330 struct callout tx_fifo_timer;
331 int watchdog_timer;

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340
341 /* Task for FAST handling */
342 struct task link_task;
343 struct task rxtx_task;
344 struct task rx_task;
345 struct task tx_task;
346 struct taskqueue *tq; /* private task queue */
347
304 struct resource *res[3];
305 void *tag[3];
306 int rid[3];
307
308 struct ifmedia media;
309 struct callout timer;
310 struct callout tx_fifo_timer;
311 int watchdog_timer;

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320
321 /* Task for FAST handling */
322 struct task link_task;
323 struct task rxtx_task;
324 struct task rx_task;
325 struct task tx_task;
326 struct taskqueue *tq; /* private task queue */
327
328#if __FreeBSD_version >= 700029
348 eventhandler_tag vlan_attach;
349 eventhandler_tag vlan_detach;
329 eventhandler_tag vlan_attach;
330 eventhandler_tag vlan_detach;
331 u32 num_vlans;
332#endif
350
351 /* Management and WOL features */
352 int wol;
353 int has_manage;
354
355 /* Info about the board itself */
356 uint8_t link_active;
357 uint16_t link_speed;

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372 * The number of remaining tx_desc is num_tx_desc_avail.
373 */
374 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
375 struct e1000_tx_desc *tx_desc_base;
376 uint32_t next_avail_tx_desc;
377 uint32_t next_tx_to_clean;
378 volatile uint16_t num_tx_desc_avail;
379 uint16_t num_tx_desc;
333
334 /* Management and WOL features */
335 int wol;
336 int has_manage;
337
338 /* Info about the board itself */
339 uint8_t link_active;
340 uint16_t link_speed;

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355 * The number of remaining tx_desc is num_tx_desc_avail.
356 */
357 struct em_dma_alloc txdma; /* bus_dma glue for tx desc */
358 struct e1000_tx_desc *tx_desc_base;
359 uint32_t next_avail_tx_desc;
360 uint32_t next_tx_to_clean;
361 volatile uint16_t num_tx_desc_avail;
362 uint16_t num_tx_desc;
363 uint16_t last_hw_offload;
380 uint32_t txd_cmd;
381 struct em_buffer *tx_buffer_area;
382 bus_dma_tag_t txtag; /* dma tag for tx */
383 uint32_t tx_tso; /* last tx was tso */
384
385 /*
386 * Receive definitions
387 *

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428 uint64_t tx_fifo_reset_cnt;
429 uint64_t tx_fifo_wrk_cnt;
430 uint32_t tx_head_addr;
431
432 /* For 82544 PCIX Workaround */
433 boolean_t pcix_82544;
434 boolean_t in_detach;
435
364 uint32_t txd_cmd;
365 struct em_buffer *tx_buffer_area;
366 bus_dma_tag_t txtag; /* dma tag for tx */
367 uint32_t tx_tso; /* last tx was tso */
368
369 /*
370 * Receive definitions
371 *

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412 uint64_t tx_fifo_reset_cnt;
413 uint64_t tx_fifo_wrk_cnt;
414 uint32_t tx_head_addr;
415
416 /* For 82544 PCIX Workaround */
417 boolean_t pcix_82544;
418 boolean_t in_detach;
419
436#ifdef EM_TIMESYNC
437 u64 last_stamp;
438 u64 last_sec;
439 u32 last_ns;
440#endif
441
442 struct e1000_hw_stats stats;
443};
444
445/* ******************************************************************************
446 * vendor_info_array
447 *
448 * This array contains the list of Subvendor/Subdevice IDs on which the driver
449 * should load.
450 *
451 * ******************************************************************************/
452typedef struct _em_vendor_info_t {
453 unsigned int vendor_id;
454 unsigned int device_id;
455 unsigned int subvendor_id;
456 unsigned int subdevice_id;
457 unsigned int index;
458} em_vendor_info_t;
459
420
421 struct e1000_hw_stats stats;
422};
423
424/* ******************************************************************************
425 * vendor_info_array
426 *
427 * This array contains the list of Subvendor/Subdevice IDs on which the driver
428 * should load.
429 *
430 * ******************************************************************************/
431typedef struct _em_vendor_info_t {
432 unsigned int vendor_id;
433 unsigned int device_id;
434 unsigned int subvendor_id;
435 unsigned int subdevice_id;
436 unsigned int index;
437} em_vendor_info_t;
438
460
461struct em_buffer {
462 int next_eop; /* Index of the desc to watch */
463 struct mbuf *m_head;
464 bus_dmamap_t map; /* bus_dma map for packet */
465};
466
467/* For 82544 PCIX Workaround */
468typedef struct _ADDRESS_LENGTH_PAIR

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491#define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
492#define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
493#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
494#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
495#define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
496#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
497#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
498
439struct em_buffer {
440 int next_eop; /* Index of the desc to watch */
441 struct mbuf *m_head;
442 bus_dmamap_t map; /* bus_dma map for packet */
443};
444
445/* For 82544 PCIX Workaround */
446typedef struct _ADDRESS_LENGTH_PAIR

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469#define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx)
470#define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx)
471#define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx)
472#define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx)
473#define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx)
474#define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED)
475#define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
476
499#ifdef IFNET_BUF_RING
500#define ADAPTER_RING_EMPTY(adapter) drbr_empty((adapter)->ifp, (adapter)->br)
501#define em_dequeue drbr_dequeue
502
503#else
504#define ADAPTER_RING_EMPTY(adapter) IFQ_DRV_IS_EMPTY(&((adapter)->ifp->if_snd))
505#define drbr_free(br, type)
506static __inline struct mbuf *
507em_dequeue(struct ifnet *ifp, struct buf_ring *br)
508{
509 struct mbuf *m;
510
511 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
512 return (m);
513}
514#ifdef BUF_RING_UNDEFINED
515
516struct buf_ring {
517};
518
519#endif
520#endif
521
522#endif /* _EM_H_DEFINED_ */
477#endif /* _EM_H_DEFINED_ */