| e1000_regs.h (235527) | e1000_regs.h (238262) |
|---|---|
| 1/****************************************************************************** 2 | 1/****************************************************************************** 2 |
| 3 Copyright (c) 2001-2011, Intel Corporation | 3 Copyright (c) 2001-2012, Intel Corporation |
| 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 13 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 13 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: stable/9/sys/dev/e1000/e1000_regs.h 235527 2012-05-16 22:22:52Z jfv $*/ | 33/*$FreeBSD: stable/9/sys/dev/e1000/e1000_regs.h 238262 2012-07-08 20:35:56Z jfv $*/ |
| 34 35#ifndef _E1000_REGS_H_ 36#define _E1000_REGS_H_ 37 38#define E1000_CTRL 0x00000 /* Device Control - RW */ 39#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 40#define E1000_STATUS 0x00008 /* Device Status - RO */ 41#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ --- 4 unchanged lines hidden (view full) --- 46#define E1000_MDICNFG 0x00E04 /* MDI Config - RW */ 47#define E1000_REGISTER_SET_SIZE 0x20000 /* CSR Size */ 48#define E1000_EEPROM_INIT_CTRL_WORD_2 0x0F /* EEPROM Init Ctrl Word 2 */ 49#define E1000_EEPROM_PCIE_CTRL_WORD_2 0x28 /* EEPROM PCIe Ctrl Word 2 */ 50#define E1000_BARCTRL 0x5BBC /* BAR ctrl reg */ 51#define E1000_BARCTRL_FLSIZE 0x0700 /* BAR ctrl Flsize */ 52#define E1000_BARCTRL_CSRSIZE 0x2000 /* BAR ctrl CSR size */ 53#define E1000_I350_BARCTRL 0x5BFC /* BAR ctrl reg */ | 34 35#ifndef _E1000_REGS_H_ 36#define _E1000_REGS_H_ 37 38#define E1000_CTRL 0x00000 /* Device Control - RW */ 39#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 40#define E1000_STATUS 0x00008 /* Device Status - RO */ 41#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ --- 4 unchanged lines hidden (view full) --- 46#define E1000_MDICNFG 0x00E04 /* MDI Config - RW */ 47#define E1000_REGISTER_SET_SIZE 0x20000 /* CSR Size */ 48#define E1000_EEPROM_INIT_CTRL_WORD_2 0x0F /* EEPROM Init Ctrl Word 2 */ 49#define E1000_EEPROM_PCIE_CTRL_WORD_2 0x28 /* EEPROM PCIe Ctrl Word 2 */ 50#define E1000_BARCTRL 0x5BBC /* BAR ctrl reg */ 51#define E1000_BARCTRL_FLSIZE 0x0700 /* BAR ctrl Flsize */ 52#define E1000_BARCTRL_CSRSIZE 0x2000 /* BAR ctrl CSR size */ 53#define E1000_I350_BARCTRL 0x5BFC /* BAR ctrl reg */ |
| 54#define E1000_I350_DTXMXPKTSZ 0x355C /* Maximum sent packet size reg*/ |
|
| 54#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 55#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 56#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 57#define E1000_FEXT 0x0002C /* Future Extended - RW */ 58#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ 59#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ 60#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 61#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ --- 76 unchanged lines hidden (view full) --- 138#define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */ 139#define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */ 140#define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */ 141#define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ 142#define E1000_IRPBS 0x02404 /* Same as RXPBS, renamed for newer Si - RW */ 143#define E1000_PBRWAC 0x024E8 /* Rx packet buffer wrap around counter - RO */ 144#define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ 145#define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ | 55#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 56#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 57#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 58#define E1000_FEXT 0x0002C /* Future Extended - RW */ 59#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ 60#define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ 61#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 62#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ --- 76 unchanged lines hidden (view full) --- 139#define E1000_RDPURD 0x025D8 /* DMA Rx Descriptor uC Data Read - RW */ 140#define E1000_RDPUCTL 0x025DC /* DMA Rx Descriptor uC Control - RW */ 141#define E1000_PBDIAG 0x02458 /* Packet Buffer Diagnostic - RW */ 142#define E1000_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */ 143#define E1000_IRPBS 0x02404 /* Same as RXPBS, renamed for newer Si - RW */ 144#define E1000_PBRWAC 0x024E8 /* Rx packet buffer wrap around counter - RO */ 145#define E1000_RDTR 0x02820 /* Rx Delay Timer - RW */ 146#define E1000_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */ |
| 147#define E1000_SRWR 0x12018 /* Shadow Ram Write Register - RW */ 148#define E1000_I210_FLMNGCTL 0x12038 149#define E1000_I210_FLMNGDATA 0x1203C 150#define E1000_I210_FLMNGCNT 0x12040 151 152#define E1000_I210_FLSWCTL 0x12048 153#define E1000_I210_FLSWDATA 0x1204C 154#define E1000_I210_FLSWCNT 0x12050 155 156#define E1000_I210_FLA 0x1201C 157 158#define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n)) 159#define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */ 160 161/* QAV Tx mode control register */ 162#define E1000_I210_TQAVCTRL 0x3570 163 164/* QAV Tx mode control register bitfields masks */ 165/* QAV enable */ 166#define E1000_TQAVCTRL_MODE (1 << 0) 167/* Fetching arbitration type */ 168#define E1000_TQAVCTRL_FETCH_ARB (1 << 4) 169/* Fetching timer enable */ 170#define E1000_TQAVCTRL_FETCH_TIMER_ENABLE (1 << 5) 171/* Launch arbitration type */ 172#define E1000_TQAVCTRL_LAUNCH_ARB (1 << 8) 173/* Launch timer enable */ 174#define E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE (1 << 9) 175/* SP waits for SR enable */ 176#define E1000_TQAVCTRL_SP_WAIT_SR (1 << 10) 177/* Fetching timer correction */ 178#define E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET 16 179#define E1000_TQAVCTRL_FETCH_TIMER_DELTA \ 180 (0xFFFF << E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET) 181 182/* High credit registers where _n can be 0 or 1. */ 183#define E1000_I210_TQAVHC(_n) (0x300C + 0x40 * (_n)) 184 185/* Queues fetch arbitration priority control register */ 186#define E1000_I210_TQAVARBCTRL 0x3574 187/* Queues priority masks where _n and _p can be 0-3. */ 188#define E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p) ((_p) << (2 * _n)) 189/* QAV Tx mode control registers where _n can be 0 or 1. */ 190#define E1000_I210_TQAVCC(_n) (0x3004 + 0x40 * (_n)) 191 192/* QAV Tx mode control register bitfields masks */ 193#define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */ 194#define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */ 195#define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */ 196 197/* Good transmitted packets counter registers */ 198#define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n))) 199 200/* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */ 201#define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * _n)) 202 |
|
| 146/* 147 * Convenience macros 148 * 149 * Note: "_n" is the queue number of the register to be written to. 150 * 151 * Example usage: 152 * E1000_RDBAL_REG(current_rx_queue) 153 */ --- 265 unchanged lines hidden (view full) --- 419#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 420#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 421#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 422#define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */ 423#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 424#define E1000_HOST_IF 0x08800 /* Host Interface */ 425#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 426#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ | 203/* 204 * Convenience macros 205 * 206 * Note: "_n" is the queue number of the register to be written to. 207 * 208 * Example usage: 209 * E1000_RDBAL_REG(current_rx_queue) 210 */ --- 265 unchanged lines hidden (view full) --- 476#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 477#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 478#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 479#define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */ 480#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 481#define E1000_HOST_IF 0x08800 /* Host Interface */ 482#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 483#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ |
| 484#define E1000_HIBBA 0x8F40 /* Host Interface Buffer Base Address */ |
|
| 427/* Flexible Host Filter Table */ | 485/* Flexible Host Filter Table */ |
| 428#define E1000_FHFT(_n) (0x09000 + (_n * 0x100)) | 486#define E1000_FHFT(_n) (0x09000 + ((_n) * 0x100)) |
| 429/* Ext Flexible Host Filter Table */ | 487/* Ext Flexible Host Filter Table */ |
| 430#define E1000_FHFT_EXT(_n) (0x09A00 + (_n * 0x100)) | 488#define E1000_FHFT_EXT(_n) (0x09A00 + ((_n) * 0x100)) |
| 431 432 433#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 434#define E1000_MDPHYA 0x0003C /* PHY address - RW */ 435#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ 436/* Management Decision Filters */ 437#define E1000_MDEF(_n) (0x05890 + (4 * (_n))) 438#define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */ --- 146 unchanged lines hidden (view full) --- 585#define E1000_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */ 586#define E1000_DMCCNT 0x05DD4 /* Current Rx Count */ 587#define E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */ 588#define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */ 589 590/* PCIe Parity Status Register */ 591#define E1000_PCIEERRSTS 0x05BA8 592 | 489 490 491#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 492#define E1000_MDPHYA 0x0003C /* PHY address - RW */ 493#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ 494/* Management Decision Filters */ 495#define E1000_MDEF(_n) (0x05890 + (4 * (_n))) 496#define E1000_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */ --- 146 unchanged lines hidden (view full) --- 643#define E1000_DMCRTRH 0x05DD0 /* Receive Packet Rate Threshold */ 644#define E1000_DMCCNT 0x05DD4 /* Current Rx Count */ 645#define E1000_FCRTC 0x02170 /* Flow Control Rx high watermark */ 646#define E1000_PCIEMISC 0x05BB8 /* PCIE misc config register */ 647 648/* PCIe Parity Status Register */ 649#define E1000_PCIEERRSTS 0x05BA8 650 |
| 593#define E1000_LTRMINV 0x5BB0 /* LTR Minimum Value */ 594#define E1000_LTRMAXV 0x5BB4 /* LTR Maximum Value */ 595#define E1000_DOBFFCTL 0x3F24 /* DMA OBFF Control Register */ 596 | |
| 597#define E1000_PROXYS 0x5F64 /* Proxying Status */ 598#define E1000_PROXYFC 0x5F60 /* Proxying Filter Control */ 599/* Thermal sensor configuration and status registers */ 600#define E1000_THMJT 0x08100 /* Junction Temperature */ 601#define E1000_THLOWTC 0x08104 /* Low Threshold Control */ 602#define E1000_THMIDTC 0x08108 /* Mid Threshold Control */ 603#define E1000_THHIGHTC 0x0810C /* High Threshold Control */ 604#define E1000_THSTAT 0x08110 /* Thermal Sensor Status */ 605 | 651#define E1000_PROXYS 0x5F64 /* Proxying Status */ 652#define E1000_PROXYFC 0x5F60 /* Proxying Filter Control */ 653/* Thermal sensor configuration and status registers */ 654#define E1000_THMJT 0x08100 /* Junction Temperature */ 655#define E1000_THLOWTC 0x08104 /* Low Threshold Control */ 656#define E1000_THMIDTC 0x08108 /* Mid Threshold Control */ 657#define E1000_THHIGHTC 0x0810C /* High Threshold Control */ 658#define E1000_THSTAT 0x08110 /* Thermal Sensor Status */ 659 |
| 606/*Energy Efficient Ethernet "EEE" registers */ | 660/* Energy Efficient Ethernet "EEE" registers */ |
| 607#define E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */ 608#define E1000_LTRC 0x01A0 /* Latency Tolerance Reporting Control */ 609#define E1000_EEER 0x0E30 /* Energy Efficient Ethernet "EEE"*/ 610#define E1000_EEE_SU 0x0E34 /* EEE Setup */ 611#define E1000_TLPIC 0x4148 /* EEE Tx LPI Count - TLPIC */ 612#define E1000_RLPIC 0x414C /* EEE Rx LPI Count - RLPIC */ 613 614/* OS2BMC Registers */ 615#define E1000_B2OSPC 0x08FE0 /* BMC2OS packets sent by BMC */ 616#define E1000_B2OGPRC 0x04158 /* BMC2OS packets received by host */ 617#define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */ 618#define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */ 619 | 661#define E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */ 662#define E1000_LTRC 0x01A0 /* Latency Tolerance Reporting Control */ 663#define E1000_EEER 0x0E30 /* Energy Efficient Ethernet "EEE"*/ 664#define E1000_EEE_SU 0x0E34 /* EEE Setup */ 665#define E1000_TLPIC 0x4148 /* EEE Tx LPI Count - TLPIC */ 666#define E1000_RLPIC 0x414C /* EEE Rx LPI Count - RLPIC */ 667 668/* OS2BMC Registers */ 669#define E1000_B2OSPC 0x08FE0 /* BMC2OS packets sent by BMC */ 670#define E1000_B2OGPRC 0x04158 /* BMC2OS packets received by host */ 671#define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */ 672#define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */ 673 |
| 674#define E1000_LTRMINV 0x5BB0 /* LTR Minimum Value */ 675#define E1000_LTRMAXV 0x5BB4 /* LTR Maximum Value */ 676#define E1000_DOBFFCTL 0x3F24 /* DMA OBFF Control Register */ 677 678 |
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| 620#endif | 679#endif |