| e1000_regs.h (203049) | e1000_regs.h (205869) |
|---|---|
| 1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/e1000/e1000_regs.h 203049 2010-01-26 22:32:22Z jfv $*/ | 33/*$FreeBSD: head/sys/dev/e1000/e1000_regs.h 205869 2010-03-29 23:36:34Z jfv $*/ |
| 34 35#ifndef _E1000_REGS_H_ 36#define _E1000_REGS_H_ 37 38#define E1000_CTRL 0x00000 /* Device Control - RW */ 39#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 40#define E1000_STATUS 0x00008 /* Device Status - RO */ 41#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ --- 18 unchanged lines hidden (view full) --- 60#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 61#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 62#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 63#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 64#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 65#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 66#define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ 67#define E1000_SVCR 0x000F0 | 34 35#ifndef _E1000_REGS_H_ 36#define _E1000_REGS_H_ 37 38#define E1000_CTRL 0x00000 /* Device Control - RW */ 39#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 40#define E1000_STATUS 0x00008 /* Device Status - RO */ 41#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ --- 18 unchanged lines hidden (view full) --- 60#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 61#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 62#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 63#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 64#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 65#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 66#define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ 67#define E1000_SVCR 0x000F0 |
| 68#define E1000_SVT 0x000F4 | 68#define E1000_SVT 0x000F4 |
| 69#define E1000_RCTL 0x00100 /* Rx Control - RW */ 70#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 71#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ 72#define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ 73#define E1000_PBA_ECC 0x01100 /* PBA ECC Register */ 74#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 75#define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) 76#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ --- 200 unchanged lines hidden (view full) --- 277#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ 278#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ 279#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 280#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ 281#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ 282#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 283#define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */ 284 | 69#define E1000_RCTL 0x00100 /* Rx Control - RW */ 70#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 71#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ 72#define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ 73#define E1000_PBA_ECC 0x01100 /* PBA ECC Register */ 74#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 75#define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) 76#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ --- 200 unchanged lines hidden (view full) --- 277#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ 278#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */ 279#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 280#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */ 281#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */ 282#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 283#define E1000_CRC_OFFSET 0x05F50 /* CRC Offset register */ 284 |
| 285/* Virtualization statistical counters */ 286#define E1000_PFVFGPRC(_n) (0x010010 + (0x100 * (_n))) 287#define E1000_PFVFGPTC(_n) (0x010014 + (0x100 * (_n))) 288#define E1000_PFVFGORC(_n) (0x010018 + (0x100 * (_n))) 289#define E1000_PFVFGOTC(_n) (0x010034 + (0x100 * (_n))) 290#define E1000_PFVFMPRC(_n) (0x010038 + (0x100 * (_n))) 291#define E1000_PFVFGPRLBC(_n) (0x010040 + (0x100 * (_n))) 292#define E1000_PFVFGPTLBC(_n) (0x010044 + (0x100 * (_n))) 293#define E1000_PFVFGORLBC(_n) (0x010048 + (0x100 * (_n))) 294#define E1000_PFVFGOTLBC(_n) (0x010050 + (0x100 * (_n))) 295 |
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| 285#define E1000_LSECTXUT 0x04300 /* LinkSec Tx Untagged Packet Count - OutPktsUntagged */ 286#define E1000_LSECTXPKTE 0x04304 /* LinkSec Encrypted Tx Packets Count - OutPktsEncrypted */ 287#define E1000_LSECTXPKTP 0x04308 /* LinkSec Protected Tx Packet Count - OutPktsProtected */ 288#define E1000_LSECTXOCTE 0x0430C /* LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted */ 289#define E1000_LSECTXOCTP 0x04310 /* LinkSec Protected Tx Octets Count - OutOctetsProtected */ 290#define E1000_LSECRXUT 0x04314 /* LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag */ 291#define E1000_LSECRXOCTD 0x0431C /* LinkSec Rx Octets Decrypted Count - InOctetsDecrypted */ 292#define E1000_LSECRXOCTV 0x04320 /* LinkSec Rx Octets Validated - InOctetsValidated */ --- 88 unchanged lines hidden (view full) --- 381#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 382#define E1000_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flexible Host Filter Table */ 383#define E1000_FHFT_EXT(_n) (0x09A00 + (_n * 0x100)) /* Ext Flexible Host Filter Table */ 384 385 386#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 387#define E1000_MDPHYA 0x0003C /* PHY address - RW */ 388#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ | 296#define E1000_LSECTXUT 0x04300 /* LinkSec Tx Untagged Packet Count - OutPktsUntagged */ 297#define E1000_LSECTXPKTE 0x04304 /* LinkSec Encrypted Tx Packets Count - OutPktsEncrypted */ 298#define E1000_LSECTXPKTP 0x04308 /* LinkSec Protected Tx Packet Count - OutPktsProtected */ 299#define E1000_LSECTXOCTE 0x0430C /* LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted */ 300#define E1000_LSECTXOCTP 0x04310 /* LinkSec Protected Tx Octets Count - OutOctetsProtected */ 301#define E1000_LSECRXUT 0x04314 /* LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag */ 302#define E1000_LSECRXOCTD 0x0431C /* LinkSec Rx Octets Decrypted Count - InOctetsDecrypted */ 303#define E1000_LSECRXOCTV 0x04320 /* LinkSec Rx Octets Validated - InOctetsValidated */ --- 88 unchanged lines hidden (view full) --- 392#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 393#define E1000_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flexible Host Filter Table */ 394#define E1000_FHFT_EXT(_n) (0x09A00 + (_n * 0x100)) /* Ext Flexible Host Filter Table */ 395 396 397#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 398#define E1000_MDPHYA 0x0003C /* PHY address - RW */ 399#define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ |
| 400#define E1000_MDEF(_n) (0x05890 + (4 * (_n))) /* Mngmt Decision Filters */ |
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| 389#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 390#define E1000_CCMCTL 0x05B48 /* CCM Control Register */ 391#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ 392#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ 393#define E1000_GCR 0x05B00 /* PCI-Ex Control */ 394#define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ 395#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 396#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ --- 125 unchanged lines hidden --- | 401#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 402#define E1000_CCMCTL 0x05B48 /* CCM Control Register */ 403#define E1000_GIOCTL 0x05B44 /* GIO Analog Control Register */ 404#define E1000_SCCTL 0x05B4C /* PCIc PLL Configuration Register */ 405#define E1000_GCR 0x05B00 /* PCI-Ex Control */ 406#define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ 407#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 408#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ --- 125 unchanged lines hidden --- |