| e1000_regs.h (190872) | e1000_regs.h (194865) |
|---|---|
| 1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/e1000/e1000_regs.h 190872 2009-04-10 00:05:46Z jfv $*/ | 33/*$FreeBSD: head/sys/dev/e1000/e1000_regs.h 194865 2009-06-24 17:41:29Z jfv $*/ |
| 34 35#ifndef _E1000_REGS_H_ 36#define _E1000_REGS_H_ 37 38#define E1000_CTRL 0x00000 /* Device Control - RW */ 39#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 40#define E1000_STATUS 0x00008 /* Device Status - RO */ 41#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ --- 11 unchanged lines hidden (view full) --- 53#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 54#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 55#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 56#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 57#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 58#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 59#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 60#define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ | 34 35#ifndef _E1000_REGS_H_ 36#define _E1000_REGS_H_ 37 38#define E1000_CTRL 0x00000 /* Device Control - RW */ 39#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 40#define E1000_STATUS 0x00008 /* Device Status - RO */ 41#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ --- 11 unchanged lines hidden (view full) --- 53#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 54#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 55#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 56#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 57#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 58#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 59#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 60#define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ |
| 61#define E1000_SVCR 0x000F0 62#define E1000_SVT 0x000F4 |
|
| 61#define E1000_RCTL 0x00100 /* Rx Control - RW */ 62#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 63#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ 64#define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ 65#define E1000_PBA_ECC 0x01100 /* PBA ECC Register */ 66#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 67#define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) 68#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ --- 313 unchanged lines hidden (view full) --- 382#define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ 383#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 384#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ 385#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 386#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 387#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 388#define E1000_SWSM 0x05B50 /* SW Semaphore */ 389#define E1000_FWSM 0x05B54 /* FW Semaphore */ | 63#define E1000_RCTL 0x00100 /* Rx Control - RW */ 64#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 65#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */ 66#define E1000_RXCW 0x00180 /* Rx Configuration Word - RO */ 67#define E1000_PBA_ECC 0x01100 /* PBA ECC Register */ 68#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 69#define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) 70#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ --- 313 unchanged lines hidden (view full) --- 384#define E1000_GCR2 0x05B64 /* PCI-Ex Control #2 */ 385#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 386#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ 387#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 388#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 389#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 390#define E1000_SWSM 0x05B50 /* SW Semaphore */ 391#define E1000_FWSM 0x05B54 /* FW Semaphore */ |
| 392#define E1000_SWSM2 0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */ |
|
| 390#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ 391#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ 392#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 393#define E1000_HICR 0x08F00 /* Host Interface Control */ 394 395/* RSS registers */ 396#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ 397#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ --- 52 unchanged lines hidden (view full) --- 450#define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ 451#define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ 452 453/* Filtering Registers */ 454#define E1000_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */ 455#define E1000_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */ 456#define E1000_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */ 457#define E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */ | 393#define E1000_DCA_ID 0x05B70 /* DCA Requester ID Information - RO */ 394#define E1000_DCA_CTRL 0x05B74 /* DCA Control - RW */ 395#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 396#define E1000_HICR 0x08F00 /* Host Interface Control */ 397 398/* RSS registers */ 399#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ 400#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ --- 52 unchanged lines hidden (view full) --- 453#define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - RW */ 454#define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ 455 456/* Filtering Registers */ 457#define E1000_SAQF(_n) (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */ 458#define E1000_DAQF(_n) (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */ 459#define E1000_SPQF(_n) (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */ 460#define E1000_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */ |
| 461#define E1000_TTQF(_n) (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */ |
|
| 458#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */ 459#define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */ 460 461#define E1000_RTTDCS 0x3600 /* Reedtown Tx Desc plane control and status */ 462#define E1000_RTTPCS 0x3474 /* Reedtown Tx Packet Plane control and status */ 463#define E1000_RTRPCS 0x2474 /* Rx packet plane control and status */ 464#define E1000_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */ 465#define E1000_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class */ --- 27 unchanged lines hidden --- | 462#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */ 463#define E1000_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */ 464 465#define E1000_RTTDCS 0x3600 /* Reedtown Tx Desc plane control and status */ 466#define E1000_RTTPCS 0x3474 /* Reedtown Tx Packet Plane control and status */ 467#define E1000_RTRPCS 0x2474 /* Rx packet plane control and status */ 468#define E1000_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */ 469#define E1000_RTTUP2TC 0x0418 /* Transmit User Priority to Traffic Class */ --- 27 unchanged lines hidden --- |