| e1000_phy.h (235527) | e1000_phy.h (238262) |
|---|---|
| 1/****************************************************************************** 2 | 1/****************************************************************************** 2 |
| 3 Copyright (c) 2001-2011, Intel Corporation | 3 Copyright (c) 2001-2012, Intel Corporation |
| 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 13 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 13 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: stable/9/sys/dev/e1000/e1000_phy.h 235527 2012-05-16 22:22:52Z jfv $*/ | 33/*$FreeBSD: stable/9/sys/dev/e1000/e1000_phy.h 238262 2012-07-08 20:35:56Z jfv $*/ |
| 34 35#ifndef _E1000_PHY_H_ 36#define _E1000_PHY_H_ 37 38void e1000_init_phy_ops_generic(struct e1000_hw *hw); 39s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data); 40void e1000_null_phy_generic(struct e1000_hw *hw); 41s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active); 42s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data); 43s32 e1000_null_set_page(struct e1000_hw *hw, u16 data); | 34 35#ifndef _E1000_PHY_H_ 36#define _E1000_PHY_H_ 37 38void e1000_init_phy_ops_generic(struct e1000_hw *hw); 39s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data); 40void e1000_null_phy_generic(struct e1000_hw *hw); 41s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active); 42s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data); 43s32 e1000_null_set_page(struct e1000_hw *hw, u16 data); |
| 44s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset, 45 u8 dev_addr, u8 *data); 46s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset, 47 u8 dev_addr, u8 data); |
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| 44s32 e1000_check_downshift_generic(struct e1000_hw *hw); 45s32 e1000_check_polarity_m88(struct e1000_hw *hw); 46s32 e1000_check_polarity_igp(struct e1000_hw *hw); 47s32 e1000_check_polarity_ife(struct e1000_hw *hw); 48s32 e1000_check_reset_block_generic(struct e1000_hw *hw); 49s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 50s32 e1000_copper_link_autoneg(struct e1000_hw *hw); 51s32 e1000_copper_link_setup_igp(struct e1000_hw *hw); --- 55 unchanged lines hidden (view full) --- 107s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data); 108s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data); 109s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); 110s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); 111s32 e1000_check_polarity_82577(struct e1000_hw *hw); 112s32 e1000_get_phy_info_82577(struct e1000_hw *hw); 113s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); 114s32 e1000_get_cable_length_82577(struct e1000_hw *hw); | 48s32 e1000_check_downshift_generic(struct e1000_hw *hw); 49s32 e1000_check_polarity_m88(struct e1000_hw *hw); 50s32 e1000_check_polarity_igp(struct e1000_hw *hw); 51s32 e1000_check_polarity_ife(struct e1000_hw *hw); 52s32 e1000_check_reset_block_generic(struct e1000_hw *hw); 53s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 54s32 e1000_copper_link_autoneg(struct e1000_hw *hw); 55s32 e1000_copper_link_setup_igp(struct e1000_hw *hw); --- 55 unchanged lines hidden (view full) --- 111s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data); 112s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data); 113s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); 114s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); 115s32 e1000_check_polarity_82577(struct e1000_hw *hw); 116s32 e1000_get_phy_info_82577(struct e1000_hw *hw); 117s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); 118s32 e1000_get_cable_length_82577(struct e1000_hw *hw); |
| 119s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data); 120s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); |
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| 115 116#define E1000_MAX_PHY_ADDR 8 117 118/* IGP01E1000 Specific Registers */ 119#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 120#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 121#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 122#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 123#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ 124#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ 125#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 126#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 127#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 128#define IGP_PAGE_SHIFT 5 129#define PHY_REG_MASK 0x1F 130 | 121 122#define E1000_MAX_PHY_ADDR 8 123 124/* IGP01E1000 Specific Registers */ 125#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 126#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 127#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 128#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 129#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ 130#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ 131#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 132#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 133#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 134#define IGP_PAGE_SHIFT 5 135#define PHY_REG_MASK 0x1F 136 |
| 137/* GS40G - I210 PHY defines */ 138#define GS40G_PAGE_SELECT 0x16 139#define GS40G_PAGE_SHIFT 16 140#define GS40G_OFFSET_MASK 0xFFFF 141#define GS40G_PAGE_2 0x20000 142#define GS40G_MAC_REG2 0x15 143#define GS40G_MAC_LB 0x4140 144#define GS40G_MAC_SPEED_1G 0X0006 145#define GS40G_COPPER_SPEC 0x0010 146#define GS40G_CS_POWER_DOWN 0x0002 147 |
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| 131/* BM/HV Specific Registers */ 132#define BM_PORT_CTRL_PAGE 769 133#define BM_PCIE_PAGE 770 134#define BM_WUC_PAGE 800 135#define BM_WUC_ADDRESS_OPCODE 0x11 136#define BM_WUC_DATA_OPCODE 0x12 137#define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE 138#define BM_WUC_ENABLE_REG 17 --- 30 unchanged lines hidden (view full) --- 169/* I82577 PHY Status 2 */ 170#define I82577_PHY_STATUS2_REV_POLARITY 0x0400 171#define I82577_PHY_STATUS2_MDIX 0x0800 172#define I82577_PHY_STATUS2_SPEED_MASK 0x0300 173#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 174#define I82577_PHY_STATUS2_SPEED_100MBPS 0x0100 175 176/* I82577 PHY Control 2 */ | 148/* BM/HV Specific Registers */ 149#define BM_PORT_CTRL_PAGE 769 150#define BM_PCIE_PAGE 770 151#define BM_WUC_PAGE 800 152#define BM_WUC_ADDRESS_OPCODE 0x11 153#define BM_WUC_DATA_OPCODE 0x12 154#define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE 155#define BM_WUC_ENABLE_REG 17 --- 30 unchanged lines hidden (view full) --- 186/* I82577 PHY Status 2 */ 187#define I82577_PHY_STATUS2_REV_POLARITY 0x0400 188#define I82577_PHY_STATUS2_MDIX 0x0800 189#define I82577_PHY_STATUS2_SPEED_MASK 0x0300 190#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 191#define I82577_PHY_STATUS2_SPEED_100MBPS 0x0100 192 193/* I82577 PHY Control 2 */ |
| 177#define I82577_PHY_CTRL2_AUTO_MDIX 0x0400 178#define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 | 194#define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200 195#define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400 196#define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600 |
| 179 180/* I82577 PHY Diagnostics Status */ 181#define I82577_DSTATUS_CABLE_LENGTH 0x03FC 182#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 183 184/* 82580 PHY Power Management */ 185#define E1000_82580_PHY_POWER_MGMT 0xE14 186#define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */ --- 121 unchanged lines hidden --- | 197 198/* I82577 PHY Diagnostics Status */ 199#define I82577_DSTATUS_CABLE_LENGTH 0x03FC 200#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 201 202/* 82580 PHY Power Management */ 203#define E1000_82580_PHY_POWER_MGMT 0xE14 204#define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */ --- 121 unchanged lines hidden --- |