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e1000_manage.c (225736) e1000_manage.c (238262)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/9/sys/dev/e1000/e1000_manage.c 218530 2011-02-11 01:00:26Z jfv $*/
33/*$FreeBSD: stable/9/sys/dev/e1000/e1000_manage.c 238262 2012-07-08 20:35:56Z jfv $*/
34
35#include "e1000_api.h"
36
37/**
38 * e1000_calculate_checksum - Calculate checksum for buffer
39 * @buffer: pointer to EEPROM
40 * @length: size of EEPROM to calculate a checksum for
41 *

--- 24 unchanged lines hidden (view full) ---

66 *
67 * This function checks whether the HOST IF is enabled for command operation
68 * and also checks whether the previous command is completed. It busy waits
69 * in case of previous command is not completed.
70 **/
71s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
72{
73 u32 hicr;
34
35#include "e1000_api.h"
36
37/**
38 * e1000_calculate_checksum - Calculate checksum for buffer
39 * @buffer: pointer to EEPROM
40 * @length: size of EEPROM to calculate a checksum for
41 *

--- 24 unchanged lines hidden (view full) ---

66 *
67 * This function checks whether the HOST IF is enabled for command operation
68 * and also checks whether the previous command is completed. It busy waits
69 * in case of previous command is not completed.
70 **/
71s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
72{
73 u32 hicr;
74 s32 ret_val = E1000_SUCCESS;
75 u8 i;
76
77 DEBUGFUNC("e1000_mng_enable_host_if_generic");
78
74 u8 i;
75
76 DEBUGFUNC("e1000_mng_enable_host_if_generic");
77
79 if (!(hw->mac.arc_subsystem_valid)) {
78 if (!hw->mac.arc_subsystem_valid) {
80 DEBUGOUT("ARC subsystem not valid.\n");
79 DEBUGOUT("ARC subsystem not valid.\n");
81 ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
82 goto out;
80 return -E1000_ERR_HOST_INTERFACE_COMMAND;
83 }
84
85 /* Check that the host interface is enabled. */
86 hicr = E1000_READ_REG(hw, E1000_HICR);
81 }
82
83 /* Check that the host interface is enabled. */
84 hicr = E1000_READ_REG(hw, E1000_HICR);
87 if ((hicr & E1000_HICR_EN) == 0) {
85 if (!(hicr & E1000_HICR_EN)) {
88 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
86 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
89 ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
90 goto out;
87 return -E1000_ERR_HOST_INTERFACE_COMMAND;
91 }
92 /* check the previous command is completed */
93 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
94 hicr = E1000_READ_REG(hw, E1000_HICR);
95 if (!(hicr & E1000_HICR_C))
96 break;
97 msec_delay_irq(1);
98 }
99
100 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
101 DEBUGOUT("Previous command timeout failed .\n");
88 }
89 /* check the previous command is completed */
90 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
91 hicr = E1000_READ_REG(hw, E1000_HICR);
92 if (!(hicr & E1000_HICR_C))
93 break;
94 msec_delay_irq(1);
95 }
96
97 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
98 DEBUGOUT("Previous command timeout failed .\n");
102 ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
103 goto out;
99 return -E1000_ERR_HOST_INTERFACE_COMMAND;
104 }
105
100 }
101
106out:
107 return ret_val;
102 return E1000_SUCCESS;
108}
109
110/**
111 * e1000_check_mng_mode_generic - Generic check management mode
112 * @hw: pointer to the HW structure
113 *
114 * Reads the firmware semaphore register and returns TRUE (>0) if
115 * manageability is enabled, else FALSE (0).
116 **/
117bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
118{
119 u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
120
121 DEBUGFUNC("e1000_check_mng_mode_generic");
122
123
124 return (fwsm & E1000_FWSM_MODE_MASK) ==
103}
104
105/**
106 * e1000_check_mng_mode_generic - Generic check management mode
107 * @hw: pointer to the HW structure
108 *
109 * Reads the firmware semaphore register and returns TRUE (>0) if
110 * manageability is enabled, else FALSE (0).
111 **/
112bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
113{
114 u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
115
116 DEBUGFUNC("e1000_check_mng_mode_generic");
117
118
119 return (fwsm & E1000_FWSM_MODE_MASK) ==
125 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
120 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
126}
127
128/**
129 * e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx
130 * @hw: pointer to the HW structure
131 *
132 * Enables packet filtering on transmit packets if manageability is enabled
133 * and host interface is enabled.

--- 8 unchanged lines hidden (view full) ---

142
143 DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
144
145 hw->mac.tx_pkt_filtering = TRUE;
146
147 /* No manageability, no filtering */
148 if (!hw->mac.ops.check_mng_mode(hw)) {
149 hw->mac.tx_pkt_filtering = FALSE;
121}
122
123/**
124 * e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx
125 * @hw: pointer to the HW structure
126 *
127 * Enables packet filtering on transmit packets if manageability is enabled
128 * and host interface is enabled.

--- 8 unchanged lines hidden (view full) ---

137
138 DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
139
140 hw->mac.tx_pkt_filtering = TRUE;
141
142 /* No manageability, no filtering */
143 if (!hw->mac.ops.check_mng_mode(hw)) {
144 hw->mac.tx_pkt_filtering = FALSE;
150 goto out;
145 return hw->mac.tx_pkt_filtering;
151 }
152
153 /*
154 * If we can't read from the host interface for whatever
155 * reason, disable filtering.
156 */
157 ret_val = hw->mac.ops.mng_enable_host_if(hw);
158 if (ret_val != E1000_SUCCESS) {
159 hw->mac.tx_pkt_filtering = FALSE;
146 }
147
148 /*
149 * If we can't read from the host interface for whatever
150 * reason, disable filtering.
151 */
152 ret_val = hw->mac.ops.mng_enable_host_if(hw);
153 if (ret_val != E1000_SUCCESS) {
154 hw->mac.tx_pkt_filtering = FALSE;
160 goto out;
155 return hw->mac.tx_pkt_filtering;
161 }
162
163 /* Read in the header. Length and offset are in dwords. */
164 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
165 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
166 for (i = 0; i < len; i++)
167 *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
156 }
157
158 /* Read in the header. Length and offset are in dwords. */
159 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
160 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
161 for (i = 0; i < len; i++)
162 *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
168 offset + i);
163 offset + i);
169 hdr_csum = hdr->checksum;
170 hdr->checksum = 0;
171 csum = e1000_calculate_checksum((u8 *)hdr,
164 hdr_csum = hdr->checksum;
165 hdr->checksum = 0;
166 csum = e1000_calculate_checksum((u8 *)hdr,
172 E1000_MNG_DHCP_COOKIE_LENGTH);
167 E1000_MNG_DHCP_COOKIE_LENGTH);
173 /*
174 * If either the checksums or signature don't match, then
175 * the cookie area isn't considered valid, in which case we
176 * take the safe route of assuming Tx filtering is enabled.
177 */
178 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
179 hw->mac.tx_pkt_filtering = TRUE;
168 /*
169 * If either the checksums or signature don't match, then
170 * the cookie area isn't considered valid, in which case we
171 * take the safe route of assuming Tx filtering is enabled.
172 */
173 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
174 hw->mac.tx_pkt_filtering = TRUE;
180 goto out;
175 return hw->mac.tx_pkt_filtering;
181 }
182
183 /* Cookie area is valid, make the final check for filtering. */
176 }
177
178 /* Cookie area is valid, make the final check for filtering. */
184 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
179 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
185 hw->mac.tx_pkt_filtering = FALSE;
180 hw->mac.tx_pkt_filtering = FALSE;
186 goto out;
187 }
188
181
189out:
190 return hw->mac.tx_pkt_filtering;
191}
192
193/**
182 return hw->mac.tx_pkt_filtering;
183}
184
185/**
194 * e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
195 * @hw: pointer to the HW structure
196 * @buffer: pointer to the host interface
197 * @length: size of the buffer
198 *
199 * Writes the DHCP information to the host interface.
200 **/
201s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
202 u16 length)
203{
204 struct e1000_host_mng_command_header hdr;
205 s32 ret_val;
206 u32 hicr;
207
208 DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
209
210 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
211 hdr.command_length = length;
212 hdr.reserved1 = 0;
213 hdr.reserved2 = 0;
214 hdr.checksum = 0;
215
216 /* Enable the host interface */
217 ret_val = hw->mac.ops.mng_enable_host_if(hw);
218 if (ret_val)
219 goto out;
220
221 /* Populate the host interface with the contents of "buffer". */
222 ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
223 sizeof(hdr), &(hdr.checksum));
224 if (ret_val)
225 goto out;
226
227 /* Write the manageability command header */
228 ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
229 if (ret_val)
230 goto out;
231
232 /* Tell the ARC a new command is pending. */
233 hicr = E1000_READ_REG(hw, E1000_HICR);
234 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
235
236out:
237 return ret_val;
238}
239
240/**
241 * e1000_mng_write_cmd_header_generic - Writes manageability command header
242 * @hw: pointer to the HW structure
243 * @hdr: pointer to the host interface command header
244 *
245 * Writes the command header after does the checksum calculation.
246 **/
247s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
186 * e1000_mng_write_cmd_header_generic - Writes manageability command header
187 * @hw: pointer to the HW structure
188 * @hdr: pointer to the host interface command header
189 *
190 * Writes the command header after does the checksum calculation.
191 **/
192s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
248 struct e1000_host_mng_command_header *hdr)
193 struct e1000_host_mng_command_header *hdr)
249{
250 u16 i, length = sizeof(struct e1000_host_mng_command_header);
251
252 DEBUGFUNC("e1000_mng_write_cmd_header_generic");
253
254 /* Write the whole command header structure with new checksum. */
255
256 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
257
258 length >>= 2;
259 /* Write the relevant command block into the ram area. */
260 for (i = 0; i < length; i++) {
261 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
194{
195 u16 i, length = sizeof(struct e1000_host_mng_command_header);
196
197 DEBUGFUNC("e1000_mng_write_cmd_header_generic");
198
199 /* Write the whole command header structure with new checksum. */
200
201 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
202
203 length >>= 2;
204 /* Write the relevant command block into the ram area. */
205 for (i = 0; i < length; i++) {
206 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
262 *((u32 *) hdr + i));
207 *((u32 *) hdr + i));
263 E1000_WRITE_FLUSH(hw);
264 }
265
266 return E1000_SUCCESS;
267}
268
269/**
270 * e1000_mng_host_if_write_generic - Write to the manageability host interface
271 * @hw: pointer to the HW structure
272 * @buffer: pointer to the host interface buffer
273 * @length: size of the buffer
274 * @offset: location in the buffer to write to
275 * @sum: sum of the data (not checksum)
276 *
277 * This function writes the buffer content at the offset given on the host if.
278 * It also does alignment considerations to do the writes in most efficient
279 * way. Also fills up the sum of the buffer in *buffer parameter.
280 **/
281s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
208 E1000_WRITE_FLUSH(hw);
209 }
210
211 return E1000_SUCCESS;
212}
213
214/**
215 * e1000_mng_host_if_write_generic - Write to the manageability host interface
216 * @hw: pointer to the HW structure
217 * @buffer: pointer to the host interface buffer
218 * @length: size of the buffer
219 * @offset: location in the buffer to write to
220 * @sum: sum of the data (not checksum)
221 *
222 * This function writes the buffer content at the offset given on the host if.
223 * It also does alignment considerations to do the writes in most efficient
224 * way. Also fills up the sum of the buffer in *buffer parameter.
225 **/
226s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
282 u16 length, u16 offset, u8 *sum)
227 u16 length, u16 offset, u8 *sum)
283{
284 u8 *tmp;
285 u8 *bufptr = buffer;
286 u32 data = 0;
228{
229 u8 *tmp;
230 u8 *bufptr = buffer;
231 u32 data = 0;
287 s32 ret_val = E1000_SUCCESS;
288 u16 remaining, i, j, prev_bytes;
289
290 DEBUGFUNC("e1000_mng_host_if_write_generic");
291
292 /* sum = only sum of the data and it is not checksum */
293
232 u16 remaining, i, j, prev_bytes;
233
234 DEBUGFUNC("e1000_mng_host_if_write_generic");
235
236 /* sum = only sum of the data and it is not checksum */
237
294 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
295 ret_val = -E1000_ERR_PARAM;
296 goto out;
297 }
238 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
239 return -E1000_ERR_PARAM;
298
299 tmp = (u8 *)&data;
300 prev_bytes = offset & 0x3;
301 offset >>= 2;
302
303 if (prev_bytes) {
304 data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
305 for (j = prev_bytes; j < sizeof(u32); j++) {

--- 17 unchanged lines hidden (view full) ---

323 */
324 for (i = 0; i < length; i++) {
325 for (j = 0; j < sizeof(u32); j++) {
326 *(tmp + j) = *bufptr++;
327 *sum += *(tmp + j);
328 }
329
330 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
240
241 tmp = (u8 *)&data;
242 prev_bytes = offset & 0x3;
243 offset >>= 2;
244
245 if (prev_bytes) {
246 data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
247 for (j = prev_bytes; j < sizeof(u32); j++) {

--- 17 unchanged lines hidden (view full) ---

265 */
266 for (i = 0; i < length; i++) {
267 for (j = 0; j < sizeof(u32); j++) {
268 *(tmp + j) = *bufptr++;
269 *sum += *(tmp + j);
270 }
271
272 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
331 data);
273 data);
332 }
333 if (remaining) {
334 for (j = 0; j < sizeof(u32); j++) {
335 if (j < remaining)
336 *(tmp + j) = *bufptr++;
337 else
338 *(tmp + j) = 0;
339
340 *sum += *(tmp + j);
341 }
274 }
275 if (remaining) {
276 for (j = 0; j < sizeof(u32); j++) {
277 if (j < remaining)
278 *(tmp + j) = *bufptr++;
279 else
280 *(tmp + j) = 0;
281
282 *sum += *(tmp + j);
283 }
342 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
284 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
285 data);
343 }
344
286 }
287
345out:
346 return ret_val;
288 return E1000_SUCCESS;
347}
348
349/**
289}
290
291/**
292 * e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
293 * @hw: pointer to the HW structure
294 * @buffer: pointer to the host interface
295 * @length: size of the buffer
296 *
297 * Writes the DHCP information to the host interface.
298 **/
299s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
300 u16 length)
301{
302 struct e1000_host_mng_command_header hdr;
303 s32 ret_val;
304 u32 hicr;
305
306 DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
307
308 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
309 hdr.command_length = length;
310 hdr.reserved1 = 0;
311 hdr.reserved2 = 0;
312 hdr.checksum = 0;
313
314 /* Enable the host interface */
315 ret_val = hw->mac.ops.mng_enable_host_if(hw);
316 if (ret_val)
317 return ret_val;
318
319 /* Populate the host interface with the contents of "buffer". */
320 ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
321 sizeof(hdr), &(hdr.checksum));
322 if (ret_val)
323 return ret_val;
324
325 /* Write the manageability command header */
326 ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
327 if (ret_val)
328 return ret_val;
329
330 /* Tell the ARC a new command is pending. */
331 hicr = E1000_READ_REG(hw, E1000_HICR);
332 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
333
334 return E1000_SUCCESS;
335}
336
337/**
350 * e1000_enable_mng_pass_thru - Check if management passthrough is needed
351 * @hw: pointer to the HW structure
352 *
353 * Verifies the hardware needs to leave interface enabled so that frames can
354 * be directed to and from the management interface.
355 **/
356bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
357{
358 u32 manc;
359 u32 fwsm, factps;
338 * e1000_enable_mng_pass_thru - Check if management passthrough is needed
339 * @hw: pointer to the HW structure
340 *
341 * Verifies the hardware needs to leave interface enabled so that frames can
342 * be directed to and from the management interface.
343 **/
344bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
345{
346 u32 manc;
347 u32 fwsm, factps;
360 bool ret_val = FALSE;
361
362 DEBUGFUNC("e1000_enable_mng_pass_thru");
363
364 if (!hw->mac.asf_firmware_present)
348
349 DEBUGFUNC("e1000_enable_mng_pass_thru");
350
351 if (!hw->mac.asf_firmware_present)
365 goto out;
352 return FALSE;
366
367 manc = E1000_READ_REG(hw, E1000_MANC);
368
369 if (!(manc & E1000_MANC_RCV_TCO_EN))
353
354 manc = E1000_READ_REG(hw, E1000_MANC);
355
356 if (!(manc & E1000_MANC_RCV_TCO_EN))
370 goto out;
357 return FALSE;
371
372 if (hw->mac.has_fwsm) {
373 fwsm = E1000_READ_REG(hw, E1000_FWSM);
374 factps = E1000_READ_REG(hw, E1000_FACTPS);
375
376 if (!(factps & E1000_FACTPS_MNGCG) &&
377 ((fwsm & E1000_FWSM_MODE_MASK) ==
358
359 if (hw->mac.has_fwsm) {
360 fwsm = E1000_READ_REG(hw, E1000_FWSM);
361 factps = E1000_READ_REG(hw, E1000_FACTPS);
362
363 if (!(factps & E1000_FACTPS_MNGCG) &&
364 ((fwsm & E1000_FWSM_MODE_MASK) ==
378 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
379 ret_val = TRUE;
380 goto out;
381 }
365 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))
366 return TRUE;
382 } else if ((hw->mac.type == e1000_82574) ||
383 (hw->mac.type == e1000_82583)) {
384 u16 data;
385
386 factps = E1000_READ_REG(hw, E1000_FACTPS);
387 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
388
389 if (!(factps & E1000_FACTPS_MNGCG) &&
390 ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
367 } else if ((hw->mac.type == e1000_82574) ||
368 (hw->mac.type == e1000_82583)) {
369 u16 data;
370
371 factps = E1000_READ_REG(hw, E1000_FACTPS);
372 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
373
374 if (!(factps & E1000_FACTPS_MNGCG) &&
375 ((data & E1000_NVM_INIT_CTRL2_MNGM) ==
391 (e1000_mng_mode_pt << 13))) {
392 ret_val = TRUE;
393 goto out;
394 }
376 (e1000_mng_mode_pt << 13)))
377 return TRUE;
395 } else if ((manc & E1000_MANC_SMBUS_EN) &&
378 } else if ((manc & E1000_MANC_SMBUS_EN) &&
396 !(manc & E1000_MANC_ASF_EN)) {
397 ret_val = TRUE;
398 goto out;
379 !(manc & E1000_MANC_ASF_EN)) {
380 return TRUE;
399 }
400
381 }
382
401out:
402 return ret_val;
383 return FALSE;
403}
404
405/**
406 * e1000_host_interface_command - Writes buffer to host interface
407 * @hw: pointer to the HW structure
408 * @buffer: contains a command to write
409 * @length: the byte length of the buffer, must be multiple of 4 bytes
410 *
411 * Writes a buffer to the Host Interface. Upon success, returns E1000_SUCCESS
412 * else returns E1000_ERR_HOST_INTERFACE_COMMAND.
413 **/
414s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)
415{
416 u32 hicr, i;
384}
385
386/**
387 * e1000_host_interface_command - Writes buffer to host interface
388 * @hw: pointer to the HW structure
389 * @buffer: contains a command to write
390 * @length: the byte length of the buffer, must be multiple of 4 bytes
391 *
392 * Writes a buffer to the Host Interface. Upon success, returns E1000_SUCCESS
393 * else returns E1000_ERR_HOST_INTERFACE_COMMAND.
394 **/
395s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)
396{
397 u32 hicr, i;
417 s32 ret_val = E1000_SUCCESS;
418
419 DEBUGFUNC("e1000_host_interface_command");
420
421 if (!(hw->mac.arc_subsystem_valid)) {
422 DEBUGOUT("Hardware doesn't support host interface command.\n");
398
399 DEBUGFUNC("e1000_host_interface_command");
400
401 if (!(hw->mac.arc_subsystem_valid)) {
402 DEBUGOUT("Hardware doesn't support host interface command.\n");
423 goto out;
403 return E1000_SUCCESS;
424 }
425
426 if (!hw->mac.asf_firmware_present) {
427 DEBUGOUT("Firmware is not present.\n");
404 }
405
406 if (!hw->mac.asf_firmware_present) {
407 DEBUGOUT("Firmware is not present.\n");
428 goto out;
408 return E1000_SUCCESS;
429 }
430
431 if (length == 0 || length & 0x3 ||
432 length > E1000_HI_MAX_BLOCK_BYTE_LENGTH) {
433 DEBUGOUT("Buffer length failure.\n");
409 }
410
411 if (length == 0 || length & 0x3 ||
412 length > E1000_HI_MAX_BLOCK_BYTE_LENGTH) {
413 DEBUGOUT("Buffer length failure.\n");
434 ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
435 goto out;
414 return -E1000_ERR_HOST_INTERFACE_COMMAND;
436 }
437
438 /* Check that the host interface is enabled. */
439 hicr = E1000_READ_REG(hw, E1000_HICR);
415 }
416
417 /* Check that the host interface is enabled. */
418 hicr = E1000_READ_REG(hw, E1000_HICR);
440 if ((hicr & E1000_HICR_EN) == 0) {
419 if (!(hicr & E1000_HICR_EN)) {
441 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
420 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
442 ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
443 goto out;
421 return -E1000_ERR_HOST_INTERFACE_COMMAND;
444 }
445
446 /* Calculate length in DWORDs */
447 length >>= 2;
448
449 /*
450 * The device driver writes the relevant command block
451 * into the ram area.
452 */
453 for (i = 0; i < length; i++)
422 }
423
424 /* Calculate length in DWORDs */
425 length >>= 2;
426
427 /*
428 * The device driver writes the relevant command block
429 * into the ram area.
430 */
431 for (i = 0; i < length; i++)
454 E1000_WRITE_REG_ARRAY_DWORD(hw,
455 E1000_HOST_IF,
456 i,
457 *((u32 *)buffer + i));
432 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
433 *((u32 *)buffer + i));
458
459 /* Setting this bit tells the ARC that a new command is pending. */
460 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
461
462 for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
463 hicr = E1000_READ_REG(hw, E1000_HICR);
464 if (!(hicr & E1000_HICR_C))
465 break;
466 msec_delay(1);
467 }
468
469 /* Check command successful completion. */
470 if (i == E1000_HI_COMMAND_TIMEOUT ||
471 (!(E1000_READ_REG(hw, E1000_HICR) & E1000_HICR_SV))) {
472 DEBUGOUT("Command has failed with no status valid.\n");
434
435 /* Setting this bit tells the ARC that a new command is pending. */
436 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
437
438 for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
439 hicr = E1000_READ_REG(hw, E1000_HICR);
440 if (!(hicr & E1000_HICR_C))
441 break;
442 msec_delay(1);
443 }
444
445 /* Check command successful completion. */
446 if (i == E1000_HI_COMMAND_TIMEOUT ||
447 (!(E1000_READ_REG(hw, E1000_HICR) & E1000_HICR_SV))) {
448 DEBUGOUT("Command has failed with no status valid.\n");
473 ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
474 goto out;
449 return -E1000_ERR_HOST_INTERFACE_COMMAND;
475 }
476
477 for (i = 0; i < length; i++)
478 *((u32 *)buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
450 }
451
452 for (i = 0; i < length; i++)
453 *((u32 *)buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
479 E1000_HOST_IF,
480 i);
454 E1000_HOST_IF,
455 i);
481
456
482out:
483 return ret_val;
457 return E1000_SUCCESS;
484}
458}
459/**
460 * e1000_load_firmware - Writes proxy FW code buffer to host interface
461 * and execute.
462 * @hw: pointer to the HW structure
463 * @buffer: contains a firmware to write
464 * @length: the byte length of the buffer, must be multiple of 4 bytes
465 *
466 * Upon success returns E1000_SUCCESS, returns E1000_ERR_CONFIG if not enabled
467 * in HW else returns E1000_ERR_HOST_INTERFACE_COMMAND.
468 **/
469s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length)
470{
471 u32 hicr, hibba, fwsm, icr, i;
485
472
473 DEBUGFUNC("e1000_load_firmware");
474
475 if (hw->mac.type < e1000_i210) {
476 DEBUGOUT("Hardware doesn't support loading FW by the driver\n");
477 return -E1000_ERR_CONFIG;
478 }
479
480 /* Check that the host interface is enabled. */
481 hicr = E1000_READ_REG(hw, E1000_HICR);
482 if (!(hicr & E1000_HICR_EN)) {
483 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
484 return -E1000_ERR_CONFIG;
485 }
486 if (!(hicr & E1000_HICR_MEMORY_BASE_EN)) {
487 DEBUGOUT("E1000_HICR_MEMORY_BASE_EN bit disabled.\n");
488 return -E1000_ERR_CONFIG;
489 }
490
491 if (length == 0 || length & 0x3 || length > E1000_HI_FW_MAX_LENGTH) {
492 DEBUGOUT("Buffer length failure.\n");
493 return -E1000_ERR_INVALID_ARGUMENT;
494 }
495
496 /* Clear notification from ROM-FW by reading ICR register */
497 icr = E1000_READ_REG(hw, E1000_ICR_V2);
498
499 /* Reset ROM-FW */
500 hicr = E1000_READ_REG(hw, E1000_HICR);
501 hicr |= E1000_HICR_FW_RESET_ENABLE;
502 E1000_WRITE_REG(hw, E1000_HICR, hicr);
503 hicr |= E1000_HICR_FW_RESET;
504 E1000_WRITE_REG(hw, E1000_HICR, hicr);
505 E1000_WRITE_FLUSH(hw);
506
507 /* Wait till MAC notifies about its readiness after ROM-FW reset */
508 for (i = 0; i < (E1000_HI_COMMAND_TIMEOUT * 2); i++) {
509 icr = E1000_READ_REG(hw, E1000_ICR_V2);
510 if (icr & E1000_ICR_MNG)
511 break;
512 msec_delay(1);
513 }
514
515 /* Check for timeout */
516 if (i == E1000_HI_COMMAND_TIMEOUT) {
517 DEBUGOUT("FW reset failed.\n");
518 return -E1000_ERR_HOST_INTERFACE_COMMAND;
519 }
520
521 /* Wait till MAC is ready to accept new FW code */
522 for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
523 fwsm = E1000_READ_REG(hw, E1000_FWSM);
524 if ((fwsm & E1000_FWSM_FW_VALID) &&
525 ((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT ==
526 E1000_FWSM_HI_EN_ONLY_MODE))
527 break;
528 msec_delay(1);
529 }
530
531 /* Check for timeout */
532 if (i == E1000_HI_COMMAND_TIMEOUT) {
533 DEBUGOUT("FW reset failed.\n");
534 return -E1000_ERR_HOST_INTERFACE_COMMAND;
535 }
536
537 /* Calculate length in DWORDs */
538 length >>= 2;
539
540 /*
541 * The device driver writes the relevant FW code block
542 * into the ram area in DWORDs via 1kB ram addressing window.
543 */
544 for (i = 0; i < length; i++) {
545 if (!(i % E1000_HI_FW_BLOCK_DWORD_LENGTH)) {
546 /* Point to correct 1kB ram window */
547 hibba = E1000_HI_FW_BASE_ADDRESS +
548 ((E1000_HI_FW_BLOCK_DWORD_LENGTH << 2) *
549 (i / E1000_HI_FW_BLOCK_DWORD_LENGTH));
550
551 E1000_WRITE_REG(hw, E1000_HIBBA, hibba);
552 }
553
554 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
555 i % E1000_HI_FW_BLOCK_DWORD_LENGTH,
556 *((u32 *)buffer + i));
557 }
558
559 /* Setting this bit tells the ARC that a new FW is ready to execute. */
560 hicr = E1000_READ_REG(hw, E1000_HICR);
561 E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
562
563 for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
564 hicr = E1000_READ_REG(hw, E1000_HICR);
565 if (!(hicr & E1000_HICR_C))
566 break;
567 msec_delay(1);
568 }
569
570 /* Check for successful FW start. */
571 if (i == E1000_HI_COMMAND_TIMEOUT) {
572 DEBUGOUT("New FW did not start within timeout period.\n");
573 return -E1000_ERR_HOST_INTERFACE_COMMAND;
574 }
575
576 return E1000_SUCCESS;
577}
578
579