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e1000_mac.c (235527) e1000_mac.c (238262)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2011, Intel Corporation
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/9/sys/dev/e1000/e1000_mac.c 235527 2012-05-16 22:22:52Z jfv $*/
33/*$FreeBSD: stable/9/sys/dev/e1000/e1000_mac.c 238262 2012-07-08 20:35:56Z jfv $*/
34
35#include "e1000_api.h"
36
37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
34
35#include "e1000_api.h"
36
37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
39static void e1000_config_collision_dist_generic(struct e1000_hw *hw);
40static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
39
40/**
41 * e1000_init_mac_ops_generic - Initialize MAC function pointers
42 * @hw: pointer to the HW structure
43 *
44 * Setups up the function pointers to no-op functions
45 **/
46void e1000_init_mac_ops_generic(struct e1000_hw *hw)

--- 343 unchanged lines hidden (view full) ---

390 s32 ret_val = E1000_SUCCESS;
391 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
392 u8 alt_mac_addr[ETH_ADDR_LEN];
393
394 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
395
396 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
397 if (ret_val)
41
42/**
43 * e1000_init_mac_ops_generic - Initialize MAC function pointers
44 * @hw: pointer to the HW structure
45 *
46 * Setups up the function pointers to no-op functions
47 **/
48void e1000_init_mac_ops_generic(struct e1000_hw *hw)

--- 343 unchanged lines hidden (view full) ---

392 s32 ret_val = E1000_SUCCESS;
393 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
394 u8 alt_mac_addr[ETH_ADDR_LEN];
395
396 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
397
398 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
399 if (ret_val)
398 goto out;
400 return ret_val;
399
400 /* not supported on older hardware or 82573 */
401 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
401
402 /* not supported on older hardware or 82573 */
403 if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
402 goto out;
404 return E1000_SUCCESS;
403
404 /*
405 * Alternate MAC address is handled by the option ROM for 82580
406 * and newer. SW support not required.
407 */
408 if (hw->mac.type >= e1000_82580)
405
406 /*
407 * Alternate MAC address is handled by the option ROM for 82580
408 * and newer. SW support not required.
409 */
410 if (hw->mac.type >= e1000_82580)
409 goto out;
411 return E1000_SUCCESS;
410
411 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
412 &nvm_alt_mac_addr_offset);
413 if (ret_val) {
414 DEBUGOUT("NVM Read Error\n");
412
413 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
414 &nvm_alt_mac_addr_offset);
415 if (ret_val) {
416 DEBUGOUT("NVM Read Error\n");
415 goto out;
417 return ret_val;
416 }
417
418 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
419 (nvm_alt_mac_addr_offset == 0x0000))
420 /* There is no Alternate MAC Address */
418 }
419
420 if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
421 (nvm_alt_mac_addr_offset == 0x0000))
422 /* There is no Alternate MAC Address */
421 goto out;
423 return E1000_SUCCESS;
422
423 if (hw->bus.func == E1000_FUNC_1)
424 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
425 if (hw->bus.func == E1000_FUNC_2)
426 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
427
428 if (hw->bus.func == E1000_FUNC_3)
429 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
430 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
431 offset = nvm_alt_mac_addr_offset + (i >> 1);
432 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
433 if (ret_val) {
434 DEBUGOUT("NVM Read Error\n");
424
425 if (hw->bus.func == E1000_FUNC_1)
426 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
427 if (hw->bus.func == E1000_FUNC_2)
428 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
429
430 if (hw->bus.func == E1000_FUNC_3)
431 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
432 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
433 offset = nvm_alt_mac_addr_offset + (i >> 1);
434 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
435 if (ret_val) {
436 DEBUGOUT("NVM Read Error\n");
435 goto out;
437 return ret_val;
436 }
437
438 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
439 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
440 }
441
442 /* if multicast bit is set, the alternate address will not be used */
443 if (alt_mac_addr[0] & 0x01) {
444 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
438 }
439
440 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
441 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
442 }
443
444 /* if multicast bit is set, the alternate address will not be used */
445 if (alt_mac_addr[0] & 0x01) {
446 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
445 goto out;
447 return E1000_SUCCESS;
446 }
447
448 /*
449 * We have a valid alternate MAC address, and we want to treat it the
450 * same as the normal permanent MAC address stored by the HW into the
451 * RAR. Do this by mapping this address into RAR0.
452 */
453 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
454
448 }
449
450 /*
451 * We have a valid alternate MAC address, and we want to treat it the
452 * same as the normal permanent MAC address stored by the HW into the
453 * RAR. Do this by mapping this address into RAR0.
454 */
455 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
456
455out:
456 return ret_val;
457 return E1000_SUCCESS;
457}
458
459/**
460 * e1000_rar_set_generic - Set receive address register
461 * @hw: pointer to the HW structure
462 * @addr: pointer to the receive address
463 * @index: receive address array register
464 *
465 * Sets the receive address array register at index to the address passed
466 * in by addr.
467 **/
458}
459
460/**
461 * e1000_rar_set_generic - Set receive address register
462 * @hw: pointer to the HW structure
463 * @addr: pointer to the receive address
464 * @index: receive address array register
465 *
466 * Sets the receive address array register at index to the address passed
467 * in by addr.
468 **/
468void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
469static void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
469{
470 u32 rar_low, rar_high;
471
472 DEBUGFUNC("e1000_rar_set_generic");
473
474 /*
475 * HW expects these in little endian so we reverse the byte order
476 * from network order (big endian) to little endian

--- 14 unchanged lines hidden (view full) ---

491 */
492 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
493 E1000_WRITE_FLUSH(hw);
494 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
495 E1000_WRITE_FLUSH(hw);
496}
497
498/**
470{
471 u32 rar_low, rar_high;
472
473 DEBUGFUNC("e1000_rar_set_generic");
474
475 /*
476 * HW expects these in little endian so we reverse the byte order
477 * from network order (big endian) to little endian

--- 14 unchanged lines hidden (view full) ---

492 */
493 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
494 E1000_WRITE_FLUSH(hw);
495 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
496 E1000_WRITE_FLUSH(hw);
497}
498
499/**
499 * e1000_update_mc_addr_list_generic - Update Multicast addresses
500 * @hw: pointer to the HW structure
501 * @mc_addr_list: array of multicast addresses to program
502 * @mc_addr_count: number of multicast addresses to program
503 *
504 * Updates entire Multicast Table Array.
505 * The caller must have a packed mc_addr_list of multicast addresses.
506 **/
507void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
508 u8 *mc_addr_list, u32 mc_addr_count)
509{
510 u32 hash_value, hash_bit, hash_reg;
511 int i;
512
513 DEBUGFUNC("e1000_update_mc_addr_list_generic");
514
515 /* clear mta_shadow */
516 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
517
518 /* update mta_shadow from mc_addr_list */
519 for (i = 0; (u32) i < mc_addr_count; i++) {
520 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
521
522 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
523 hash_bit = hash_value & 0x1F;
524
525 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
526 mc_addr_list += (ETH_ADDR_LEN);
527 }
528
529 /* replace the entire MTA table */
530 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
531 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
532 E1000_WRITE_FLUSH(hw);
533}
534
535/**
536 * e1000_hash_mc_addr_generic - Generate a multicast hash value
537 * @hw: pointer to the HW structure
538 * @mc_addr: pointer to a multicast address
539 *
540 * Generates a multicast address hash value which is used to determine
541 * the multicast filter table array address and new table value.
542 **/
543u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)

--- 56 unchanged lines hidden (view full) ---

600
601 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
602 (((u16) mc_addr[5]) << bit_shift)));
603
604 return hash_value;
605}
606
607/**
500 * e1000_hash_mc_addr_generic - Generate a multicast hash value
501 * @hw: pointer to the HW structure
502 * @mc_addr: pointer to a multicast address
503 *
504 * Generates a multicast address hash value which is used to determine
505 * the multicast filter table array address and new table value.
506 **/
507u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)

--- 56 unchanged lines hidden (view full) ---

564
565 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
566 (((u16) mc_addr[5]) << bit_shift)));
567
568 return hash_value;
569}
570
571/**
572 * e1000_update_mc_addr_list_generic - Update Multicast addresses
573 * @hw: pointer to the HW structure
574 * @mc_addr_list: array of multicast addresses to program
575 * @mc_addr_count: number of multicast addresses to program
576 *
577 * Updates entire Multicast Table Array.
578 * The caller must have a packed mc_addr_list of multicast addresses.
579 **/
580void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
581 u8 *mc_addr_list, u32 mc_addr_count)
582{
583 u32 hash_value, hash_bit, hash_reg;
584 int i;
585
586 DEBUGFUNC("e1000_update_mc_addr_list_generic");
587
588 /* clear mta_shadow */
589 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
590
591 /* update mta_shadow from mc_addr_list */
592 for (i = 0; (u32) i < mc_addr_count; i++) {
593 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
594
595 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
596 hash_bit = hash_value & 0x1F;
597
598 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
599 mc_addr_list += (ETH_ADDR_LEN);
600 }
601
602 /* replace the entire MTA table */
603 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
604 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
605 E1000_WRITE_FLUSH(hw);
606}
607
608/**
608 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
609 * @hw: pointer to the HW structure
610 *
611 * In certain situations, a system BIOS may report that the PCIx maximum
612 * memory read byte count (MMRBC) value is higher than than the actual
613 * value. We check the PCIx command register with the current PCIx status
614 * register.
615 **/

--- 91 unchanged lines hidden (view full) ---

707 DEBUGFUNC("e1000_check_for_copper_link");
708
709 /*
710 * We only want to go out to the PHY registers to see if Auto-Neg
711 * has completed and/or if our link status has changed. The
712 * get_link_status flag is set upon receiving a Link Status
713 * Change or Rx Sequence Error interrupt.
714 */
609 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
610 * @hw: pointer to the HW structure
611 *
612 * In certain situations, a system BIOS may report that the PCIx maximum
613 * memory read byte count (MMRBC) value is higher than than the actual
614 * value. We check the PCIx command register with the current PCIx status
615 * register.
616 **/

--- 91 unchanged lines hidden (view full) ---

708 DEBUGFUNC("e1000_check_for_copper_link");
709
710 /*
711 * We only want to go out to the PHY registers to see if Auto-Neg
712 * has completed and/or if our link status has changed. The
713 * get_link_status flag is set upon receiving a Link Status
714 * Change or Rx Sequence Error interrupt.
715 */
715 if (!mac->get_link_status) {
716 ret_val = E1000_SUCCESS;
717 goto out;
718 }
716 if (!mac->get_link_status)
717 return E1000_SUCCESS;
719
720 /*
721 * First we want to see if the MII Status Register reports
722 * link. If so, then we want to get the current speed/duplex
723 * of the PHY.
724 */
725 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
726 if (ret_val)
718
719 /*
720 * First we want to see if the MII Status Register reports
721 * link. If so, then we want to get the current speed/duplex
722 * of the PHY.
723 */
724 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
725 if (ret_val)
727 goto out;
726 return ret_val;
728
729 if (!link)
727
728 if (!link)
730 goto out; /* No link detected */
729 return E1000_SUCCESS; /* No link detected */
731
732 mac->get_link_status = FALSE;
733
734 /*
735 * Check if there was DownShift, must be checked
736 * immediately after link-up
737 */
738 e1000_check_downshift_generic(hw);
739
740 /*
741 * If we are forcing speed/duplex, then we simply return since
742 * we have already determined whether we have link or not.
743 */
730
731 mac->get_link_status = FALSE;
732
733 /*
734 * Check if there was DownShift, must be checked
735 * immediately after link-up
736 */
737 e1000_check_downshift_generic(hw);
738
739 /*
740 * If we are forcing speed/duplex, then we simply return since
741 * we have already determined whether we have link or not.
742 */
744 if (!mac->autoneg) {
745 ret_val = -E1000_ERR_CONFIG;
746 goto out;
747 }
743 if (!mac->autoneg)
744 return -E1000_ERR_CONFIG;
748
749 /*
750 * Auto-Neg is enabled. Auto Speed Detection takes care
751 * of MAC speed/duplex configuration. So we only need to
752 * configure Collision Distance in the MAC.
753 */
754 mac->ops.config_collision_dist(hw);
755
756 /*
757 * Configure Flow Control now that Auto-Neg has completed.
758 * First, we need to restore the desired flow control
759 * settings because we may have had to re-autoneg with a
760 * different link partner.
761 */
762 ret_val = e1000_config_fc_after_link_up_generic(hw);
763 if (ret_val)
764 DEBUGOUT("Error configuring flow control\n");
765
745
746 /*
747 * Auto-Neg is enabled. Auto Speed Detection takes care
748 * of MAC speed/duplex configuration. So we only need to
749 * configure Collision Distance in the MAC.
750 */
751 mac->ops.config_collision_dist(hw);
752
753 /*
754 * Configure Flow Control now that Auto-Neg has completed.
755 * First, we need to restore the desired flow control
756 * settings because we may have had to re-autoneg with a
757 * different link partner.
758 */
759 ret_val = e1000_config_fc_after_link_up_generic(hw);
760 if (ret_val)
761 DEBUGOUT("Error configuring flow control\n");
762
766out:
767 return ret_val;
768}
769
770/**
771 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
772 * @hw: pointer to the HW structure
773 *
774 * Checks for link up on the hardware. If link is not up and we have
775 * a signal, then we need to force link up.
776 **/
777s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
778{
779 struct e1000_mac_info *mac = &hw->mac;
780 u32 rxcw;
781 u32 ctrl;
782 u32 status;
763 return ret_val;
764}
765
766/**
767 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
768 * @hw: pointer to the HW structure
769 *
770 * Checks for link up on the hardware. If link is not up and we have
771 * a signal, then we need to force link up.
772 **/
773s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
774{
775 struct e1000_mac_info *mac = &hw->mac;
776 u32 rxcw;
777 u32 ctrl;
778 u32 status;
783 s32 ret_val = E1000_SUCCESS;
779 s32 ret_val;
784
785 DEBUGFUNC("e1000_check_for_fiber_link_generic");
786
787 ctrl = E1000_READ_REG(hw, E1000_CTRL);
788 status = E1000_READ_REG(hw, E1000_STATUS);
789 rxcw = E1000_READ_REG(hw, E1000_RXCW);
790
791 /*
792 * If we don't have link (auto-negotiation failed or link partner
793 * cannot auto-negotiate), the cable is plugged in (we have signal),
794 * and our link partner is not trying to auto-negotiate with us (we
795 * are receiving idles or data), we need to force link up. We also
796 * need to give auto-negotiation time to complete, in case the cable
797 * was just plugged in. The autoneg_failed flag does this.
798 */
799 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
780
781 DEBUGFUNC("e1000_check_for_fiber_link_generic");
782
783 ctrl = E1000_READ_REG(hw, E1000_CTRL);
784 status = E1000_READ_REG(hw, E1000_STATUS);
785 rxcw = E1000_READ_REG(hw, E1000_RXCW);
786
787 /*
788 * If we don't have link (auto-negotiation failed or link partner
789 * cannot auto-negotiate), the cable is plugged in (we have signal),
790 * and our link partner is not trying to auto-negotiate with us (we
791 * are receiving idles or data), we need to force link up. We also
792 * need to give auto-negotiation time to complete, in case the cable
793 * was just plugged in. The autoneg_failed flag does this.
794 */
795 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
800 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
801 (!(rxcw & E1000_RXCW_C))) {
802 if (mac->autoneg_failed == 0) {
803 mac->autoneg_failed = 1;
804 goto out;
796 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&
797 !(rxcw & E1000_RXCW_C)) {
798 if (!mac->autoneg_failed) {
799 mac->autoneg_failed = TRUE;
800 return E1000_SUCCESS;
805 }
806 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
807
808 /* Disable auto-negotiation in the TXCW register */
809 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
810
811 /* Force link-up and also force full-duplex. */
812 ctrl = E1000_READ_REG(hw, E1000_CTRL);
813 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
814 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
815
816 /* Configure Flow Control after forcing link up. */
817 ret_val = e1000_config_fc_after_link_up_generic(hw);
818 if (ret_val) {
819 DEBUGOUT("Error configuring flow control\n");
801 }
802 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
803
804 /* Disable auto-negotiation in the TXCW register */
805 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
806
807 /* Force link-up and also force full-duplex. */
808 ctrl = E1000_READ_REG(hw, E1000_CTRL);
809 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
810 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
811
812 /* Configure Flow Control after forcing link up. */
813 ret_val = e1000_config_fc_after_link_up_generic(hw);
814 if (ret_val) {
815 DEBUGOUT("Error configuring flow control\n");
820 goto out;
816 return ret_val;
821 }
822 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
823 /*
824 * If we are forcing link and we are receiving /C/ ordered
825 * sets, re-enable auto-negotiation in the TXCW register
826 * and disable forced link in the Device Control register
827 * in an attempt to auto-negotiate with our link partner.
828 */
829 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
830 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
831 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
832
833 mac->serdes_has_link = TRUE;
834 }
835
817 }
818 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
819 /*
820 * If we are forcing link and we are receiving /C/ ordered
821 * sets, re-enable auto-negotiation in the TXCW register
822 * and disable forced link in the Device Control register
823 * in an attempt to auto-negotiate with our link partner.
824 */
825 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
826 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
827 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
828
829 mac->serdes_has_link = TRUE;
830 }
831
836out:
837 return ret_val;
832 return E1000_SUCCESS;
838}
839
840/**
841 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
842 * @hw: pointer to the HW structure
843 *
844 * Checks for link up on the hardware. If link is not up and we have
845 * a signal, then we need to force link up.
846 **/
847s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
848{
849 struct e1000_mac_info *mac = &hw->mac;
850 u32 rxcw;
851 u32 ctrl;
852 u32 status;
833}
834
835/**
836 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
837 * @hw: pointer to the HW structure
838 *
839 * Checks for link up on the hardware. If link is not up and we have
840 * a signal, then we need to force link up.
841 **/
842s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
843{
844 struct e1000_mac_info *mac = &hw->mac;
845 u32 rxcw;
846 u32 ctrl;
847 u32 status;
853 s32 ret_val = E1000_SUCCESS;
848 s32 ret_val;
854
855 DEBUGFUNC("e1000_check_for_serdes_link_generic");
856
857 ctrl = E1000_READ_REG(hw, E1000_CTRL);
858 status = E1000_READ_REG(hw, E1000_STATUS);
859 rxcw = E1000_READ_REG(hw, E1000_RXCW);
860
861 /*
862 * If we don't have link (auto-negotiation failed or link partner
863 * cannot auto-negotiate), and our link partner is not trying to
864 * auto-negotiate with us (we are receiving idles or data),
865 * we need to force link up. We also need to give auto-negotiation
866 * time to complete.
867 */
868 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
849
850 DEBUGFUNC("e1000_check_for_serdes_link_generic");
851
852 ctrl = E1000_READ_REG(hw, E1000_CTRL);
853 status = E1000_READ_REG(hw, E1000_STATUS);
854 rxcw = E1000_READ_REG(hw, E1000_RXCW);
855
856 /*
857 * If we don't have link (auto-negotiation failed or link partner
858 * cannot auto-negotiate), and our link partner is not trying to
859 * auto-negotiate with us (we are receiving idles or data),
860 * we need to force link up. We also need to give auto-negotiation
861 * time to complete.
862 */
863 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
869 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
870 if (mac->autoneg_failed == 0) {
871 mac->autoneg_failed = 1;
872 goto out;
864 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {
865 if (!mac->autoneg_failed) {
866 mac->autoneg_failed = TRUE;
867 return E1000_SUCCESS;
873 }
874 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
875
876 /* Disable auto-negotiation in the TXCW register */
877 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
878
879 /* Force link-up and also force full-duplex. */
880 ctrl = E1000_READ_REG(hw, E1000_CTRL);
881 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
882 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
883
884 /* Configure Flow Control after forcing link up. */
885 ret_val = e1000_config_fc_after_link_up_generic(hw);
886 if (ret_val) {
887 DEBUGOUT("Error configuring flow control\n");
868 }
869 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
870
871 /* Disable auto-negotiation in the TXCW register */
872 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
873
874 /* Force link-up and also force full-duplex. */
875 ctrl = E1000_READ_REG(hw, E1000_CTRL);
876 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
877 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
878
879 /* Configure Flow Control after forcing link up. */
880 ret_val = e1000_config_fc_after_link_up_generic(hw);
881 if (ret_val) {
882 DEBUGOUT("Error configuring flow control\n");
888 goto out;
883 return ret_val;
889 }
890 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
891 /*
892 * If we are forcing link and we are receiving /C/ ordered
893 * sets, re-enable auto-negotiation in the TXCW register
894 * and disable forced link in the Device Control register
895 * in an attempt to auto-negotiate with our link partner.
896 */

--- 41 unchanged lines hidden (view full) ---

938 DEBUGOUT("SERDES: Link down - no sync.\n");
939 }
940 } else {
941 mac->serdes_has_link = FALSE;
942 DEBUGOUT("SERDES: Link down - autoneg failed\n");
943 }
944 }
945
884 }
885 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
886 /*
887 * If we are forcing link and we are receiving /C/ ordered
888 * sets, re-enable auto-negotiation in the TXCW register
889 * and disable forced link in the Device Control register
890 * in an attempt to auto-negotiate with our link partner.
891 */

--- 41 unchanged lines hidden (view full) ---

933 DEBUGOUT("SERDES: Link down - no sync.\n");
934 }
935 } else {
936 mac->serdes_has_link = FALSE;
937 DEBUGOUT("SERDES: Link down - autoneg failed\n");
938 }
939 }
940
946out:
947 return ret_val;
941 return E1000_SUCCESS;
948}
949
950/**
942}
943
944/**
945 * e1000_set_default_fc_generic - Set flow control default values
946 * @hw: pointer to the HW structure
947 *
948 * Read the EEPROM for the default values for flow control and store the
949 * values.
950 **/
951s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
952{
953 s32 ret_val;
954 u16 nvm_data;
955
956 DEBUGFUNC("e1000_set_default_fc_generic");
957
958 /*
959 * Read and store word 0x0F of the EEPROM. This word contains bits
960 * that determine the hardware's default PAUSE (flow control) mode,
961 * a bit that determines whether the HW defaults to enabling or
962 * disabling auto-negotiation, and the direction of the
963 * SW defined pins. If there is no SW over-ride of the flow
964 * control setting, then the variable hw->fc will
965 * be initialized based on a value in the EEPROM.
966 */
967 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
968
969 if (ret_val) {
970 DEBUGOUT("NVM Read Error\n");
971 return ret_val;
972 }
973
974 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
975 hw->fc.requested_mode = e1000_fc_none;
976 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
977 NVM_WORD0F_ASM_DIR)
978 hw->fc.requested_mode = e1000_fc_tx_pause;
979 else
980 hw->fc.requested_mode = e1000_fc_full;
981
982 return E1000_SUCCESS;
983}
984
985/**
951 * e1000_setup_link_generic - Setup flow control and link settings
952 * @hw: pointer to the HW structure
953 *
954 * Determines which flow control settings to use, then configures flow
955 * control. Calls the appropriate media-specific link configuration
956 * function. Assuming the adapter has a valid link partner, a valid link
957 * should be established. Assumes the hardware has previously been reset
958 * and the transmitter and receiver are not enabled.
959 **/
960s32 e1000_setup_link_generic(struct e1000_hw *hw)
961{
986 * e1000_setup_link_generic - Setup flow control and link settings
987 * @hw: pointer to the HW structure
988 *
989 * Determines which flow control settings to use, then configures flow
990 * control. Calls the appropriate media-specific link configuration
991 * function. Assuming the adapter has a valid link partner, a valid link
992 * should be established. Assumes the hardware has previously been reset
993 * and the transmitter and receiver are not enabled.
994 **/
995s32 e1000_setup_link_generic(struct e1000_hw *hw)
996{
962 s32 ret_val = E1000_SUCCESS;
997 s32 ret_val;
963
964 DEBUGFUNC("e1000_setup_link_generic");
965
966 /*
967 * In the case of the phy reset being blocked, we already have a link.
968 * We do not need to set it up again.
969 */
998
999 DEBUGFUNC("e1000_setup_link_generic");
1000
1001 /*
1002 * In the case of the phy reset being blocked, we already have a link.
1003 * We do not need to set it up again.
1004 */
970 if (e1000_check_reset_block(hw))
971 goto out;
1005 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
1006 return E1000_SUCCESS;
972
973 /*
974 * If requested flow control is set to default, set flow control
975 * based on the EEPROM flow control settings.
976 */
977 if (hw->fc.requested_mode == e1000_fc_default) {
978 ret_val = e1000_set_default_fc_generic(hw);
979 if (ret_val)
1007
1008 /*
1009 * If requested flow control is set to default, set flow control
1010 * based on the EEPROM flow control settings.
1011 */
1012 if (hw->fc.requested_mode == e1000_fc_default) {
1013 ret_val = e1000_set_default_fc_generic(hw);
1014 if (ret_val)
980 goto out;
1015 return ret_val;
981 }
982
983 /*
984 * Save off the requested flow control mode for use later. Depending
985 * on the link partner's capabilities, we may or may not use this mode.
986 */
987 hw->fc.current_mode = hw->fc.requested_mode;
988
989 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
990 hw->fc.current_mode);
991
992 /* Call the necessary media_type subroutine to configure the link. */
993 ret_val = hw->mac.ops.setup_physical_interface(hw);
994 if (ret_val)
1016 }
1017
1018 /*
1019 * Save off the requested flow control mode for use later. Depending
1020 * on the link partner's capabilities, we may or may not use this mode.
1021 */
1022 hw->fc.current_mode = hw->fc.requested_mode;
1023
1024 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1025 hw->fc.current_mode);
1026
1027 /* Call the necessary media_type subroutine to configure the link. */
1028 ret_val = hw->mac.ops.setup_physical_interface(hw);
1029 if (ret_val)
995 goto out;
1030 return ret_val;
996
997 /*
998 * Initialize the flow control address, type, and PAUSE timer
999 * registers to their default values. This is done even if flow
1000 * control is disabled, because it does not hurt anything to
1001 * initialize these registers.
1002 */
1003 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1004 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1005 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1006 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1007
1008 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1009
1031
1032 /*
1033 * Initialize the flow control address, type, and PAUSE timer
1034 * registers to their default values. This is done even if flow
1035 * control is disabled, because it does not hurt anything to
1036 * initialize these registers.
1037 */
1038 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1039 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1040 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1041 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1042
1043 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1044
1010 ret_val = e1000_set_fc_watermarks_generic(hw);
1011
1012out:
1013 return ret_val;
1045 return e1000_set_fc_watermarks_generic(hw);
1014}
1015
1016/**
1046}
1047
1048/**
1017 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1049 * e1000_commit_fc_settings_generic - Configure flow control
1018 * @hw: pointer to the HW structure
1019 *
1050 * @hw: pointer to the HW structure
1051 *
1020 * Configures collision distance and flow control for fiber and serdes
1021 * links. Upon successful setup, poll for link.
1052 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1053 * base on the flow control settings in e1000_mac_info.
1022 **/
1054 **/
1023s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1055s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1024{
1025 struct e1000_mac_info *mac = &hw->mac;
1056{
1057 struct e1000_mac_info *mac = &hw->mac;
1026 u32 ctrl;
1027 s32 ret_val = E1000_SUCCESS;
1058 u32 txcw;
1028
1059
1029 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1060 DEBUGFUNC("e1000_commit_fc_settings_generic");
1030
1061
1031 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1032
1033 /* Take the link out of reset */
1034 ctrl &= ~E1000_CTRL_LRST;
1035
1036 mac->ops.config_collision_dist(hw);
1037
1038 ret_val = e1000_commit_fc_settings_generic(hw);
1039 if (ret_val)
1040 goto out;
1041
1042 /*
1062 /*
1043 * Since auto-negotiation is enabled, take the link out of reset (the
1044 * link will be in reset, because we previously reset the chip). This
1045 * will restart auto-negotiation. If auto-negotiation is successful
1046 * then the link-up status bit will be set and the flow control enable
1047 * bits (RFCE and TFCE) will be set according to their negotiated value.
1063 * Check for a software override of the flow control settings, and
1064 * setup the device accordingly. If auto-negotiation is enabled, then
1065 * software will have to set the "PAUSE" bits to the correct value in
1066 * the Transmit Config Word Register (TXCW) and re-start auto-
1067 * negotiation. However, if auto-negotiation is disabled, then
1068 * software will have to manually configure the two flow control enable
1069 * bits in the CTRL register.
1070 *
1071 * The possible values of the "fc" parameter are:
1072 * 0: Flow control is completely disabled
1073 * 1: Rx flow control is enabled (we can receive pause frames,
1074 * but not send pause frames).
1075 * 2: Tx flow control is enabled (we can send pause frames but we
1076 * do not support receiving pause frames).
1077 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1048 */
1078 */
1049 DEBUGOUT("Auto-negotiation enabled\n");
1050
1051 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1052 E1000_WRITE_FLUSH(hw);
1053 msec_delay(1);
1054
1055 /*
1056 * For these adapters, the SW definable pin 1 is set when the optics
1057 * detect a signal. If we have a signal, then poll for a "Link-Up"
1058 * indication.
1059 */
1060 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1061 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1062 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1063 } else {
1064 DEBUGOUT("No signal detected\n");
1079 switch (hw->fc.current_mode) {
1080 case e1000_fc_none:
1081 /* Flow control completely disabled by a software over-ride. */
1082 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1083 break;
1084 case e1000_fc_rx_pause:
1085 /*
1086 * Rx Flow control is enabled and Tx Flow control is disabled
1087 * by a software over-ride. Since there really isn't a way to
1088 * advertise that we are capable of Rx Pause ONLY, we will
1089 * advertise that we support both symmetric and asymmetric Rx
1090 * PAUSE. Later, we will disable the adapter's ability to send
1091 * PAUSE frames.
1092 */
1093 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1094 break;
1095 case e1000_fc_tx_pause:
1096 /*
1097 * Tx Flow control is enabled, and Rx Flow control is disabled,
1098 * by a software over-ride.
1099 */
1100 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1101 break;
1102 case e1000_fc_full:
1103 /*
1104 * Flow control (both Rx and Tx) is enabled by a software
1105 * over-ride.
1106 */
1107 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1108 break;
1109 default:
1110 DEBUGOUT("Flow control param set incorrectly\n");
1111 return -E1000_ERR_CONFIG;
1112 break;
1065 }
1066
1113 }
1114
1067out:
1068 return ret_val;
1069}
1115 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1116 mac->txcw = txcw;
1070
1117
1071/**
1072 * e1000_config_collision_dist_generic - Configure collision distance
1073 * @hw: pointer to the HW structure
1074 *
1075 * Configures the collision distance to the default value and is used
1076 * during link setup.
1077 **/
1078void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1079{
1080 u32 tctl;
1081
1082 DEBUGFUNC("e1000_config_collision_dist_generic");
1083
1084 tctl = E1000_READ_REG(hw, E1000_TCTL);
1085
1086 tctl &= ~E1000_TCTL_COLD;
1087 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1088
1089 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1090 E1000_WRITE_FLUSH(hw);
1118 return E1000_SUCCESS;
1091}
1092
1093/**
1094 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1095 * @hw: pointer to the HW structure
1096 *
1097 * Polls for link up by reading the status register, if link fails to come
1098 * up with auto-negotiation, then the link is forced if a signal is detected.
1099 **/
1100s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1101{
1102 struct e1000_mac_info *mac = &hw->mac;
1103 u32 i, status;
1119}
1120
1121/**
1122 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1123 * @hw: pointer to the HW structure
1124 *
1125 * Polls for link up by reading the status register, if link fails to come
1126 * up with auto-negotiation, then the link is forced if a signal is detected.
1127 **/
1128s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1129{
1130 struct e1000_mac_info *mac = &hw->mac;
1131 u32 i, status;
1104 s32 ret_val = E1000_SUCCESS;
1132 s32 ret_val;
1105
1106 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1107
1108 /*
1109 * If we have a signal (the cable is plugged in, or assumed TRUE for
1110 * serdes media) then poll for a "Link-Up" indication in the Device
1111 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1112 * seconds (Auto-negotiation should complete in less than 500
1113 * milliseconds even if the other end is doing it in SW).
1114 */
1115 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1116 msec_delay(10);
1117 status = E1000_READ_REG(hw, E1000_STATUS);
1118 if (status & E1000_STATUS_LU)
1119 break;
1120 }
1121 if (i == FIBER_LINK_UP_LIMIT) {
1122 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1133
1134 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1135
1136 /*
1137 * If we have a signal (the cable is plugged in, or assumed TRUE for
1138 * serdes media) then poll for a "Link-Up" indication in the Device
1139 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1140 * seconds (Auto-negotiation should complete in less than 500
1141 * milliseconds even if the other end is doing it in SW).
1142 */
1143 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1144 msec_delay(10);
1145 status = E1000_READ_REG(hw, E1000_STATUS);
1146 if (status & E1000_STATUS_LU)
1147 break;
1148 }
1149 if (i == FIBER_LINK_UP_LIMIT) {
1150 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1123 mac->autoneg_failed = 1;
1151 mac->autoneg_failed = TRUE;
1124 /*
1125 * AutoNeg failed to achieve a link, so we'll call
1126 * mac->check_for_link. This routine will force the
1127 * link up if we detect a signal. This will allow us to
1128 * communicate with non-autonegotiating link partners.
1129 */
1130 ret_val = mac->ops.check_for_link(hw);
1131 if (ret_val) {
1132 DEBUGOUT("Error while checking for link\n");
1152 /*
1153 * AutoNeg failed to achieve a link, so we'll call
1154 * mac->check_for_link. This routine will force the
1155 * link up if we detect a signal. This will allow us to
1156 * communicate with non-autonegotiating link partners.
1157 */
1158 ret_val = mac->ops.check_for_link(hw);
1159 if (ret_val) {
1160 DEBUGOUT("Error while checking for link\n");
1133 goto out;
1161 return ret_val;
1134 }
1162 }
1135 mac->autoneg_failed = 0;
1163 mac->autoneg_failed = FALSE;
1136 } else {
1164 } else {
1137 mac->autoneg_failed = 0;
1165 mac->autoneg_failed = FALSE;
1138 DEBUGOUT("Valid Link Found\n");
1139 }
1140
1166 DEBUGOUT("Valid Link Found\n");
1167 }
1168
1141out:
1142 return ret_val;
1169 return E1000_SUCCESS;
1143}
1144
1145/**
1170}
1171
1172/**
1146 * e1000_commit_fc_settings_generic - Configure flow control
1173 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1147 * @hw: pointer to the HW structure
1148 *
1174 * @hw: pointer to the HW structure
1175 *
1149 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1150 * base on the flow control settings in e1000_mac_info.
1176 * Configures collision distance and flow control for fiber and serdes
1177 * links. Upon successful setup, poll for link.
1151 **/
1178 **/
1152s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1179s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1153{
1180{
1154 struct e1000_mac_info *mac = &hw->mac;
1155 u32 txcw;
1156 s32 ret_val = E1000_SUCCESS;
1181 u32 ctrl;
1182 s32 ret_val;
1157
1183
1158 DEBUGFUNC("e1000_commit_fc_settings_generic");
1184 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1159
1185
1186 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1187
1188 /* Take the link out of reset */
1189 ctrl &= ~E1000_CTRL_LRST;
1190
1191 hw->mac.ops.config_collision_dist(hw);
1192
1193 ret_val = e1000_commit_fc_settings_generic(hw);
1194 if (ret_val)
1195 return ret_val;
1196
1160 /*
1197 /*
1161 * Check for a software override of the flow control settings, and
1162 * setup the device accordingly. If auto-negotiation is enabled, then
1163 * software will have to set the "PAUSE" bits to the correct value in
1164 * the Transmit Config Word Register (TXCW) and re-start auto-
1165 * negotiation. However, if auto-negotiation is disabled, then
1166 * software will have to manually configure the two flow control enable
1167 * bits in the CTRL register.
1168 *
1169 * The possible values of the "fc" parameter are:
1170 * 0: Flow control is completely disabled
1171 * 1: Rx flow control is enabled (we can receive pause frames,
1172 * but not send pause frames).
1173 * 2: Tx flow control is enabled (we can send pause frames but we
1174 * do not support receiving pause frames).
1175 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1198 * Since auto-negotiation is enabled, take the link out of reset (the
1199 * link will be in reset, because we previously reset the chip). This
1200 * will restart auto-negotiation. If auto-negotiation is successful
1201 * then the link-up status bit will be set and the flow control enable
1202 * bits (RFCE and TFCE) will be set according to their negotiated value.
1176 */
1203 */
1177 switch (hw->fc.current_mode) {
1178 case e1000_fc_none:
1179 /* Flow control completely disabled by a software over-ride. */
1180 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1181 break;
1182 case e1000_fc_rx_pause:
1183 /*
1184 * Rx Flow control is enabled and Tx Flow control is disabled
1185 * by a software over-ride. Since there really isn't a way to
1186 * advertise that we are capable of Rx Pause ONLY, we will
1187 * advertise that we support both symmetric and asymmetric Rx
1188 * PAUSE. Later, we will disable the adapter's ability to send
1189 * PAUSE frames.
1190 */
1191 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1192 break;
1193 case e1000_fc_tx_pause:
1194 /*
1195 * Tx Flow control is enabled, and Rx Flow control is disabled,
1196 * by a software over-ride.
1197 */
1198 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1199 break;
1200 case e1000_fc_full:
1201 /*
1202 * Flow control (both Rx and Tx) is enabled by a software
1203 * over-ride.
1204 */
1205 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1206 break;
1207 default:
1208 DEBUGOUT("Flow control param set incorrectly\n");
1209 ret_val = -E1000_ERR_CONFIG;
1210 goto out;
1211 break;
1212 }
1204 DEBUGOUT("Auto-negotiation enabled\n");
1213
1205
1214 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1215 mac->txcw = txcw;
1206 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1207 E1000_WRITE_FLUSH(hw);
1208 msec_delay(1);
1216
1209
1217out:
1210 /*
1211 * For these adapters, the SW definable pin 1 is set when the optics
1212 * detect a signal. If we have a signal, then poll for a "Link-Up"
1213 * indication.
1214 */
1215 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1216 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1217 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1218 } else {
1219 DEBUGOUT("No signal detected\n");
1220 }
1221
1218 return ret_val;
1219}
1220
1221/**
1222 return ret_val;
1223}
1224
1225/**
1226 * e1000_config_collision_dist_generic - Configure collision distance
1227 * @hw: pointer to the HW structure
1228 *
1229 * Configures the collision distance to the default value and is used
1230 * during link setup.
1231 **/
1232static void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1233{
1234 u32 tctl;
1235
1236 DEBUGFUNC("e1000_config_collision_dist_generic");
1237
1238 tctl = E1000_READ_REG(hw, E1000_TCTL);
1239
1240 tctl &= ~E1000_TCTL_COLD;
1241 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1242
1243 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1244 E1000_WRITE_FLUSH(hw);
1245}
1246
1247/**
1222 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1223 * @hw: pointer to the HW structure
1224 *
1225 * Sets the flow control high/low threshold (watermark) registers. If
1226 * flow control XON frame transmission is enabled, then set XON frame
1227 * transmission as well.
1228 **/
1229s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)

--- 23 unchanged lines hidden (view full) ---

1253 }
1254 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1255 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1256
1257 return E1000_SUCCESS;
1258}
1259
1260/**
1248 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1249 * @hw: pointer to the HW structure
1250 *
1251 * Sets the flow control high/low threshold (watermark) registers. If
1252 * flow control XON frame transmission is enabled, then set XON frame
1253 * transmission as well.
1254 **/
1255s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)

--- 23 unchanged lines hidden (view full) ---

1279 }
1280 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1281 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1282
1283 return E1000_SUCCESS;
1284}
1285
1286/**
1261 * e1000_set_default_fc_generic - Set flow control default values
1262 * @hw: pointer to the HW structure
1263 *
1264 * Read the EEPROM for the default values for flow control and store the
1265 * values.
1266 **/
1267s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1268{
1269 s32 ret_val = E1000_SUCCESS;
1270 u16 nvm_data;
1271
1272 DEBUGFUNC("e1000_set_default_fc_generic");
1273
1274 /*
1275 * Read and store word 0x0F of the EEPROM. This word contains bits
1276 * that determine the hardware's default PAUSE (flow control) mode,
1277 * a bit that determines whether the HW defaults to enabling or
1278 * disabling auto-negotiation, and the direction of the
1279 * SW defined pins. If there is no SW over-ride of the flow
1280 * control setting, then the variable hw->fc will
1281 * be initialized based on a value in the EEPROM.
1282 */
1283 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1284
1285 if (ret_val) {
1286 DEBUGOUT("NVM Read Error\n");
1287 goto out;
1288 }
1289
1290 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1291 hw->fc.requested_mode = e1000_fc_none;
1292 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1293 NVM_WORD0F_ASM_DIR)
1294 hw->fc.requested_mode = e1000_fc_tx_pause;
1295 else
1296 hw->fc.requested_mode = e1000_fc_full;
1297
1298out:
1299 return ret_val;
1300}
1301
1302/**
1303 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1304 * @hw: pointer to the HW structure
1305 *
1306 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1307 * device control register to reflect the adapter settings. TFCE and RFCE
1308 * need to be explicitly set by software when a copper PHY is used because
1309 * autonegotiation is managed by the PHY rather than the MAC. Software must
1310 * also configure these bits when link is forced on a fiber connection.
1311 **/
1312s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1313{
1314 u32 ctrl;
1287 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1288 * @hw: pointer to the HW structure
1289 *
1290 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1291 * device control register to reflect the adapter settings. TFCE and RFCE
1292 * need to be explicitly set by software when a copper PHY is used because
1293 * autonegotiation is managed by the PHY rather than the MAC. Software must
1294 * also configure these bits when link is forced on a fiber connection.
1295 **/
1296s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1297{
1298 u32 ctrl;
1315 s32 ret_val = E1000_SUCCESS;
1316
1317 DEBUGFUNC("e1000_force_mac_fc_generic");
1318
1319 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1320
1321 /*
1322 * Because we didn't get link via the internal auto-negotiation
1323 * mechanism (we either forced link or we got link via PHY

--- 26 unchanged lines hidden (view full) ---

1350 ctrl &= (~E1000_CTRL_RFCE);
1351 ctrl |= E1000_CTRL_TFCE;
1352 break;
1353 case e1000_fc_full:
1354 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1355 break;
1356 default:
1357 DEBUGOUT("Flow control param set incorrectly\n");
1299
1300 DEBUGFUNC("e1000_force_mac_fc_generic");
1301
1302 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1303
1304 /*
1305 * Because we didn't get link via the internal auto-negotiation
1306 * mechanism (we either forced link or we got link via PHY

--- 26 unchanged lines hidden (view full) ---

1333 ctrl &= (~E1000_CTRL_RFCE);
1334 ctrl |= E1000_CTRL_TFCE;
1335 break;
1336 case e1000_fc_full:
1337 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1338 break;
1339 default:
1340 DEBUGOUT("Flow control param set incorrectly\n");
1358 ret_val = -E1000_ERR_CONFIG;
1359 goto out;
1341 return -E1000_ERR_CONFIG;
1360 }
1361
1362 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1363
1342 }
1343
1344 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1345
1364out:
1365 return ret_val;
1346 return E1000_SUCCESS;
1366}
1367
1368/**
1369 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1370 * @hw: pointer to the HW structure
1371 *
1372 * Checks the status of auto-negotiation after link up to ensure that the
1373 * speed and duplex were not forced. If the link needed to be forced, then

--- 21 unchanged lines hidden (view full) ---

1395 ret_val = e1000_force_mac_fc_generic(hw);
1396 } else {
1397 if (hw->phy.media_type == e1000_media_type_copper)
1398 ret_val = e1000_force_mac_fc_generic(hw);
1399 }
1400
1401 if (ret_val) {
1402 DEBUGOUT("Error forcing flow control settings\n");
1347}
1348
1349/**
1350 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1351 * @hw: pointer to the HW structure
1352 *
1353 * Checks the status of auto-negotiation after link up to ensure that the
1354 * speed and duplex were not forced. If the link needed to be forced, then

--- 21 unchanged lines hidden (view full) ---

1376 ret_val = e1000_force_mac_fc_generic(hw);
1377 } else {
1378 if (hw->phy.media_type == e1000_media_type_copper)
1379 ret_val = e1000_force_mac_fc_generic(hw);
1380 }
1381
1382 if (ret_val) {
1383 DEBUGOUT("Error forcing flow control settings\n");
1403 goto out;
1384 return ret_val;
1404 }
1405
1406 /*
1407 * Check for the case where we have copper media and auto-neg is
1408 * enabled. In this case, we need to check and see if Auto-Neg
1409 * has completed, and if so, how the PHY and link partner has
1410 * flow control configured.
1411 */
1412 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1413 /*
1414 * Read the MII Status Register and check to see if AutoNeg
1415 * has completed. We read this twice because this reg has
1416 * some "sticky" (latched) bits.
1417 */
1418 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1419 if (ret_val)
1385 }
1386
1387 /*
1388 * Check for the case where we have copper media and auto-neg is
1389 * enabled. In this case, we need to check and see if Auto-Neg
1390 * has completed, and if so, how the PHY and link partner has
1391 * flow control configured.
1392 */
1393 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1394 /*
1395 * Read the MII Status Register and check to see if AutoNeg
1396 * has completed. We read this twice because this reg has
1397 * some "sticky" (latched) bits.
1398 */
1399 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1400 if (ret_val)
1420 goto out;
1401 return ret_val;
1421 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1422 if (ret_val)
1402 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1403 if (ret_val)
1423 goto out;
1404 return ret_val;
1424
1425 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1426 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1405
1406 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1407 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1427 goto out;
1408 return ret_val;
1428 }
1429
1430 /*
1431 * The AutoNeg process has completed, so we now need to
1432 * read both the Auto Negotiation Advertisement
1433 * Register (Address 4) and the Auto_Negotiation Base
1434 * Page Ability Register (Address 5) to determine how
1435 * flow control was negotiated.
1436 */
1437 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1438 &mii_nway_adv_reg);
1439 if (ret_val)
1409 }
1410
1411 /*
1412 * The AutoNeg process has completed, so we now need to
1413 * read both the Auto Negotiation Advertisement
1414 * Register (Address 4) and the Auto_Negotiation Base
1415 * Page Ability Register (Address 5) to determine how
1416 * flow control was negotiated.
1417 */
1418 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1419 &mii_nway_adv_reg);
1420 if (ret_val)
1440 goto out;
1421 return ret_val;
1441 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1442 &mii_nway_lp_ability_reg);
1443 if (ret_val)
1422 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1423 &mii_nway_lp_ability_reg);
1424 if (ret_val)
1444 goto out;
1425 return ret_val;
1445
1446 /*
1447 * Two bits in the Auto Negotiation Advertisement Register
1448 * (Address 4) and two bits in the Auto Negotiation Base
1449 * Page Ability Register (Address 5) determine flow control
1450 * for both the PHY and the link partner. The following
1451 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1452 * 1999, describes these PAUSE resolution bits and how flow

--- 82 unchanged lines hidden (view full) ---

1535 /*
1536 * Now we need to do one last check... If we auto-
1537 * negotiated to HALF DUPLEX, flow control should not be
1538 * enabled per IEEE 802.3 spec.
1539 */
1540 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1541 if (ret_val) {
1542 DEBUGOUT("Error getting link speed and duplex\n");
1426
1427 /*
1428 * Two bits in the Auto Negotiation Advertisement Register
1429 * (Address 4) and two bits in the Auto Negotiation Base
1430 * Page Ability Register (Address 5) determine flow control
1431 * for both the PHY and the link partner. The following
1432 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1433 * 1999, describes these PAUSE resolution bits and how flow

--- 82 unchanged lines hidden (view full) ---

1516 /*
1517 * Now we need to do one last check... If we auto-
1518 * negotiated to HALF DUPLEX, flow control should not be
1519 * enabled per IEEE 802.3 spec.
1520 */
1521 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1522 if (ret_val) {
1523 DEBUGOUT("Error getting link speed and duplex\n");
1543 goto out;
1524 return ret_val;
1544 }
1545
1546 if (duplex == HALF_DUPLEX)
1547 hw->fc.current_mode = e1000_fc_none;
1548
1549 /*
1550 * Now we call a subroutine to actually force the MAC
1551 * controller to use the correct flow control settings.
1552 */
1553 ret_val = e1000_force_mac_fc_generic(hw);
1554 if (ret_val) {
1555 DEBUGOUT("Error forcing flow control settings\n");
1525 }
1526
1527 if (duplex == HALF_DUPLEX)
1528 hw->fc.current_mode = e1000_fc_none;
1529
1530 /*
1531 * Now we call a subroutine to actually force the MAC
1532 * controller to use the correct flow control settings.
1533 */
1534 ret_val = e1000_force_mac_fc_generic(hw);
1535 if (ret_val) {
1536 DEBUGOUT("Error forcing flow control settings\n");
1556 goto out;
1537 return ret_val;
1557 }
1558 }
1559
1538 }
1539 }
1540
1560out:
1561 return ret_val;
1541 return E1000_SUCCESS;
1562}
1563
1564/**
1565 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1566 * @hw: pointer to the HW structure
1567 * @speed: stores the current speed
1568 * @duplex: stores the current duplex
1569 *

--- 54 unchanged lines hidden (view full) ---

1624 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1625 * @hw: pointer to the HW structure
1626 *
1627 * Acquire the HW semaphore to access the PHY or NVM
1628 **/
1629s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1630{
1631 u32 swsm;
1542}
1543
1544/**
1545 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1546 * @hw: pointer to the HW structure
1547 * @speed: stores the current speed
1548 * @duplex: stores the current duplex
1549 *

--- 54 unchanged lines hidden (view full) ---

1604 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1605 * @hw: pointer to the HW structure
1606 *
1607 * Acquire the HW semaphore to access the PHY or NVM
1608 **/
1609s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1610{
1611 u32 swsm;
1632 s32 ret_val = E1000_SUCCESS;
1633 s32 timeout = hw->nvm.word_size + 1;
1634 s32 i = 0;
1635
1636 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1637
1638 /* Get the SW semaphore */
1639 while (i < timeout) {
1640 swsm = E1000_READ_REG(hw, E1000_SWSM);
1641 if (!(swsm & E1000_SWSM_SMBI))
1642 break;
1643
1644 usec_delay(50);
1645 i++;
1646 }
1647
1648 if (i == timeout) {
1649 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1612 s32 timeout = hw->nvm.word_size + 1;
1613 s32 i = 0;
1614
1615 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1616
1617 /* Get the SW semaphore */
1618 while (i < timeout) {
1619 swsm = E1000_READ_REG(hw, E1000_SWSM);
1620 if (!(swsm & E1000_SWSM_SMBI))
1621 break;
1622
1623 usec_delay(50);
1624 i++;
1625 }
1626
1627 if (i == timeout) {
1628 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1650 ret_val = -E1000_ERR_NVM;
1651 goto out;
1629 return -E1000_ERR_NVM;
1652 }
1653
1654 /* Get the FW semaphore. */
1655 for (i = 0; i < timeout; i++) {
1656 swsm = E1000_READ_REG(hw, E1000_SWSM);
1657 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1658
1659 /* Semaphore acquired if bit latched */
1660 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1661 break;
1662
1663 usec_delay(50);
1664 }
1665
1666 if (i == timeout) {
1667 /* Release semaphores */
1668 e1000_put_hw_semaphore_generic(hw);
1669 DEBUGOUT("Driver can't access the NVM\n");
1630 }
1631
1632 /* Get the FW semaphore. */
1633 for (i = 0; i < timeout; i++) {
1634 swsm = E1000_READ_REG(hw, E1000_SWSM);
1635 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1636
1637 /* Semaphore acquired if bit latched */
1638 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1639 break;
1640
1641 usec_delay(50);
1642 }
1643
1644 if (i == timeout) {
1645 /* Release semaphores */
1646 e1000_put_hw_semaphore_generic(hw);
1647 DEBUGOUT("Driver can't access the NVM\n");
1670 ret_val = -E1000_ERR_NVM;
1671 goto out;
1648 return -E1000_ERR_NVM;
1672 }
1673
1649 }
1650
1674out:
1675 return ret_val;
1651 return E1000_SUCCESS;
1676}
1677
1678/**
1679 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1680 * @hw: pointer to the HW structure
1681 *
1682 * Release hardware semaphore used to access the PHY or NVM
1683 **/

--- 14 unchanged lines hidden (view full) ---

1698 * e1000_get_auto_rd_done_generic - Check for auto read completion
1699 * @hw: pointer to the HW structure
1700 *
1701 * Check EEPROM for Auto Read done bit.
1702 **/
1703s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1704{
1705 s32 i = 0;
1652}
1653
1654/**
1655 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1656 * @hw: pointer to the HW structure
1657 *
1658 * Release hardware semaphore used to access the PHY or NVM
1659 **/

--- 14 unchanged lines hidden (view full) ---

1674 * e1000_get_auto_rd_done_generic - Check for auto read completion
1675 * @hw: pointer to the HW structure
1676 *
1677 * Check EEPROM for Auto Read done bit.
1678 **/
1679s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1680{
1681 s32 i = 0;
1706 s32 ret_val = E1000_SUCCESS;
1707
1708 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1709
1710 while (i < AUTO_READ_DONE_TIMEOUT) {
1711 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1712 break;
1713 msec_delay(1);
1714 i++;
1715 }
1716
1717 if (i == AUTO_READ_DONE_TIMEOUT) {
1718 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1682
1683 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1684
1685 while (i < AUTO_READ_DONE_TIMEOUT) {
1686 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1687 break;
1688 msec_delay(1);
1689 i++;
1690 }
1691
1692 if (i == AUTO_READ_DONE_TIMEOUT) {
1693 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1719 ret_val = -E1000_ERR_RESET;
1720 goto out;
1694 return -E1000_ERR_RESET;
1721 }
1722
1695 }
1696
1723out:
1724 return ret_val;
1697 return E1000_SUCCESS;
1725}
1726
1727/**
1728 * e1000_valid_led_default_generic - Verify a valid default LED config
1729 * @hw: pointer to the HW structure
1730 * @data: pointer to the NVM (EEPROM)
1731 *
1732 * Read the EEPROM for the current default LED configuration. If the
1733 * LED configuration is not valid, set to a valid LED configuration.
1734 **/
1735s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1736{
1737 s32 ret_val;
1738
1739 DEBUGFUNC("e1000_valid_led_default_generic");
1740
1741 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1742 if (ret_val) {
1743 DEBUGOUT("NVM Read Error\n");
1698}
1699
1700/**
1701 * e1000_valid_led_default_generic - Verify a valid default LED config
1702 * @hw: pointer to the HW structure
1703 * @data: pointer to the NVM (EEPROM)
1704 *
1705 * Read the EEPROM for the current default LED configuration. If the
1706 * LED configuration is not valid, set to a valid LED configuration.
1707 **/
1708s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1709{
1710 s32 ret_val;
1711
1712 DEBUGFUNC("e1000_valid_led_default_generic");
1713
1714 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1715 if (ret_val) {
1716 DEBUGOUT("NVM Read Error\n");
1744 goto out;
1717 return ret_val;
1745 }
1746
1747 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1748 *data = ID_LED_DEFAULT;
1749
1718 }
1719
1720 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1721 *data = ID_LED_DEFAULT;
1722
1750out:
1751 return ret_val;
1723 return E1000_SUCCESS;
1752}
1753
1754/**
1755 * e1000_id_led_init_generic -
1756 * @hw: pointer to the HW structure
1757 *
1758 **/
1759s32 e1000_id_led_init_generic(struct e1000_hw *hw)

--- 5 unchanged lines hidden (view full) ---

1765 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1766 u16 data, i, temp;
1767 const u16 led_mask = 0x0F;
1768
1769 DEBUGFUNC("e1000_id_led_init_generic");
1770
1771 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1772 if (ret_val)
1724}
1725
1726/**
1727 * e1000_id_led_init_generic -
1728 * @hw: pointer to the HW structure
1729 *
1730 **/
1731s32 e1000_id_led_init_generic(struct e1000_hw *hw)

--- 5 unchanged lines hidden (view full) ---

1737 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1738 u16 data, i, temp;
1739 const u16 led_mask = 0x0F;
1740
1741 DEBUGFUNC("e1000_id_led_init_generic");
1742
1743 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1744 if (ret_val)
1773 goto out;
1745 return ret_val;
1774
1775 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1776 mac->ledctl_mode1 = mac->ledctl_default;
1777 mac->ledctl_mode2 = mac->ledctl_default;
1778
1779 for (i = 0; i < 4; i++) {
1780 temp = (data >> (i << 2)) & led_mask;
1781 switch (temp) {

--- 27 unchanged lines hidden (view full) ---

1809 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1810 break;
1811 default:
1812 /* Do nothing */
1813 break;
1814 }
1815 }
1816
1746
1747 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1748 mac->ledctl_mode1 = mac->ledctl_default;
1749 mac->ledctl_mode2 = mac->ledctl_default;
1750
1751 for (i = 0; i < 4; i++) {
1752 temp = (data >> (i << 2)) & led_mask;
1753 switch (temp) {

--- 27 unchanged lines hidden (view full) ---

1781 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1782 break;
1783 default:
1784 /* Do nothing */
1785 break;
1786 }
1787 }
1788
1817out:
1818 return ret_val;
1789 return E1000_SUCCESS;
1819}
1820
1821/**
1822 * e1000_setup_led_generic - Configures SW controllable LED
1823 * @hw: pointer to the HW structure
1824 *
1825 * This prepares the SW controllable LED for use and saves the current state
1826 * of the LED so it can be later restored.
1827 **/
1828s32 e1000_setup_led_generic(struct e1000_hw *hw)
1829{
1830 u32 ledctl;
1790}
1791
1792/**
1793 * e1000_setup_led_generic - Configures SW controllable LED
1794 * @hw: pointer to the HW structure
1795 *
1796 * This prepares the SW controllable LED for use and saves the current state
1797 * of the LED so it can be later restored.
1798 **/
1799s32 e1000_setup_led_generic(struct e1000_hw *hw)
1800{
1801 u32 ledctl;
1831 s32 ret_val = E1000_SUCCESS;
1832
1833 DEBUGFUNC("e1000_setup_led_generic");
1834
1802
1803 DEBUGFUNC("e1000_setup_led_generic");
1804
1835 if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
1836 ret_val = -E1000_ERR_CONFIG;
1837 goto out;
1838 }
1805 if (hw->mac.ops.setup_led != e1000_setup_led_generic)
1806 return -E1000_ERR_CONFIG;
1839
1840 if (hw->phy.media_type == e1000_media_type_fiber) {
1841 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1842 hw->mac.ledctl_default = ledctl;
1843 /* Turn off LED0 */
1844 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1845 E1000_LEDCTL_LED0_MODE_MASK);
1846 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1847 E1000_LEDCTL_LED0_MODE_SHIFT);
1848 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1849 } else if (hw->phy.media_type == e1000_media_type_copper) {
1850 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1851 }
1852
1807
1808 if (hw->phy.media_type == e1000_media_type_fiber) {
1809 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1810 hw->mac.ledctl_default = ledctl;
1811 /* Turn off LED0 */
1812 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
1813 E1000_LEDCTL_LED0_MODE_MASK);
1814 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1815 E1000_LEDCTL_LED0_MODE_SHIFT);
1816 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1817 } else if (hw->phy.media_type == e1000_media_type_copper) {
1818 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1819 }
1820
1853out:
1854 return ret_val;
1821 return E1000_SUCCESS;
1855}
1856
1857/**
1858 * e1000_cleanup_led_generic - Set LED config to default operation
1859 * @hw: pointer to the HW structure
1860 *
1861 * Remove the current LED configuration and set the LED configuration
1862 * to the default value, saved from the EEPROM.

--- 108 unchanged lines hidden (view full) ---

1971 **/
1972void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1973{
1974 u32 gcr;
1975
1976 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1977
1978 if (hw->bus.type != e1000_bus_type_pci_express)
1822}
1823
1824/**
1825 * e1000_cleanup_led_generic - Set LED config to default operation
1826 * @hw: pointer to the HW structure
1827 *
1828 * Remove the current LED configuration and set the LED configuration
1829 * to the default value, saved from the EEPROM.

--- 108 unchanged lines hidden (view full) ---

1938 **/
1939void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1940{
1941 u32 gcr;
1942
1943 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1944
1945 if (hw->bus.type != e1000_bus_type_pci_express)
1979 goto out;
1946 return;
1980
1981 if (no_snoop) {
1982 gcr = E1000_READ_REG(hw, E1000_GCR);
1983 gcr &= ~(PCIE_NO_SNOOP_ALL);
1984 gcr |= no_snoop;
1985 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1986 }
1947
1948 if (no_snoop) {
1949 gcr = E1000_READ_REG(hw, E1000_GCR);
1950 gcr &= ~(PCIE_NO_SNOOP_ALL);
1951 gcr |= no_snoop;
1952 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1953 }
1987out:
1988 return;
1989}
1990
1991/**
1992 * e1000_disable_pcie_master_generic - Disables PCI-express master access
1993 * @hw: pointer to the HW structure
1994 *
1995 * Returns E1000_SUCCESS if successful, else returns -10
1996 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1997 * the master requests to be disabled.
1998 *
1999 * Disables PCI-Express master access and verifies there are no pending
2000 * requests.
2001 **/
2002s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2003{
2004 u32 ctrl;
2005 s32 timeout = MASTER_DISABLE_TIMEOUT;
1954}
1955
1956/**
1957 * e1000_disable_pcie_master_generic - Disables PCI-express master access
1958 * @hw: pointer to the HW structure
1959 *
1960 * Returns E1000_SUCCESS if successful, else returns -10
1961 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1962 * the master requests to be disabled.
1963 *
1964 * Disables PCI-Express master access and verifies there are no pending
1965 * requests.
1966 **/
1967s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
1968{
1969 u32 ctrl;
1970 s32 timeout = MASTER_DISABLE_TIMEOUT;
2006 s32 ret_val = E1000_SUCCESS;
2007
2008 DEBUGFUNC("e1000_disable_pcie_master_generic");
2009
2010 if (hw->bus.type != e1000_bus_type_pci_express)
1971
1972 DEBUGFUNC("e1000_disable_pcie_master_generic");
1973
1974 if (hw->bus.type != e1000_bus_type_pci_express)
2011 goto out;
1975 return E1000_SUCCESS;
2012
2013 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2014 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2015 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2016
2017 while (timeout) {
2018 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2019 E1000_STATUS_GIO_MASTER_ENABLE))
2020 break;
2021 usec_delay(100);
2022 timeout--;
2023 }
2024
2025 if (!timeout) {
2026 DEBUGOUT("Master requests are pending.\n");
1976
1977 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1978 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1979 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1980
1981 while (timeout) {
1982 if (!(E1000_READ_REG(hw, E1000_STATUS) &
1983 E1000_STATUS_GIO_MASTER_ENABLE))
1984 break;
1985 usec_delay(100);
1986 timeout--;
1987 }
1988
1989 if (!timeout) {
1990 DEBUGOUT("Master requests are pending.\n");
2027 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
1991 return -E1000_ERR_MASTER_REQUESTS_PENDING;
2028 }
2029
1992 }
1993
2030out:
2031 return ret_val;
1994 return E1000_SUCCESS;
2032}
2033
2034/**
2035 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2036 * @hw: pointer to the HW structure
2037 *
2038 * Reset the Adaptive Interframe Spacing throttle to default values.
2039 **/
2040void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2041{
2042 struct e1000_mac_info *mac = &hw->mac;
2043
2044 DEBUGFUNC("e1000_reset_adaptive_generic");
2045
2046 if (!mac->adaptive_ifs) {
2047 DEBUGOUT("Not in Adaptive IFS mode!\n");
1995}
1996
1997/**
1998 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
1999 * @hw: pointer to the HW structure
2000 *
2001 * Reset the Adaptive Interframe Spacing throttle to default values.
2002 **/
2003void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2004{
2005 struct e1000_mac_info *mac = &hw->mac;
2006
2007 DEBUGFUNC("e1000_reset_adaptive_generic");
2008
2009 if (!mac->adaptive_ifs) {
2010 DEBUGOUT("Not in Adaptive IFS mode!\n");
2048 goto out;
2011 return;
2049 }
2050
2051 mac->current_ifs_val = 0;
2052 mac->ifs_min_val = IFS_MIN;
2053 mac->ifs_max_val = IFS_MAX;
2054 mac->ifs_step_size = IFS_STEP;
2055 mac->ifs_ratio = IFS_RATIO;
2056
2057 mac->in_ifs_mode = FALSE;
2058 E1000_WRITE_REG(hw, E1000_AIT, 0);
2012 }
2013
2014 mac->current_ifs_val = 0;
2015 mac->ifs_min_val = IFS_MIN;
2016 mac->ifs_max_val = IFS_MAX;
2017 mac->ifs_step_size = IFS_STEP;
2018 mac->ifs_ratio = IFS_RATIO;
2019
2020 mac->in_ifs_mode = FALSE;
2021 E1000_WRITE_REG(hw, E1000_AIT, 0);
2059out:
2060 return;
2061}
2062
2063/**
2064 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2065 * @hw: pointer to the HW structure
2066 *
2067 * Update the Adaptive Interframe Spacing Throttle value based on the
2068 * time between transmitted packets and time between collisions.
2069 **/
2070void e1000_update_adaptive_generic(struct e1000_hw *hw)
2071{
2072 struct e1000_mac_info *mac = &hw->mac;
2073
2074 DEBUGFUNC("e1000_update_adaptive_generic");
2075
2076 if (!mac->adaptive_ifs) {
2077 DEBUGOUT("Not in Adaptive IFS mode!\n");
2022}
2023
2024/**
2025 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2026 * @hw: pointer to the HW structure
2027 *
2028 * Update the Adaptive Interframe Spacing Throttle value based on the
2029 * time between transmitted packets and time between collisions.
2030 **/
2031void e1000_update_adaptive_generic(struct e1000_hw *hw)
2032{
2033 struct e1000_mac_info *mac = &hw->mac;
2034
2035 DEBUGFUNC("e1000_update_adaptive_generic");
2036
2037 if (!mac->adaptive_ifs) {
2038 DEBUGOUT("Not in Adaptive IFS mode!\n");
2078 goto out;
2039 return;
2079 }
2080
2081 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2082 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2083 mac->in_ifs_mode = TRUE;
2084 if (mac->current_ifs_val < mac->ifs_max_val) {
2085 if (!mac->current_ifs_val)
2086 mac->current_ifs_val = mac->ifs_min_val;

--- 7 unchanged lines hidden (view full) ---

2094 } else {
2095 if (mac->in_ifs_mode &&
2096 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2097 mac->current_ifs_val = 0;
2098 mac->in_ifs_mode = FALSE;
2099 E1000_WRITE_REG(hw, E1000_AIT, 0);
2100 }
2101 }
2040 }
2041
2042 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2043 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2044 mac->in_ifs_mode = TRUE;
2045 if (mac->current_ifs_val < mac->ifs_max_val) {
2046 if (!mac->current_ifs_val)
2047 mac->current_ifs_val = mac->ifs_min_val;

--- 7 unchanged lines hidden (view full) ---

2055 } else {
2056 if (mac->in_ifs_mode &&
2057 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2058 mac->current_ifs_val = 0;
2059 mac->in_ifs_mode = FALSE;
2060 E1000_WRITE_REG(hw, E1000_AIT, 0);
2061 }
2062 }
2102out:
2103 return;
2104}
2105
2106/**
2107 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2108 * @hw: pointer to the HW structure
2109 *
2110 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2111 * set, which is forced to MDI mode only.
2112 **/
2113static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2114{
2063}
2064
2065/**
2066 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2067 * @hw: pointer to the HW structure
2068 *
2069 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2070 * set, which is forced to MDI mode only.
2071 **/
2072static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2073{
2115 s32 ret_val = E1000_SUCCESS;
2116
2117 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2118
2119 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2120 DEBUGOUT("Invalid MDI setting detected\n");
2121 hw->phy.mdix = 1;
2074 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2075
2076 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2077 DEBUGOUT("Invalid MDI setting detected\n");
2078 hw->phy.mdix = 1;
2122 ret_val = -E1000_ERR_CONFIG;
2123 goto out;
2079 return -E1000_ERR_CONFIG;
2124 }
2125
2080 }
2081
2126out:
2127 return ret_val;
2082 return E1000_SUCCESS;
2128}
2129
2130/**
2131 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2132 * @hw: pointer to the HW structure
2133 * @reg: 32bit register offset such as E1000_SCTL
2134 * @offset: register offset to write to
2135 * @data: data to write at register offset
2136 *
2137 * Writes an address/data control type register. There are several of these
2138 * and they all have the format address << 8 | data and bit 31 is polled for
2139 * completion.
2140 **/
2141s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2142 u32 offset, u8 data)
2143{
2144 u32 i, regvalue = 0;
2083}
2084
2085/**
2086 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2087 * @hw: pointer to the HW structure
2088 * @reg: 32bit register offset such as E1000_SCTL
2089 * @offset: register offset to write to
2090 * @data: data to write at register offset
2091 *
2092 * Writes an address/data control type register. There are several of these
2093 * and they all have the format address << 8 | data and bit 31 is polled for
2094 * completion.
2095 **/
2096s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2097 u32 offset, u8 data)
2098{
2099 u32 i, regvalue = 0;
2145 s32 ret_val = E1000_SUCCESS;
2146
2147 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2148
2149 /* Set up the address and data */
2150 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2151 E1000_WRITE_REG(hw, reg, regvalue);
2152
2153 /* Poll the ready bit to see if the MDI read completed */
2154 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2155 usec_delay(5);
2156 regvalue = E1000_READ_REG(hw, reg);
2157 if (regvalue & E1000_GEN_CTL_READY)
2158 break;
2159 }
2160 if (!(regvalue & E1000_GEN_CTL_READY)) {
2161 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2100
2101 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2102
2103 /* Set up the address and data */
2104 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2105 E1000_WRITE_REG(hw, reg, regvalue);
2106
2107 /* Poll the ready bit to see if the MDI read completed */
2108 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2109 usec_delay(5);
2110 regvalue = E1000_READ_REG(hw, reg);
2111 if (regvalue & E1000_GEN_CTL_READY)
2112 break;
2113 }
2114 if (!(regvalue & E1000_GEN_CTL_READY)) {
2115 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2162 ret_val = -E1000_ERR_PHY;
2163 goto out;
2116 return -E1000_ERR_PHY;
2164 }
2165
2117 }
2118
2166out:
2167 return ret_val;
2119 return E1000_SUCCESS;
2168}
2120}