| e1000_ich8lan.h (213234) | e1000_ich8lan.h (218588) |
|---|---|
| 1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.h 213234 2010-09-28 00:13:15Z jfv $*/ | 33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.h 218588 2011-02-12 00:07:40Z jfv $*/ |
| 34 35#ifndef _E1000_ICH8LAN_H_ 36#define _E1000_ICH8LAN_H_ 37 38#define ICH_FLASH_GFPREG 0x0000 39#define ICH_FLASH_HSFSTS 0x0004 40#define ICH_FLASH_HSFCTL 0x0006 41#define ICH_FLASH_FADDR 0x0008 --- 104 unchanged lines hidden (view full) --- 146#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 147#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 148#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 149#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 150#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 151#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 152#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 153 | 34 35#ifndef _E1000_ICH8LAN_H_ 36#define _E1000_ICH8LAN_H_ 37 38#define ICH_FLASH_GFPREG 0x0000 39#define ICH_FLASH_HSFSTS 0x0004 40#define ICH_FLASH_HSFCTL 0x0006 41#define ICH_FLASH_FADDR 0x0008 --- 104 unchanged lines hidden (view full) --- 146#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 147#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 148#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 149#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 150#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 151#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 152#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 153 |
| 154#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ | 154#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ |
| 155#define HV_MUX_DATA_CTRL PHY_REG(776, 16) 156#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 157#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 | 155#define HV_MUX_DATA_CTRL PHY_REG(776, 16) 156#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 157#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 |
| 158#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */ 159#define HV_SCC_LOWER PHY_REG(778, 17) 160#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */ 161#define HV_ECOL_LOWER PHY_REG(778, 19) 162#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */ 163#define HV_MCC_LOWER PHY_REG(778, 21) 164#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */ 165#define HV_LATECOL_LOWER PHY_REG(778, 24) 166#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */ 167#define HV_COLC_LOWER PHY_REG(778, 26) 168#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */ 169#define HV_DC_LOWER PHY_REG(778, 28) 170#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ 171#define HV_TNCRS_LOWER PHY_REG(778, 30) | 158#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */ 159#define HV_SCC_LOWER PHY_REG(778, 17) 160#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */ 161#define HV_ECOL_LOWER PHY_REG(778, 19) 162#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */ 163#define HV_MCC_LOWER PHY_REG(778, 21) 164#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */ 165#define HV_LATECOL_LOWER PHY_REG(778, 24) 166#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */ 167#define HV_COLC_LOWER PHY_REG(778, 26) 168#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */ 169#define HV_DC_LOWER PHY_REG(778, 28) 170#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ 171#define HV_TNCRS_LOWER PHY_REG(778, 30) |
| 172 173#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 174 175#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 176#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 177 178/* SMBus Address Phy Register */ 179#define HV_SMB_ADDR PHY_REG(768, 26) --- 10 unchanged lines hidden (view full) --- 190#define HV_OEM_BITS PHY_REG(768, 25) 191#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 192#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 193#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ 194 195#define LCD_CFG_PHY_ADDR_BIT 0x0020 /* Phy address bit from LCD Config word */ 196 197/* KMRN Mode Control */ | 172 173#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 174 175#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 176#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 177 178/* SMBus Address Phy Register */ 179#define HV_SMB_ADDR PHY_REG(768, 26) --- 10 unchanged lines hidden (view full) --- 190#define HV_OEM_BITS PHY_REG(768, 25) 191#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 192#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 193#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ 194 195#define LCD_CFG_PHY_ADDR_BIT 0x0020 /* Phy address bit from LCD Config word */ 196 197/* KMRN Mode Control */ |
| 198#define HV_KMRN_MODE_CTRL PHY_REG(769, 16) 199#define HV_KMRN_MDIO_SLOW 0x0400 | 198#define HV_KMRN_MODE_CTRL PHY_REG(769, 16) 199#define HV_KMRN_MDIO_SLOW 0x0400 |
| 200 201/* PHY Power Management Control */ | 200 201/* PHY Power Management Control */ |
| 202#define HV_PM_CTRL PHY_REG(770, 17) | 202#define HV_PM_CTRL PHY_REG(770, 17) |
| 203 204#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */ 205 206/* PHY Low Power Idle Control */ | 203 204#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */ 205 206/* PHY Low Power Idle Control */ |
| 207#define I82579_LPI_CTRL PHY_REG(772, 20) 208#define I82579_LPI_CTRL_ENABLE_MASK 0x6000 | 207#define I82579_LPI_CTRL PHY_REG(772, 20) 208#define I82579_LPI_CTRL_ENABLE_MASK 0x6000 |
| 209 | 209 |
| 210/* EMI Registers */ 211#define I82579_EMI_ADDR 0x10 212#define I82579_EMI_DATA 0x11 213#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ 214 |
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| 210/* 211 * Additional interrupts need to be handled for ICH family: 212 * DSW = The FW changed the status of the DISSW bit in FWSM 213 * PHYINT = The LAN connected device generates an interrupt 214 * EPRST = Manageability reset event 215 */ 216#define IMS_ICH_ENABLE_MASK (\ 217 E1000_IMS_DSW | \ --- 8 unchanged lines hidden (view full) --- 226/* Security Processing bit Indication */ 227#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000 228#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000 229#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000 230#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000 231#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000 232 233/* Receive Address Initial CRC Calculation */ | 215/* 216 * Additional interrupts need to be handled for ICH family: 217 * DSW = The FW changed the status of the DISSW bit in FWSM 218 * PHYINT = The LAN connected device generates an interrupt 219 * EPRST = Manageability reset event 220 */ 221#define IMS_ICH_ENABLE_MASK (\ 222 E1000_IMS_DSW | \ --- 8 unchanged lines hidden (view full) --- 231/* Security Processing bit Indication */ 232#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000 233#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000 234#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000 235#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000 236#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000 237 238/* Receive Address Initial CRC Calculation */ |
| 234#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) | 239#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) |
| 235 236void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 237 bool state); 238void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 239void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 240void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw); 241s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 242s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_config); 243s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 244void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 245s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 246#endif | 240 241void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 242 bool state); 243void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 244void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 245void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw); 246s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 247s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_config); 248s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 249void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 250s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 251#endif |