2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
| 2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
|
36#ifndef _E1000_ICH8LAN_H_
37#define _E1000_ICH8LAN_H_
38
39#define ICH_FLASH_GFPREG 0x0000
40#define ICH_FLASH_HSFSTS 0x0004
41#define ICH_FLASH_HSFCTL 0x0006
42#define ICH_FLASH_FADDR 0x0008
43#define ICH_FLASH_FDATA0 0x0010
44
45#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
46#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
47#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
48#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
49#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
50
51#define ICH_CYCLE_READ 0
52#define ICH_CYCLE_WRITE 2
53#define ICH_CYCLE_ERASE 3
54
55#define FLASH_GFPREG_BASE_MASK 0x1FFF
56#define FLASH_SECTOR_ADDR_SHIFT 12
57
58#define E1000_SHADOW_RAM_WORDS 2048
59
60#define ICH_FLASH_SEG_SIZE_256 256
61#define ICH_FLASH_SEG_SIZE_4K 4096
62#define ICH_FLASH_SEG_SIZE_8K 8192
63#define ICH_FLASH_SEG_SIZE_64K 65536
64#define ICH_FLASH_SECTOR_SIZE 4096
65
66#define ICH_FLASH_REG_MAPSIZE 0x00A0
67
68#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
69#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */
70/* FW established a valid mode */
71#define E1000_ICH_FWSM_FW_VALID 0x00008000
72
73#define E1000_ICH_MNG_IAMT_MODE 0x2
74
75#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
76 (ID_LED_DEF1_OFF2 << 8) | \
77 (ID_LED_DEF1_ON2 << 4) | \
78 (ID_LED_DEF1_DEF2))
79
80#define E1000_ICH_NVM_SIG_WORD 0x13
81#define E1000_ICH_NVM_SIG_MASK 0xC000
82
83#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
84
85#define E1000_FEXTNVM_SW_CONFIG 1
86#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
87
88#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
89
90#define E1000_ICH_RAR_ENTRIES 7
91
92#define PHY_PAGE_SHIFT 5
93#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
94 ((reg) & MAX_PHY_REG_ADDRESS))
95#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
96#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
97#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
98#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */
99
100#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
101#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
102#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
103#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020
104
105/*
106 * Additional interrupts need to be handled for ICH family:
107 * DSW = The FW changed the status of the DISSW bit in FWSM
108 * PHYINT = The LAN connected device generates an interrupt
109 * EPRST = Manageability reset event
110 */
111#define IMS_ICH_ENABLE_MASK (\
112 E1000_IMS_DSW | \
113 E1000_IMS_PHYINT | \
114 E1000_IMS_EPRST)
115
| 35#ifndef _E1000_ICH8LAN_H_
36#define _E1000_ICH8LAN_H_
37
38#define ICH_FLASH_GFPREG 0x0000
39#define ICH_FLASH_HSFSTS 0x0004
40#define ICH_FLASH_HSFCTL 0x0006
41#define ICH_FLASH_FADDR 0x0008
42#define ICH_FLASH_FDATA0 0x0010
43
44#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
45#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
46#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
47#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
48#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
49
50#define ICH_CYCLE_READ 0
51#define ICH_CYCLE_WRITE 2
52#define ICH_CYCLE_ERASE 3
53
54#define FLASH_GFPREG_BASE_MASK 0x1FFF
55#define FLASH_SECTOR_ADDR_SHIFT 12
56
57#define E1000_SHADOW_RAM_WORDS 2048
58
59#define ICH_FLASH_SEG_SIZE_256 256
60#define ICH_FLASH_SEG_SIZE_4K 4096
61#define ICH_FLASH_SEG_SIZE_8K 8192
62#define ICH_FLASH_SEG_SIZE_64K 65536
63#define ICH_FLASH_SECTOR_SIZE 4096
64
65#define ICH_FLASH_REG_MAPSIZE 0x00A0
66
67#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
68#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */
69/* FW established a valid mode */
70#define E1000_ICH_FWSM_FW_VALID 0x00008000
71
72#define E1000_ICH_MNG_IAMT_MODE 0x2
73
74#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
75 (ID_LED_DEF1_OFF2 << 8) | \
76 (ID_LED_DEF1_ON2 << 4) | \
77 (ID_LED_DEF1_DEF2))
78
79#define E1000_ICH_NVM_SIG_WORD 0x13
80#define E1000_ICH_NVM_SIG_MASK 0xC000
81
82#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
83
84#define E1000_FEXTNVM_SW_CONFIG 1
85#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
86
87#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
88
89#define E1000_ICH_RAR_ENTRIES 7
90
91#define PHY_PAGE_SHIFT 5
92#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
93 ((reg) & MAX_PHY_REG_ADDRESS))
94#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
95#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
96#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
97#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */
98
99#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
100#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
101#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
102#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020
103
104/*
105 * Additional interrupts need to be handled for ICH family:
106 * DSW = The FW changed the status of the DISSW bit in FWSM
107 * PHYINT = The LAN connected device generates an interrupt
108 * EPRST = Manageability reset event
109 */
110#define IMS_ICH_ENABLE_MASK (\
111 E1000_IMS_DSW | \
112 E1000_IMS_PHYINT | \
113 E1000_IMS_EPRST)
114
|