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e1000_ich8lan.c (195850) e1000_ich8lan.c (200243)
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 195850 2009-07-24 16:54:22Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 200243 2009-12-08 01:07:44Z jfv $*/
34
35/*
36 * 82562G 10/100 Network Connection
37 * 82562G-2 10/100 Network Connection
38 * 82562GT 10/100 Network Connection
39 * 82562GT-2 10/100 Network Connection
40 * 82562V 10/100 Network Connection
41 * 82562V-2 10/100 Network Connection

--- 21 unchanged lines hidden (view full) ---

63#include "e1000_api.h"
64
65static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
66static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw);
67static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
68static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
69static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
70static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
34
35/*
36 * 82562G 10/100 Network Connection
37 * 82562G-2 10/100 Network Connection
38 * 82562GT 10/100 Network Connection
39 * 82562GT-2 10/100 Network Connection
40 * 82562V 10/100 Network Connection
41 * 82562V-2 10/100 Network Connection

--- 21 unchanged lines hidden (view full) ---

63#include "e1000_api.h"
64
65static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
66static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw);
67static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
68static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
69static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
70static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
71static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
72static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
71static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
72static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
73static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
73static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
74static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
75static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
74static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
76static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
75static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
76 bool active);
77static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
78 bool active);
79static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
80 u16 words, u16 *data);
81static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
82 u16 words, u16 *data);

--- 7 unchanged lines hidden (view full) ---

90static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
91static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
92static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
93static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
94 u16 *speed, u16 *duplex);
95static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
96static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
97static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
77static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
78 bool active);
79static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
80 bool active);
81static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
82 u16 words, u16 *data);
83static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
84 u16 words, u16 *data);

--- 7 unchanged lines hidden (view full) ---

92static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
93static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
94static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
95static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
96 u16 *speed, u16 *duplex);
97static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
98static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
99static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
100static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
98static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
99static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
100static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
101static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
102static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
103static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
104static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
105static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
101static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
102static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
103static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
104static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
105static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
106static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
107static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
108static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
106static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
107static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
108static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
109static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
110 u32 offset, u8 *data);
111static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
112 u8 size, u16 *data);
113static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
114 u32 offset, u16 *data);
115static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
116 u32 offset, u8 byte);
117static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
118 u32 offset, u8 data);
119static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
120 u8 size, u16 data);
121static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
122static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
109static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
110static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
111static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
112 u32 offset, u8 *data);
113static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
114 u8 size, u16 *data);
115static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
116 u32 offset, u16 *data);
117static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
118 u32 offset, u8 byte);
119static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
120 u32 offset, u8 data);
121static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
122 u8 size, u16 data);
123static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
124static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
125static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
126static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
127static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
123
124/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
125/* Offset 04h HSFSTS */
126union ich8_hws_flash_status {
127 struct ich8_hsfsts {
128 u16 flcdone :1; /* bit 0 Flash Cycle Done */
129 u16 flcerr :1; /* bit 1 Flash Cycle Error */
130 u16 dael :1; /* bit 2 Direct Access error Log */

--- 43 unchanged lines hidden (view full) ---

174 s32 ret_val = E1000_SUCCESS;
175
176 DEBUGFUNC("e1000_init_phy_params_pchlan");
177
178 phy->addr = 1;
179 phy->reset_delay_us = 100;
180
181 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
128
129/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
130/* Offset 04h HSFSTS */
131union ich8_hws_flash_status {
132 struct ich8_hsfsts {
133 u16 flcdone :1; /* bit 0 Flash Cycle Done */
134 u16 flcerr :1; /* bit 1 Flash Cycle Error */
135 u16 dael :1; /* bit 2 Direct Access error Log */

--- 43 unchanged lines hidden (view full) ---

179 s32 ret_val = E1000_SUCCESS;
180
181 DEBUGFUNC("e1000_init_phy_params_pchlan");
182
183 phy->addr = 1;
184 phy->reset_delay_us = 100;
185
186 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
182 phy->ops.check_polarity = e1000_check_polarity_ife;
183 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
187 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
184 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
185 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
186 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
188 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
187 phy->ops.get_info = e1000_get_phy_info_ich8lan;
188 phy->ops.read_reg = e1000_read_phy_reg_hv;
189 phy->ops.read_reg = e1000_read_phy_reg_hv;
190 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
189 phy->ops.release = e1000_release_swflag_ich8lan;
190 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
191 phy->ops.release = e1000_release_swflag_ich8lan;
192 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
191 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
192 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
193 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
194 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
193 phy->ops.write_reg = e1000_write_phy_reg_hv;
195 phy->ops.write_reg = e1000_write_phy_reg_hv;
196 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
194 phy->ops.power_up = e1000_power_up_phy_copper;
195 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
196 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
197
198 phy->id = e1000_phy_unknown;
199 e1000_get_phy_id(hw);
200 phy->type = e1000_get_phy_type_from_id(phy->id);
201
197 phy->ops.power_up = e1000_power_up_phy_copper;
198 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
199 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
200
201 phy->id = e1000_phy_unknown;
202 e1000_get_phy_id(hw);
203 phy->type = e1000_get_phy_type_from_id(phy->id);
204
202 if (phy->type == e1000_phy_82577) {
205 switch (phy->type) {
206 case e1000_phy_82577:
203 phy->ops.check_polarity = e1000_check_polarity_82577;
204 phy->ops.force_speed_duplex =
205 e1000_phy_force_speed_duplex_82577;
207 phy->ops.check_polarity = e1000_check_polarity_82577;
208 phy->ops.force_speed_duplex =
209 e1000_phy_force_speed_duplex_82577;
206 phy->ops.get_cable_length = e1000_get_cable_length_82577;
210 phy->ops.get_cable_length = e1000_get_cable_length_82577;
207 phy->ops.get_info = e1000_get_phy_info_82577;
208 phy->ops.commit = e1000_phy_sw_reset_generic;
211 phy->ops.get_info = e1000_get_phy_info_82577;
212 phy->ops.commit = e1000_phy_sw_reset_generic;
213 case e1000_phy_82578:
214 phy->ops.check_polarity = e1000_check_polarity_m88;
215 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
216 phy->ops.get_cable_length = e1000_get_cable_length_m88;
217 phy->ops.get_info = e1000_get_phy_info_m88;
218 break;
219 default:
220 ret_val = -E1000_ERR_PHY;
221 break;
209 }
210
211 return ret_val;
212}
213
214/**
215 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
216 * @hw: pointer to the HW structure

--- 7 unchanged lines hidden (view full) ---

224 u16 i = 0;
225
226 DEBUGFUNC("e1000_init_phy_params_ich8lan");
227
228 phy->addr = 1;
229 phy->reset_delay_us = 100;
230
231 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
222 }
223
224 return ret_val;
225}
226
227/**
228 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
229 * @hw: pointer to the HW structure

--- 7 unchanged lines hidden (view full) ---

237 u16 i = 0;
238
239 DEBUGFUNC("e1000_init_phy_params_ich8lan");
240
241 phy->addr = 1;
242 phy->reset_delay_us = 100;
243
244 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
232 phy->ops.check_polarity = e1000_check_polarity_ife;
233 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
245 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
234 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
235 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
236 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
246 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
247 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
237 phy->ops.get_info = e1000_get_phy_info_ich8lan;
238 phy->ops.read_reg = e1000_read_phy_reg_igp;
239 phy->ops.release = e1000_release_swflag_ich8lan;
240 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
241 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
242 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
243 phy->ops.write_reg = e1000_write_phy_reg_igp;
244 phy->ops.power_up = e1000_power_up_phy_copper;
245 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;

--- 22 unchanged lines hidden (view full) ---

268 goto out;
269 }
270
271 /* Verify phy id */
272 switch (phy->id) {
273 case IGP03E1000_E_PHY_ID:
274 phy->type = e1000_phy_igp_3;
275 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
248 phy->ops.read_reg = e1000_read_phy_reg_igp;
249 phy->ops.release = e1000_release_swflag_ich8lan;
250 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
251 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
252 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
253 phy->ops.write_reg = e1000_write_phy_reg_igp;
254 phy->ops.power_up = e1000_power_up_phy_copper;
255 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;

--- 22 unchanged lines hidden (view full) ---

278 goto out;
279 }
280
281 /* Verify phy id */
282 switch (phy->id) {
283 case IGP03E1000_E_PHY_ID:
284 phy->type = e1000_phy_igp_3;
285 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
286 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
287 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
288 phy->ops.get_info = e1000_get_phy_info_igp;
289 phy->ops.check_polarity = e1000_check_polarity_igp;
290 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
276 break;
277 case IFE_E_PHY_ID:
278 case IFE_PLUS_E_PHY_ID:
279 case IFE_C_E_PHY_ID:
280 phy->type = e1000_phy_ife;
281 phy->autoneg_mask = E1000_ALL_NOT_GIG;
291 break;
292 case IFE_E_PHY_ID:
293 case IFE_PLUS_E_PHY_ID:
294 case IFE_C_E_PHY_ID:
295 phy->type = e1000_phy_ife;
296 phy->autoneg_mask = E1000_ALL_NOT_GIG;
297 phy->ops.get_info = e1000_get_phy_info_ife;
298 phy->ops.check_polarity = e1000_check_polarity_ife;
299 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
282 break;
283 case BME1000_E_PHY_ID:
284 phy->type = e1000_phy_bm;
285 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
286 phy->ops.read_reg = e1000_read_phy_reg_bm;
287 phy->ops.write_reg = e1000_write_phy_reg_bm;
288 phy->ops.commit = e1000_phy_sw_reset_generic;
300 break;
301 case BME1000_E_PHY_ID:
302 phy->type = e1000_phy_bm;
303 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
304 phy->ops.read_reg = e1000_read_phy_reg_bm;
305 phy->ops.write_reg = e1000_write_phy_reg_bm;
306 phy->ops.commit = e1000_phy_sw_reset_generic;
307 phy->ops.get_info = e1000_get_phy_info_m88;
308 phy->ops.check_polarity = e1000_check_polarity_m88;
309 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
289 break;
290 default:
291 ret_val = -E1000_ERR_PHY;
292 goto out;
293 }
294
295out:
296 return ret_val;

--- 51 unchanged lines hidden (view full) ---

348 nvm->word_size = E1000_SHADOW_RAM_WORDS;
349
350 /* Clear shadow ram */
351 for (i = 0; i < nvm->word_size; i++) {
352 dev_spec->shadow_ram[i].modified = FALSE;
353 dev_spec->shadow_ram[i].value = 0xFFFF;
354 }
355
310 break;
311 default:
312 ret_val = -E1000_ERR_PHY;
313 goto out;
314 }
315
316out:
317 return ret_val;

--- 51 unchanged lines hidden (view full) ---

369 nvm->word_size = E1000_SHADOW_RAM_WORDS;
370
371 /* Clear shadow ram */
372 for (i = 0; i < nvm->word_size; i++) {
373 dev_spec->shadow_ram[i].modified = FALSE;
374 dev_spec->shadow_ram[i].value = 0xFFFF;
375 }
376
377 E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
378 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
379
356 /* Function Pointers */
380 /* Function Pointers */
357 nvm->ops.acquire = e1000_acquire_swflag_ich8lan;
381 nvm->ops.acquire = e1000_acquire_nvm_ich8lan;
382 nvm->ops.release = e1000_release_nvm_ich8lan;
358 nvm->ops.read = e1000_read_nvm_ich8lan;
383 nvm->ops.read = e1000_read_nvm_ich8lan;
359 nvm->ops.release = e1000_release_swflag_ich8lan;
360 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
361 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
362 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
363 nvm->ops.write = e1000_write_nvm_ich8lan;
364
365out:
366 return ret_val;
367}

--- 20 unchanged lines hidden (view full) ---

388 /* Set rar entry count */
389 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
390 if (mac->type == e1000_ich8lan)
391 mac->rar_entry_count--;
392 /* Set if part includes ASF firmware */
393 mac->asf_firmware_present = TRUE;
394 /* Set if manageability features are enabled. */
395 mac->arc_subsystem_valid = TRUE;
384 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
385 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
386 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
387 nvm->ops.write = e1000_write_nvm_ich8lan;
388
389out:
390 return ret_val;
391}

--- 20 unchanged lines hidden (view full) ---

412 /* Set rar entry count */
413 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
414 if (mac->type == e1000_ich8lan)
415 mac->rar_entry_count--;
416 /* Set if part includes ASF firmware */
417 mac->asf_firmware_present = TRUE;
418 /* Set if manageability features are enabled. */
419 mac->arc_subsystem_valid = TRUE;
420 /* Adaptive IFS supported */
421 mac->adaptive_ifs = TRUE;
396
397 /* Function pointers */
398
399 /* bus type/speed/width */
400 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
401 /* function id */
402 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
403 /* reset */
404 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
405 /* hw initialization */
406 mac->ops.init_hw = e1000_init_hw_ich8lan;
407 /* link setup */
408 mac->ops.setup_link = e1000_setup_link_ich8lan;
409 /* physical interface setup */
410 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
411 /* check for link */
422
423 /* Function pointers */
424
425 /* bus type/speed/width */
426 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
427 /* function id */
428 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
429 /* reset */
430 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
431 /* hw initialization */
432 mac->ops.init_hw = e1000_init_hw_ich8lan;
433 /* link setup */
434 mac->ops.setup_link = e1000_setup_link_ich8lan;
435 /* physical interface setup */
436 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
437 /* check for link */
412 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
438 mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
413 /* check management mode */
414 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
415 /* link info */
416 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
417 /* multicast address update */
418 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
419 /* setting MTA */
420 mac->ops.mta_set = e1000_mta_set_generic;

--- 34 unchanged lines hidden (view full) ---

455 default:
456 break;
457 }
458
459 /* Enable PCS Lock-loss workaround for ICH8 */
460 if (mac->type == e1000_ich8lan)
461 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
462
439 /* check management mode */
440 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
441 /* link info */
442 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
443 /* multicast address update */
444 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
445 /* setting MTA */
446 mac->ops.mta_set = e1000_mta_set_generic;

--- 34 unchanged lines hidden (view full) ---

481 default:
482 break;
483 }
484
485 /* Enable PCS Lock-loss workaround for ICH8 */
486 if (mac->type == e1000_ich8lan)
487 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
488
463
464 return E1000_SUCCESS;
465}
466
467/**
489 return E1000_SUCCESS;
490}
491
492/**
493 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
494 * @hw: pointer to the HW structure
495 *
496 * Checks to see of the link status of the hardware has changed. If a
497 * change in link status has been detected, then we read the PHY registers
498 * to get the current speed/duplex if link exists.
499 **/
500static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
501{
502 struct e1000_mac_info *mac = &hw->mac;
503 s32 ret_val;
504 bool link;
505
506 DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
507
508 /*
509 * We only want to go out to the PHY registers to see if Auto-Neg
510 * has completed and/or if our link status has changed. The
511 * get_link_status flag is set upon receiving a Link Status
512 * Change or Rx Sequence Error interrupt.
513 */
514 if (!mac->get_link_status) {
515 ret_val = E1000_SUCCESS;
516 goto out;
517 }
518
519 /*
520 * First we want to see if the MII Status Register reports
521 * link. If so, then we want to get the current speed/duplex
522 * of the PHY.
523 */
524 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
525 if (ret_val)
526 goto out;
527
528 if (hw->mac.type == e1000_pchlan) {
529 ret_val = e1000_k1_gig_workaround_hv(hw, link);
530 if (ret_val)
531 goto out;
532 }
533
534 if (!link)
535 goto out; /* No link detected */
536
537 mac->get_link_status = FALSE;
538
539 if (hw->phy.type == e1000_phy_82578) {
540 ret_val = e1000_link_stall_workaround_hv(hw);
541 if (ret_val)
542 goto out;
543 }
544
545 /*
546 * Check if there was DownShift, must be checked
547 * immediately after link-up
548 */
549 e1000_check_downshift_generic(hw);
550
551 /*
552 * If we are forcing speed/duplex, then we simply return since
553 * we have already determined whether we have link or not.
554 */
555 if (!mac->autoneg) {
556 ret_val = -E1000_ERR_CONFIG;
557 goto out;
558 }
559
560 /*
561 * Auto-Neg is enabled. Auto Speed Detection takes care
562 * of MAC speed/duplex configuration. So we only need to
563 * configure Collision Distance in the MAC.
564 */
565 e1000_config_collision_dist_generic(hw);
566
567 /*
568 * Configure Flow Control now that Auto-Neg has completed.
569 * First, we need to restore the desired flow control
570 * settings because we may have had to re-autoneg with a
571 * different link partner.
572 */
573 ret_val = e1000_config_fc_after_link_up_generic(hw);
574 if (ret_val)
575 DEBUGOUT("Error configuring flow control\n");
576
577out:
578 return ret_val;
579}
580
581/**
468 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
469 * @hw: pointer to the HW structure
470 *
471 * Initialize family-specific function pointers for PHY, MAC, and NVM.
472 **/
473void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
474{
475 DEBUGFUNC("e1000_init_function_pointers_ich8lan");

--- 10 unchanged lines hidden (view full) ---

486 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
487 break;
488 default:
489 break;
490 }
491}
492
493/**
582 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
583 * @hw: pointer to the HW structure
584 *
585 * Initialize family-specific function pointers for PHY, MAC, and NVM.
586 **/
587void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
588{
589 DEBUGFUNC("e1000_init_function_pointers_ich8lan");

--- 10 unchanged lines hidden (view full) ---

600 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
601 break;
602 default:
603 break;
604 }
605}
606
607/**
608 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
609 * @hw: pointer to the HW structure
610 *
611 * Acquires the mutex for performing NVM operations.
612 **/
613static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
614{
615 DEBUGFUNC("e1000_acquire_nvm_ich8lan");
616
617 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
618
619 return E1000_SUCCESS;
620}
621
622/**
623 * e1000_release_nvm_ich8lan - Release NVM mutex
624 * @hw: pointer to the HW structure
625 *
626 * Releases the mutex used while performing NVM operations.
627 **/
628static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
629{
630 DEBUGFUNC("e1000_release_nvm_ich8lan");
631
632 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
633
634 return;
635}
636
637/**
494 * e1000_acquire_swflag_ich8lan - Acquire software control flag
495 * @hw: pointer to the HW structure
496 *
638 * e1000_acquire_swflag_ich8lan - Acquire software control flag
639 * @hw: pointer to the HW structure
640 *
497 * Acquires the software control flag for performing NVM and PHY
498 * operations. This is a function pointer entry point only called by
499 * read/write routines for the PHY and NVM parts.
641 * Acquires the software control flag for performing PHY and select
642 * MAC CSR accesses.
500 **/
501static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
502{
503 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
504 s32 ret_val = E1000_SUCCESS;
505
506 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
507
643 **/
644static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
645{
646 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
647 s32 ret_val = E1000_SUCCESS;
648
649 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
650
651 E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
652
508 while (timeout) {
509 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
653 while (timeout) {
654 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
655 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
656 break;
510
657
511 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) {
512 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
513 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
514
515 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
516 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
517 break;
518 }
519 msec_delay_irq(1);
520 timeout--;
521 }
522
523 if (!timeout) {
524 DEBUGOUT("SW/FW/HW has locked the resource for too long.\n");
658 msec_delay_irq(1);
659 timeout--;
660 }
661
662 if (!timeout) {
663 DEBUGOUT("SW/FW/HW has locked the resource for too long.\n");
664 ret_val = -E1000_ERR_CONFIG;
665 goto out;
666 }
667
668 timeout = SW_FLAG_TIMEOUT;
669
670 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
671 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
672
673 while (timeout) {
674 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
675 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
676 break;
677
678 msec_delay_irq(1);
679 timeout--;
680 }
681
682 if (!timeout) {
683 DEBUGOUT("Failed to acquire the semaphore.\n");
525 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
526 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
527 ret_val = -E1000_ERR_CONFIG;
528 goto out;
529 }
530
531out:
684 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
685 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
686 ret_val = -E1000_ERR_CONFIG;
687 goto out;
688 }
689
690out:
691 if (ret_val)
692 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
693
532 return ret_val;
533}
534
535/**
536 * e1000_release_swflag_ich8lan - Release software control flag
537 * @hw: pointer to the HW structure
538 *
694 return ret_val;
695}
696
697/**
698 * e1000_release_swflag_ich8lan - Release software control flag
699 * @hw: pointer to the HW structure
700 *
539 * Releases the software control flag for performing NVM and PHY operations.
540 * This is a function pointer entry point only called by read/write
541 * routines for the PHY and NVM parts.
701 * Releases the software control flag for performing PHY and select
702 * MAC CSR accesses.
542 **/
543static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
544{
545 u32 extcnf_ctrl;
546
547 DEBUGFUNC("e1000_release_swflag_ich8lan");
548
549 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
550 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
551 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
552
703 **/
704static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
705{
706 u32 extcnf_ctrl;
707
708 DEBUGFUNC("e1000_release_swflag_ich8lan");
709
710 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
711 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
712 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
713
714 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
715
553 return;
554}
555
556/**
557 * e1000_check_mng_mode_ich8lan - Checks management mode
558 * @hw: pointer to the HW structure
559 *
560 * This checks if the adapter has manageability enabled.

--- 28 unchanged lines hidden (view full) ---

589
590 fwsm = E1000_READ_REG(hw, E1000_FWSM);
591
592 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
593 : E1000_BLK_PHY_RESET;
594}
595
596/**
716 return;
717}
718
719/**
720 * e1000_check_mng_mode_ich8lan - Checks management mode
721 * @hw: pointer to the HW structure
722 *
723 * This checks if the adapter has manageability enabled.

--- 28 unchanged lines hidden (view full) ---

752
753 fwsm = E1000_READ_REG(hw, E1000_FWSM);
754
755 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
756 : E1000_BLK_PHY_RESET;
757}
758
759/**
760 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
761 * @hw: pointer to the HW structure
762 *
763 * SW should configure the LCD from the NVM extended configuration region
764 * as a workaround for certain parts.
765 **/
766static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
767{
768 struct e1000_phy_info *phy = &hw->phy;
769 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
770 s32 ret_val;
771 u16 word_addr, reg_data, reg_addr, phy_page = 0;
772
773 ret_val = hw->phy.ops.acquire(hw);
774 if (ret_val)
775 return ret_val;
776
777 /*
778 * Initialize the PHY from the NVM on ICH platforms. This
779 * is needed due to an issue where the NVM configuration is
780 * not properly autoloaded after power transitions.
781 * Therefore, after each PHY reset, we will load the
782 * configuration data out of the NVM manually.
783 */
784 if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) ||
785 (hw->mac.type == e1000_pchlan)) {
786 /* Check if SW needs to configure the PHY */
787 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
788 (hw->device_id == E1000_DEV_ID_ICH8_IGP_M) ||
789 (hw->mac.type == e1000_pchlan))
790 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
791 else
792 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
793
794 data = E1000_READ_REG(hw, E1000_FEXTNVM);
795 if (!(data & sw_cfg_mask))
796 goto out;
797
798 /* Wait for basic configuration completes before proceeding */
799 e1000_lan_init_done_ich8lan(hw);
800
801 /*
802 * Make sure HW does not configure LCD from PHY
803 * extended configuration before SW configuration
804 */
805 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
806 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
807 goto out;
808
809 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
810 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
811 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
812 if (!cnf_size)
813 goto out;
814
815 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
816 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
817
818 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
819 (hw->mac.type == e1000_pchlan)) {
820 /*
821 * HW configures the SMBus address and LEDs when the
822 * OEM and LCD Write Enable bits are set in the NVM.
823 * When both NVM bits are cleared, SW will configure
824 * them instead.
825 */
826 data = E1000_READ_REG(hw, E1000_STRAP);
827 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
828 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
829 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
830 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
831 reg_data);
832 if (ret_val)
833 goto out;
834
835 data = E1000_READ_REG(hw, E1000_LEDCTL);
836 ret_val = e1000_write_phy_reg_hv_locked(hw,
837 HV_LED_CONFIG,
838 (u16)data);
839 if (ret_val)
840 goto out;
841 }
842
843 /* Configure LCD from extended configuration region. */
844
845 /* cnf_base_addr is in DWORD */
846 word_addr = (u16)(cnf_base_addr << 1);
847
848 for (i = 0; i < cnf_size; i++) {
849 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
850 &reg_data);
851 if (ret_val)
852 goto out;
853
854 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
855 1, &reg_addr);
856 if (ret_val)
857 goto out;
858
859 /* Save off the PHY page for future writes. */
860 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
861 phy_page = reg_data;
862 continue;
863 }
864
865 reg_addr &= PHY_REG_MASK;
866 reg_addr |= phy_page;
867
868 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
869 reg_data);
870 if (ret_val)
871 goto out;
872 }
873 }
874
875out:
876 hw->phy.ops.release(hw);
877 return ret_val;
878}
879
880/**
881 * e1000_k1_gig_workaround_hv - K1 Si workaround
882 * @hw: pointer to the HW structure
883 * @link: link up bool flag
884 *
885 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
886 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
887 * If link is down, the function will restore the default K1 setting located
888 * in the NVM.
889 **/
890static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
891{
892 s32 ret_val = E1000_SUCCESS;
893 u16 status_reg = 0;
894 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
895
896 DEBUGFUNC("e1000_k1_gig_workaround_hv");
897
898 if (hw->mac.type != e1000_pchlan)
899 goto out;
900
901 /* Wrap the whole flow with the sw flag */
902 ret_val = hw->phy.ops.acquire(hw);
903 if (ret_val)
904 goto out;
905
906 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
907 if (link) {
908 if (hw->phy.type == e1000_phy_82578) {
909 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
910 &status_reg);
911 if (ret_val)
912 goto release;
913
914 status_reg &= BM_CS_STATUS_LINK_UP |
915 BM_CS_STATUS_RESOLVED |
916 BM_CS_STATUS_SPEED_MASK;
917
918 if (status_reg == (BM_CS_STATUS_LINK_UP |
919 BM_CS_STATUS_RESOLVED |
920 BM_CS_STATUS_SPEED_1000))
921 k1_enable = FALSE;
922 }
923
924 if (hw->phy.type == e1000_phy_82577) {
925 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
926 &status_reg);
927 if (ret_val)
928 goto release;
929
930 status_reg &= HV_M_STATUS_LINK_UP |
931 HV_M_STATUS_AUTONEG_COMPLETE |
932 HV_M_STATUS_SPEED_MASK;
933
934 if (status_reg == (HV_M_STATUS_LINK_UP |
935 HV_M_STATUS_AUTONEG_COMPLETE |
936 HV_M_STATUS_SPEED_1000))
937 k1_enable = FALSE;
938 }
939
940 /* Link stall fix for link up */
941 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
942 0x0100);
943 if (ret_val)
944 goto release;
945
946 } else {
947 /* Link stall fix for link down */
948 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
949 0x4100);
950 if (ret_val)
951 goto release;
952 }
953
954 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
955
956release:
957 hw->phy.ops.release(hw);
958out:
959 return ret_val;
960}
961
962/**
963 * e1000_configure_k1_ich8lan - Configure K1 power state
964 * @hw: pointer to the HW structure
965 * @enable: K1 state to configure
966 *
967 * Configure the K1 power state based on the provided parameter.
968 * Assumes semaphore already acquired.
969 *
970 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
971 **/
972s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
973{
974 s32 ret_val = E1000_SUCCESS;
975 u32 ctrl_reg = 0;
976 u32 ctrl_ext = 0;
977 u32 reg = 0;
978 u16 kmrn_reg = 0;
979
980 ret_val = e1000_read_kmrn_reg_locked(hw,
981 E1000_KMRNCTRLSTA_K1_CONFIG,
982 &kmrn_reg);
983 if (ret_val)
984 goto out;
985
986 if (k1_enable)
987 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
988 else
989 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
990
991 ret_val = e1000_write_kmrn_reg_locked(hw,
992 E1000_KMRNCTRLSTA_K1_CONFIG,
993 kmrn_reg);
994 if (ret_val)
995 goto out;
996
997 usec_delay(20);
998 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
999 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1000
1001 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1002 reg |= E1000_CTRL_FRCSPD;
1003 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1004
1005 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1006 usec_delay(20);
1007 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1008 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1009 usec_delay(20);
1010
1011out:
1012 return ret_val;
1013}
1014
1015/**
1016 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1017 * @hw: pointer to the HW structure
1018 * @d0_state: boolean if entering d0 or d3 device state
1019 *
1020 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1021 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1022 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1023 **/
1024s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1025{
1026 s32 ret_val = 0;
1027 u32 mac_reg;
1028 u16 oem_reg;
1029
1030 if (hw->mac.type != e1000_pchlan)
1031 return ret_val;
1032
1033 ret_val = hw->phy.ops.acquire(hw);
1034 if (ret_val)
1035 return ret_val;
1036
1037 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1038 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1039 goto out;
1040
1041 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
1042 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1043 goto out;
1044
1045 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
1046
1047 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1048 if (ret_val)
1049 goto out;
1050
1051 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1052
1053 if (d0_state) {
1054 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1055 oem_reg |= HV_OEM_BITS_GBE_DIS;
1056
1057 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1058 oem_reg |= HV_OEM_BITS_LPLU;
1059 } else {
1060 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1061 oem_reg |= HV_OEM_BITS_GBE_DIS;
1062
1063 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1064 oem_reg |= HV_OEM_BITS_LPLU;
1065 }
1066 /* Restart auto-neg to activate the bits */
1067 if (!hw->phy.ops.check_reset_block(hw))
1068 oem_reg |= HV_OEM_BITS_RESTART_AN;
1069 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1070
1071out:
1072 hw->phy.ops.release(hw);
1073
1074 return ret_val;
1075}
1076
1077
1078/**
597 * e1000_hv_phy_powerdown_workaround_ich8lan - Power down workaround on Sx
598 * @hw: pointer to the HW structure
599 **/
600s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
601{
602 if ((hw->phy.type != e1000_phy_82577) || (hw->revision_id > 2))
603 return E1000_SUCCESS;
604

--- 4 unchanged lines hidden (view full) ---

609 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
610 * done after every PHY reset.
611 **/
612static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
613{
614 s32 ret_val = E1000_SUCCESS;
615
616 if (hw->mac.type != e1000_pchlan)
1079 * e1000_hv_phy_powerdown_workaround_ich8lan - Power down workaround on Sx
1080 * @hw: pointer to the HW structure
1081 **/
1082s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
1083{
1084 if ((hw->phy.type != e1000_phy_82577) || (hw->revision_id > 2))
1085 return E1000_SUCCESS;
1086

--- 4 unchanged lines hidden (view full) ---

1091 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1092 * done after every PHY reset.
1093 **/
1094static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1095{
1096 s32 ret_val = E1000_SUCCESS;
1097
1098 if (hw->mac.type != e1000_pchlan)
617 return ret_val;
1099 goto out;
618
619 /* Hanksville M Phy init for IEEE. */
620 if ((hw->revision_id == 2) &&
621 (hw->phy.type == e1000_phy_82577) &&
622 ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
623 hw->phy.ops.write_reg(hw, 0x10, 0x8823);
624 hw->phy.ops.write_reg(hw, 0x11, 0x0018);
625 hw->phy.ops.write_reg(hw, 0x10, 0x8824);

--- 17 unchanged lines hidden (view full) ---

643 }
644
645 if (((hw->phy.type == e1000_phy_82577) &&
646 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
647 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
648 /* Disable generation of early preamble */
649 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
650 if (ret_val)
1100
1101 /* Hanksville M Phy init for IEEE. */
1102 if ((hw->revision_id == 2) &&
1103 (hw->phy.type == e1000_phy_82577) &&
1104 ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
1105 hw->phy.ops.write_reg(hw, 0x10, 0x8823);
1106 hw->phy.ops.write_reg(hw, 0x11, 0x0018);
1107 hw->phy.ops.write_reg(hw, 0x10, 0x8824);

--- 17 unchanged lines hidden (view full) ---

1125 }
1126
1127 if (((hw->phy.type == e1000_phy_82577) &&
1128 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1129 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1130 /* Disable generation of early preamble */
1131 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
1132 if (ret_val)
651 return ret_val;
1133 goto out;
652
653 /* Preamble tuning for SSC */
654 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204);
655 if (ret_val)
1134
1135 /* Preamble tuning for SSC */
1136 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204);
1137 if (ret_val)
656 return ret_val;
1138 goto out;
657 }
658
659 if (hw->phy.type == e1000_phy_82578) {
660 if (hw->revision_id < 3) {
661 /* PHY config */
662 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29,
663 0x66C0);
664 if (ret_val)
1139 }
1140
1141 if (hw->phy.type == e1000_phy_82578) {
1142 if (hw->revision_id < 3) {
1143 /* PHY config */
1144 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29,
1145 0x66C0);
1146 if (ret_val)
665 return ret_val;
1147 goto out;
666
667 /* PHY config */
668 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E,
669 0xFFFF);
670 if (ret_val)
1148
1149 /* PHY config */
1150 ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E,
1151 0xFFFF);
1152 if (ret_val)
671 return ret_val;
1153 goto out;
672 }
673
674 /*
675 * Return registers to default by doing a soft reset then
676 * writing 0x3140 to the control register.
677 */
678 if (hw->phy.revision < 2) {
679 e1000_phy_sw_reset_generic(hw);

--- 6 unchanged lines hidden (view full) ---

686 (hw->phy.type == e1000_phy_82577) &&
687 ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
688 /*
689 * Workaround for OEM (GbE) not operating after reset -
690 * restart AN (twice)
691 */
692 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
693 if (ret_val)
1154 }
1155
1156 /*
1157 * Return registers to default by doing a soft reset then
1158 * writing 0x3140 to the control register.
1159 */
1160 if (hw->phy.revision < 2) {
1161 e1000_phy_sw_reset_generic(hw);

--- 6 unchanged lines hidden (view full) ---

1168 (hw->phy.type == e1000_phy_82577) &&
1169 ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
1170 /*
1171 * Workaround for OEM (GbE) not operating after reset -
1172 * restart AN (twice)
1173 */
1174 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
1175 if (ret_val)
694 return ret_val;
1176 goto out;
695 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
696 if (ret_val)
1177 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
1178 if (ret_val)
697 return ret_val;
1179 goto out;
698 }
699
700 /* Select page 0 */
701 ret_val = hw->phy.ops.acquire(hw);
702 if (ret_val)
1180 }
1181
1182 /* Select page 0 */
1183 ret_val = hw->phy.ops.acquire(hw);
1184 if (ret_val)
703 return ret_val;
1185 goto out;
1186
704 hw->phy.addr = 1;
1187 hw->phy.addr = 1;
705 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1188 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1189 if (ret_val)
1190 goto out;
706 hw->phy.ops.release(hw);
707
1191 hw->phy.ops.release(hw);
1192
1193 /*
1194 * Configure the K1 Si workaround during phy reset assuming there is
1195 * link so that it disables K1 if link is in 1Gbps.
1196 */
1197 ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
1198
1199out:
708 return ret_val;
709}
710
711/**
712 * e1000_lan_init_done_ich8lan - Check for PHY config completion
713 * @hw: pointer to the HW structure
714 *
715 * Check the appropriate indication the MAC has finished configuring the

--- 31 unchanged lines hidden (view full) ---

747 * @hw: pointer to the HW structure
748 *
749 * Resets the PHY
750 * This is a function pointer entry point called by drivers
751 * or other shared routines.
752 **/
753static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
754{
1200 return ret_val;
1201}
1202
1203/**
1204 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1205 * @hw: pointer to the HW structure
1206 *
1207 * Check the appropriate indication the MAC has finished configuring the

--- 31 unchanged lines hidden (view full) ---

1239 * @hw: pointer to the HW structure
1240 *
1241 * Resets the PHY
1242 * This is a function pointer entry point called by drivers
1243 * or other shared routines.
1244 **/
1245static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1246{
755 struct e1000_phy_info *phy = &hw->phy;
756 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
757 s32 ret_val;
758 u16 word_addr, reg_data, reg_addr, phy_page = 0;
1247 s32 ret_val = E1000_SUCCESS;
1248 u16 reg;
759
760 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
761
762 ret_val = e1000_phy_hw_reset_generic(hw);
763 if (ret_val)
764 goto out;
765
766 /* Allow time for h/w to get to a quiescent state after reset */
767 msec_delay(10);
768
769 if (hw->mac.type == e1000_pchlan) {
770 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
771 if (ret_val)
772 goto out;
773 }
774
1249
1250 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
1251
1252 ret_val = e1000_phy_hw_reset_generic(hw);
1253 if (ret_val)
1254 goto out;
1255
1256 /* Allow time for h/w to get to a quiescent state after reset */
1257 msec_delay(10);
1258
1259 if (hw->mac.type == e1000_pchlan) {
1260 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1261 if (ret_val)
1262 goto out;
1263 }
1264
775 /*
776 * Initialize the PHY from the NVM on ICH platforms. This
777 * is needed due to an issue where the NVM configuration is
778 * not properly autoloaded after power transitions.
779 * Therefore, after each PHY reset, we will load the
780 * configuration data out of the NVM manually.
781 */
782 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
783 /* Check if SW needs configure the PHY */
784 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
785 (hw->device_id == E1000_DEV_ID_ICH8_IGP_M))
786 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
787 else
788 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1265 /* Dummy read to clear the phy wakeup bit after lcd reset */
1266 if (hw->mac.type == e1000_pchlan)
1267 hw->phy.ops.read_reg(hw, BM_WUC, &reg);
789
1268
790 data = E1000_READ_REG(hw, E1000_FEXTNVM);
791 if (!(data & sw_cfg_mask))
792 goto out;
1269 /* Configure the LCD with the extended configuration region in NVM */
1270 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1271 if (ret_val)
1272 goto out;
793
1273
794 /* Wait for basic configuration completes before proceeding */
795 e1000_lan_init_done_ich8lan(hw);
1274 /* Configure the LCD with the OEM bits in NVM */
1275 if (hw->mac.type == e1000_pchlan)
1276 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
796
1277
797 /*
798 * Make sure HW does not configure LCD from PHY
799 * extended configuration before SW configuration
800 */
801 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
802 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
803 goto out;
804
805 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
806 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
807 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
808 if (!cnf_size)
809 goto out;
810
811 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
812 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
813
814 /* Configure LCD from extended configuration region. */
815
816 /* cnf_base_addr is in DWORD */
817 word_addr = (u16)(cnf_base_addr << 1);
818
819 for (i = 0; i < cnf_size; i++) {
820 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
821 &reg_data);
822 if (ret_val)
823 goto out;
824
825 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
826 1, &reg_addr);
827 if (ret_val)
828 goto out;
829
830 /* Save off the PHY page for future writes. */
831 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
832 phy_page = reg_data;
833 continue;
834 }
835
836 reg_addr |= phy_page;
837
838 ret_val = phy->ops.write_reg(hw, (u32)reg_addr, reg_data);
839 if (ret_val)
840 goto out;
841 }
842 }
843
844out:
845 return ret_val;
846}
847
848/**
1278out:
1279 return ret_val;
1280}
1281
1282/**
849 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
1283 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
850 * @hw: pointer to the HW structure
1284 * @hw: pointer to the HW structure
1285 * @active: TRUE to enable LPLU, FALSE to disable
851 *
1286 *
852 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
1287 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1288 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1289 * the phy speed. This function will manually set the LPLU bit and restart
1290 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1291 * since it configures the same bit.
853 **/
1292 **/
854static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
1293static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
855{
1294{
856 s32 ret_val = -E1000_ERR_PHY_TYPE;
1295 s32 ret_val = E1000_SUCCESS;
1296 u16 oem_reg;
857
1297
858 DEBUGFUNC("e1000_get_phy_info_ich8lan");
1298 DEBUGFUNC("e1000_set_lplu_state_pchlan");
859
1299
860 switch (hw->phy.type) {
861 case e1000_phy_ife:
862 ret_val = e1000_get_phy_info_ife_ich8lan(hw);
863 break;
864 case e1000_phy_igp_3:
865 case e1000_phy_bm:
866 case e1000_phy_82578:
867 case e1000_phy_82577:
868 ret_val = e1000_get_phy_info_igp(hw);
869 break;
870 default:
871 break;
872 }
873
874 return ret_val;
875}
876
877/**
878 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
879 * @hw: pointer to the HW structure
880 *
881 * Populates "phy" structure with various feature states.
882 * This function is only called by other family-specific
883 * routines.
884 **/
885static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
886{
887 struct e1000_phy_info *phy = &hw->phy;
888 s32 ret_val;
889 u16 data;
890 bool link;
891
892 DEBUGFUNC("e1000_get_phy_info_ife_ich8lan");
893
894 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1300 ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
895 if (ret_val)
896 goto out;
897
1301 if (ret_val)
1302 goto out;
1303
898 if (!link) {
899 DEBUGOUT("Phy info is only valid if link is up\n");
900 ret_val = -E1000_ERR_CONFIG;
901 goto out;
902 }
1304 if (active)
1305 oem_reg |= HV_OEM_BITS_LPLU;
1306 else
1307 oem_reg &= ~HV_OEM_BITS_LPLU;
903
1308
904 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
905 if (ret_val)
906 goto out;
907 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
908 ? FALSE : TRUE;
1309 oem_reg |= HV_OEM_BITS_RESTART_AN;
1310 ret_val = hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
909
1311
910 if (phy->polarity_correction) {
911 ret_val = e1000_check_polarity_ife(hw);
912 if (ret_val)
913 goto out;
914 } else {
915 /* Polarity is forced */
916 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
917 ? e1000_rev_polarity_reversed
918 : e1000_rev_polarity_normal;
919 }
920
921 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
922 if (ret_val)
923 goto out;
924
925 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
926
927 /* The following parameters are undefined for 10/100 operation. */
928 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
929 phy->local_rx = e1000_1000t_rx_status_undefined;
930 phy->remote_rx = e1000_1000t_rx_status_undefined;
931
932out:
933 return ret_val;
934}
935
936/**
937 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
938 * @hw: pointer to the HW structure
939 * @active: TRUE to enable LPLU, FALSE to disable

--- 225 unchanged lines hidden (view full) ---

1165 *bank = 0;
1166
1167 /* Check bank 0 */
1168 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1169 &sig_byte);
1170 if (ret_val)
1171 goto out;
1172 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1312out:
1313 return ret_val;
1314}
1315
1316/**
1317 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1318 * @hw: pointer to the HW structure
1319 * @active: TRUE to enable LPLU, FALSE to disable

--- 225 unchanged lines hidden (view full) ---

1545 *bank = 0;
1546
1547 /* Check bank 0 */
1548 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1549 &sig_byte);
1550 if (ret_val)
1551 goto out;
1552 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1173 E1000_ICH_NVM_SIG_VALUE) {
1553 E1000_ICH_NVM_SIG_VALUE) {
1174 *bank = 0;
1175 goto out;
1176 }
1177
1178 /* Check bank 1 */
1179 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1180 bank1_offset,
1554 *bank = 0;
1555 goto out;
1556 }
1557
1558 /* Check bank 1 */
1559 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1560 bank1_offset,
1181 &sig_byte);
1561 &sig_byte);
1182 if (ret_val)
1183 goto out;
1184 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1562 if (ret_val)
1563 goto out;
1564 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1185 E1000_ICH_NVM_SIG_VALUE) {
1565 E1000_ICH_NVM_SIG_VALUE) {
1186 *bank = 1;
1187 goto out;
1188 }
1189
1190 DEBUGOUT("ERROR: No valid NVM bank present\n");
1191 ret_val = -E1000_ERR_NVM;
1192 break;
1193 }

--- 24 unchanged lines hidden (view full) ---

1218
1219 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1220 (words == 0)) {
1221 DEBUGOUT("nvm parameter(s) out of bounds\n");
1222 ret_val = -E1000_ERR_NVM;
1223 goto out;
1224 }
1225
1566 *bank = 1;
1567 goto out;
1568 }
1569
1570 DEBUGOUT("ERROR: No valid NVM bank present\n");
1571 ret_val = -E1000_ERR_NVM;
1572 break;
1573 }

--- 24 unchanged lines hidden (view full) ---

1598
1599 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1600 (words == 0)) {
1601 DEBUGOUT("nvm parameter(s) out of bounds\n");
1602 ret_val = -E1000_ERR_NVM;
1603 goto out;
1604 }
1605
1226 ret_val = nvm->ops.acquire(hw);
1227 if (ret_val)
1228 goto out;
1606 nvm->ops.acquire(hw);
1229
1230 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1607
1608 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1231 if (ret_val != E1000_SUCCESS)
1232 goto release;
1609 if (ret_val != E1000_SUCCESS) {
1610 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
1611 bank = 0;
1612 }
1233
1234 act_offset = (bank) ? nvm->flash_bank_size : 0;
1235 act_offset += offset;
1236
1613
1614 act_offset = (bank) ? nvm->flash_bank_size : 0;
1615 act_offset += offset;
1616
1617 ret_val = E1000_SUCCESS;
1237 for (i = 0; i < words; i++) {
1238 if ((dev_spec->shadow_ram) &&
1239 (dev_spec->shadow_ram[offset+i].modified)) {
1240 data[i] = dev_spec->shadow_ram[offset+i].value;
1241 } else {
1242 ret_val = e1000_read_flash_word_ich8lan(hw,
1243 act_offset + i,
1244 &word);
1245 if (ret_val)
1246 break;
1247 data[i] = word;
1248 }
1249 }
1250
1618 for (i = 0; i < words; i++) {
1619 if ((dev_spec->shadow_ram) &&
1620 (dev_spec->shadow_ram[offset+i].modified)) {
1621 data[i] = dev_spec->shadow_ram[offset+i].value;
1622 } else {
1623 ret_val = e1000_read_flash_word_ich8lan(hw,
1624 act_offset + i,
1625 &word);
1626 if (ret_val)
1627 break;
1628 data[i] = word;
1629 }
1630 }
1631
1251release:
1252 nvm->ops.release(hw);
1253
1254out:
1255 if (ret_val)
1256 DEBUGOUT1("NVM read error: %d\n", ret_val);
1257
1258 return ret_val;
1259}

--- 269 unchanged lines hidden (view full) ---

1529
1530 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1531 (words == 0)) {
1532 DEBUGOUT("nvm parameter(s) out of bounds\n");
1533 ret_val = -E1000_ERR_NVM;
1534 goto out;
1535 }
1536
1632 nvm->ops.release(hw);
1633
1634out:
1635 if (ret_val)
1636 DEBUGOUT1("NVM read error: %d\n", ret_val);
1637
1638 return ret_val;
1639}

--- 269 unchanged lines hidden (view full) ---

1909
1910 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1911 (words == 0)) {
1912 DEBUGOUT("nvm parameter(s) out of bounds\n");
1913 ret_val = -E1000_ERR_NVM;
1914 goto out;
1915 }
1916
1537 ret_val = nvm->ops.acquire(hw);
1538 if (ret_val)
1539 goto out;
1917 nvm->ops.acquire(hw);
1540
1541 for (i = 0; i < words; i++) {
1542 dev_spec->shadow_ram[offset+i].modified = TRUE;
1543 dev_spec->shadow_ram[offset+i].value = data[i];
1544 }
1545
1546 nvm->ops.release(hw);
1547

--- 24 unchanged lines hidden (view full) ---

1572
1573 ret_val = e1000_update_nvm_checksum_generic(hw);
1574 if (ret_val)
1575 goto out;
1576
1577 if (nvm->type != e1000_nvm_flash_sw)
1578 goto out;
1579
1918
1919 for (i = 0; i < words; i++) {
1920 dev_spec->shadow_ram[offset+i].modified = TRUE;
1921 dev_spec->shadow_ram[offset+i].value = data[i];
1922 }
1923
1924 nvm->ops.release(hw);
1925

--- 24 unchanged lines hidden (view full) ---

1950
1951 ret_val = e1000_update_nvm_checksum_generic(hw);
1952 if (ret_val)
1953 goto out;
1954
1955 if (nvm->type != e1000_nvm_flash_sw)
1956 goto out;
1957
1580 ret_val = nvm->ops.acquire(hw);
1581 if (ret_val)
1582 goto out;
1958 nvm->ops.acquire(hw);
1583
1584 /*
1585 * We're writing to the opposite bank so if we're on bank 1,
1586 * write to bank 0 etc. We also need to erase the segment that
1587 * is going to be written
1588 */
1589 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1590 if (ret_val != E1000_SUCCESS) {
1959
1960 /*
1961 * We're writing to the opposite bank so if we're on bank 1,
1962 * write to bank 0 etc. We also need to erase the segment that
1963 * is going to be written
1964 */
1965 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1966 if (ret_val != E1000_SUCCESS) {
1591 nvm->ops.release(hw);
1592 goto out;
1967 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
1968 bank = 0;
1593 }
1594
1595 if (bank == 0) {
1596 new_bank_offset = nvm->flash_bank_size;
1597 old_bank_offset = 0;
1598 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1599 if (ret_val) {
1600 nvm->ops.release(hw);

--- 72 unchanged lines hidden (view full) ---

1673 * and we need to change bit 14 to 0b
1674 */
1675 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1676 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1677 if (ret_val) {
1678 nvm->ops.release(hw);
1679 goto out;
1680 }
1969 }
1970
1971 if (bank == 0) {
1972 new_bank_offset = nvm->flash_bank_size;
1973 old_bank_offset = 0;
1974 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1975 if (ret_val) {
1976 nvm->ops.release(hw);

--- 72 unchanged lines hidden (view full) ---

2049 * and we need to change bit 14 to 0b
2050 */
2051 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2052 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2053 if (ret_val) {
2054 nvm->ops.release(hw);
2055 goto out;
2056 }
2057
1681 data &= 0xBFFF;
1682 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1683 act_offset * 2 + 1,
1684 (u8)(data >> 8));
1685 if (ret_val) {
1686 nvm->ops.release(hw);
1687 goto out;
1688 }

--- 135 unchanged lines hidden (view full) ---

1824
1825 /*
1826 * If we're here, then things are most likely
1827 * completely hosed, but if the error condition
1828 * is detected, it won't hurt to give it another
1829 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1830 */
1831 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
2058 data &= 0xBFFF;
2059 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2060 act_offset * 2 + 1,
2061 (u8)(data >> 8));
2062 if (ret_val) {
2063 nvm->ops.release(hw);
2064 goto out;
2065 }

--- 135 unchanged lines hidden (view full) ---

2201
2202 /*
2203 * If we're here, then things are most likely
2204 * completely hosed, but if the error condition
2205 * is detected, it won't hurt to give it another
2206 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2207 */
2208 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1832 if (hsfsts.hsf_status.flcerr == 1) {
2209 if (hsfsts.hsf_status.flcerr == 1)
1833 /* Repeat for some time before giving up. */
1834 continue;
2210 /* Repeat for some time before giving up. */
2211 continue;
1835 } else if (hsfsts.hsf_status.flcdone == 0) {
2212 if (hsfsts.hsf_status.flcdone == 0) {
1836 DEBUGOUT("Timeout error - flash cycle "
1837 "did not complete.");
1838 break;
1839 }
1840 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1841
1842out:
1843 return ret_val;

--- 111 unchanged lines hidden (view full) ---

1955 break;
1956 default:
1957 ret_val = -E1000_ERR_NVM;
1958 goto out;
1959 }
1960
1961 /* Start with the base address, then add the sector offset. */
1962 flash_linear_addr = hw->nvm.flash_base_addr;
2213 DEBUGOUT("Timeout error - flash cycle "
2214 "did not complete.");
2215 break;
2216 }
2217 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2218
2219out:
2220 return ret_val;

--- 111 unchanged lines hidden (view full) ---

2332 break;
2333 default:
2334 ret_val = -E1000_ERR_NVM;
2335 goto out;
2336 }
2337
2338 /* Start with the base address, then add the sector offset. */
2339 flash_linear_addr = hw->nvm.flash_base_addr;
1963 flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
2340 flash_linear_addr += (bank) ? flash_bank_size : 0;
1964
1965 for (j = 0; j < iteration ; j++) {
1966 do {
1967 /* Steps */
1968 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1969 if (ret_val)
1970 goto out;
1971

--- 176 unchanged lines hidden (view full) ---

2148 * e1000_reset_hw_ich8lan - Reset the hardware
2149 * @hw: pointer to the HW structure
2150 *
2151 * Does a full reset of the hardware which includes a reset of the PHY and
2152 * MAC.
2153 **/
2154static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2155{
2341
2342 for (j = 0; j < iteration ; j++) {
2343 do {
2344 /* Steps */
2345 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2346 if (ret_val)
2347 goto out;
2348

--- 176 unchanged lines hidden (view full) ---

2525 * e1000_reset_hw_ich8lan - Reset the hardware
2526 * @hw: pointer to the HW structure
2527 *
2528 * Does a full reset of the hardware which includes a reset of the PHY and
2529 * MAC.
2530 **/
2531static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2532{
2533 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2534 u16 reg;
2156 u32 ctrl, icr, kab;
2157 s32 ret_val;
2158
2159 DEBUGFUNC("e1000_reset_hw_ich8lan");
2160
2161 /*
2162 * Prevent the PCI-E bus from sticking if there is no TLP connection
2163 * on the last TLP read/write transaction when MAC is reset.

--- 19 unchanged lines hidden (view full) ---

2183 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2184 if (hw->mac.type == e1000_ich8lan) {
2185 /* Set Tx and Rx buffer allocation to 8k apiece. */
2186 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
2187 /* Set Packet Buffer Size to 16k. */
2188 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
2189 }
2190
2535 u32 ctrl, icr, kab;
2536 s32 ret_val;
2537
2538 DEBUGFUNC("e1000_reset_hw_ich8lan");
2539
2540 /*
2541 * Prevent the PCI-E bus from sticking if there is no TLP connection
2542 * on the last TLP read/write transaction when MAC is reset.

--- 19 unchanged lines hidden (view full) ---

2562 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2563 if (hw->mac.type == e1000_ich8lan) {
2564 /* Set Tx and Rx buffer allocation to 8k apiece. */
2565 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
2566 /* Set Packet Buffer Size to 16k. */
2567 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
2568 }
2569
2570 if (hw->mac.type == e1000_pchlan) {
2571 /* Save the NVM K1 bit setting*/
2572 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2573 if (ret_val)
2574 return ret_val;
2575
2576 if (reg & E1000_NVM_K1_ENABLE)
2577 dev_spec->nvm_k1_enabled = TRUE;
2578 else
2579 dev_spec->nvm_k1_enabled = FALSE;
2580 }
2581
2191 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2192
2193 if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) {
2194 /* Clear PHY Reset Asserted bit */
2195 if (hw->mac.type >= e1000_pchlan) {
2196 u32 status = E1000_READ_REG(hw, E1000_STATUS);
2197 E1000_WRITE_REG(hw, E1000_STATUS, status &
2198 ~E1000_STATUS_PHYRA);

--- 25 unchanged lines hidden (view full) ---

2224 /*
2225 * When auto config read does not complete, do not
2226 * return with an error. This can happen in situations
2227 * where there is no eeprom and prevents getting link.
2228 */
2229 DEBUGOUT("Auto Read Done did not complete\n");
2230 }
2231 }
2582 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2583
2584 if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) {
2585 /* Clear PHY Reset Asserted bit */
2586 if (hw->mac.type >= e1000_pchlan) {
2587 u32 status = E1000_READ_REG(hw, E1000_STATUS);
2588 E1000_WRITE_REG(hw, E1000_STATUS, status &
2589 ~E1000_STATUS_PHYRA);

--- 25 unchanged lines hidden (view full) ---

2615 /*
2616 * When auto config read does not complete, do not
2617 * return with an error. This can happen in situations
2618 * where there is no eeprom and prevents getting link.
2619 */
2620 DEBUGOUT("Auto Read Done did not complete\n");
2621 }
2622 }
2623 /* Dummy read to clear the phy wakeup bit after lcd reset */
2624 if (hw->mac.type == e1000_pchlan)
2625 hw->phy.ops.read_reg(hw, BM_WUC, &reg);
2232
2626
2627 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2628 if (ret_val)
2629 goto out;
2630
2631 if (hw->mac.type == e1000_pchlan) {
2632 ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
2633 if (ret_val)
2634 goto out;
2635 }
2636 /*
2637 * For PCH, this write will make sure that any noise
2638 * will be detected as a CRC error and be dropped rather than show up
2639 * as a bad packet to the DMA engine.
2640 */
2641 if (hw->mac.type == e1000_pchlan)
2642 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
2643
2233 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2234 icr = E1000_READ_REG(hw, E1000_ICR);
2235
2236 kab = E1000_READ_REG(hw, E1000_KABGTXD);
2237 kab |= E1000_KABGTXD_BGSQLBIAS;
2238 E1000_WRITE_REG(hw, E1000_KABGTXD, kab);
2239
2240 if (hw->mac.type == e1000_pchlan)
2241 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2242
2644 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2645 icr = E1000_READ_REG(hw, E1000_ICR);
2646
2647 kab = E1000_READ_REG(hw, E1000_KABGTXD);
2648 kab |= E1000_KABGTXD_BGSQLBIAS;
2649 E1000_WRITE_REG(hw, E1000_KABGTXD, kab);
2650
2651 if (hw->mac.type == e1000_pchlan)
2652 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2653
2654out:
2243 return ret_val;
2244}
2245
2246/**
2247 * e1000_init_hw_ich8lan - Initialize the hardware
2248 * @hw: pointer to the HW structure
2249 *
2250 * Prepares the hardware for transmit and receive by doing the following:

--- 13 unchanged lines hidden (view full) ---

2264
2265 DEBUGFUNC("e1000_init_hw_ich8lan");
2266
2267 e1000_initialize_hw_bits_ich8lan(hw);
2268
2269 /* Initialize identification LED */
2270 ret_val = mac->ops.id_led_init(hw);
2271 if (ret_val)
2655 return ret_val;
2656}
2657
2658/**
2659 * e1000_init_hw_ich8lan - Initialize the hardware
2660 * @hw: pointer to the HW structure
2661 *
2662 * Prepares the hardware for transmit and receive by doing the following:

--- 13 unchanged lines hidden (view full) ---

2676
2677 DEBUGFUNC("e1000_init_hw_ich8lan");
2678
2679 e1000_initialize_hw_bits_ich8lan(hw);
2680
2681 /* Initialize identification LED */
2682 ret_val = mac->ops.id_led_init(hw);
2683 if (ret_val)
2272 /* This is not fatal and we should not stop init due to this */
2273 DEBUGOUT("Error initializing identification LED\n");
2684 DEBUGOUT("Error initializing identification LED\n");
2685 /* This is not fatal and we should not stop init due to this */
2274
2275 /* Setup the receive address. */
2276 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
2277
2278 /* Zero out the Multicast HASH table */
2279 DEBUGOUT("Zeroing the MTA\n");
2280 for (i = 0; i < mac->mta_reg_count; i++)
2281 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);

--- 29 unchanged lines hidden (view full) ---

2311
2312 /*
2313 * ICH8 has opposite polarity of no_snoop bits.
2314 * By default, we should use snoop behavior.
2315 */
2316 if (mac->type == e1000_ich8lan)
2317 snoop = PCIE_ICH8_SNOOP_ALL;
2318 else
2686
2687 /* Setup the receive address. */
2688 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
2689
2690 /* Zero out the Multicast HASH table */
2691 DEBUGOUT("Zeroing the MTA\n");
2692 for (i = 0; i < mac->mta_reg_count; i++)
2693 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);

--- 29 unchanged lines hidden (view full) ---

2723
2724 /*
2725 * ICH8 has opposite polarity of no_snoop bits.
2726 * By default, we should use snoop behavior.
2727 */
2728 if (mac->type == e1000_ich8lan)
2729 snoop = PCIE_ICH8_SNOOP_ALL;
2730 else
2319 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
2731 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2320 e1000_set_pcie_no_snoop_generic(hw, snoop);
2321
2322 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2323 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2324 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2325
2326 /*
2327 * Clear all of the statistics registers (clear on read). It is

--- 140 unchanged lines hidden (view full) ---

2468 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2469 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2470
2471 /*
2472 * Set the mac to wait the maximum time between each iteration
2473 * and increase the max iterations when polling the phy;
2474 * this fixes erroneous timeouts at 10Mbps.
2475 */
2732 e1000_set_pcie_no_snoop_generic(hw, snoop);
2733
2734 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2735 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2736 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2737
2738 /*
2739 * Clear all of the statistics registers (clear on read). It is

--- 140 unchanged lines hidden (view full) ---

2880 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2881 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2882
2883 /*
2884 * Set the mac to wait the maximum time between each iteration
2885 * and increase the max iterations when polling the phy;
2886 * this fixes erroneous timeouts at 10Mbps.
2887 */
2476 ret_val = e1000_write_kmrn_reg_generic(hw,
2477 E1000_KMRNCTRLSTA_TIMEOUTS,
2888 ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
2478 0xFFFF);
2479 if (ret_val)
2480 goto out;
2481 ret_val = e1000_read_kmrn_reg_generic(hw,
2482 E1000_KMRNCTRLSTA_INBAND_PARAM,
2483 &reg_data);
2484 if (ret_val)
2485 goto out;

--- 297 unchanged lines hidden (view full) ---

2783 *
2784 * Should only be called for applicable parts.
2785 **/
2786void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2787{
2788 u32 phy_ctrl;
2789
2790 switch (hw->mac.type) {
2889 0xFFFF);
2890 if (ret_val)
2891 goto out;
2892 ret_val = e1000_read_kmrn_reg_generic(hw,
2893 E1000_KMRNCTRLSTA_INBAND_PARAM,
2894 &reg_data);
2895 if (ret_val)
2896 goto out;

--- 297 unchanged lines hidden (view full) ---

3194 *
3195 * Should only be called for applicable parts.
3196 **/
3197void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3198{
3199 u32 phy_ctrl;
3200
3201 switch (hw->mac.type) {
3202 case e1000_ich8lan:
2791 case e1000_ich9lan:
2792 case e1000_ich10lan:
2793 case e1000_pchlan:
2794 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2795 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2796 E1000_PHY_CTRL_GBE_DISABLE;
2797 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2798
3203 case e1000_ich9lan:
3204 case e1000_ich10lan:
3205 case e1000_pchlan:
3206 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3207 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3208 E1000_PHY_CTRL_GBE_DISABLE;
3209 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3210
2799 /* Workaround SWFLAG unexpectedly set during S0->Sx */
2800 if (hw->mac.type == e1000_pchlan)
3211 if (hw->mac.type == e1000_pchlan)
2801 usec_delay(500);
3212 e1000_phy_hw_reset_ich8lan(hw);
2802 default:
2803 break;
2804 }
2805
2806 return;
2807}
2808
2809/**

--- 167 unchanged lines hidden (view full) ---

2977static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2978{
2979 s32 ret_val = E1000_SUCCESS;
2980 u32 bank = 0;
2981
2982 if (hw->mac.type >= e1000_pchlan) {
2983 u32 status = E1000_READ_REG(hw, E1000_STATUS);
2984
3213 default:
3214 break;
3215 }
3216
3217 return;
3218}
3219
3220/**

--- 167 unchanged lines hidden (view full) ---

3388static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3389{
3390 s32 ret_val = E1000_SUCCESS;
3391 u32 bank = 0;
3392
3393 if (hw->mac.type >= e1000_pchlan) {
3394 u32 status = E1000_READ_REG(hw, E1000_STATUS);
3395
2985 if (status & E1000_STATUS_PHYRA) {
3396 if (status & E1000_STATUS_PHYRA)
2986 E1000_WRITE_REG(hw, E1000_STATUS, status &
2987 ~E1000_STATUS_PHYRA);
3397 E1000_WRITE_REG(hw, E1000_STATUS, status &
3398 ~E1000_STATUS_PHYRA);
2988 } else
3399 else
2989 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
2990 }
2991
2992 e1000_get_cfg_done_generic(hw);
2993
2994 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3400 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
3401 }
3402
3403 e1000_get_cfg_done_generic(hw);
3404
3405 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2995 if ((hw->mac.type != e1000_ich10lan) &&
2996 (hw->mac.type != e1000_pchlan)) {
3406 if (hw->mac.type <= e1000_ich9lan) {
2997 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
2998 (hw->phy.type == e1000_phy_igp_3)) {
2999 e1000_phy_init_script_igp3(hw);
3000 }
3001 } else {
3002 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3003 /* Maybe we should do a basic PHY config */
3004 DEBUGOUT("EEPROM not present\n");

--- 73 unchanged lines hidden --- 		3407 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
3408 (hw->phy.type == e1000_phy_igp_3)) {
3409 e1000_phy_init_script_igp3(hw);
3410 }
3411 } else {
3412 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3413 /* Maybe we should do a basic PHY config */
3414 DEBUGOUT("EEPROM not present\n");

--- 73 unchanged lines hidden ---