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e1000_ich8lan.c (176667) e1000_ich8lan.c (177867)
1/*******************************************************************************
1/******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,

--- 14 unchanged lines hidden (view full) ---

24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,

--- 14 unchanged lines hidden (view full) ---

24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33/* $FreeBSD: head/sys/dev/em/e1000_ich8lan.c 176667 2008-02-29 21:50:11Z jfv $ */
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/em/e1000_ich8lan.c 177867 2008-04-02 22:00:36Z jfv $*/
34
34
35
36/* e1000_ich8lan
37 * e1000_ich9lan
38 */
39
40#include "e1000_api.h"
41#include "e1000_ich8lan.h"
42
35/* e1000_ich8lan
36 * e1000_ich9lan
37 */
38
39#include "e1000_api.h"
40#include "e1000_ich8lan.h"
41
43STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
44STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
45STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
46STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
47STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
48STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
49STATIC s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
50STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
51STATIC s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw);
52STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
53STATIC s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
54STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
42static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
43static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
44static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
45static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
46static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
47static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
48static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
49static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
50static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw);
51static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
52static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
53static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
55 bool active);
54 bool active);
56STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
55static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
57 bool active);
56 bool active);
58STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
57static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
59 u16 words, u16 *data);
58 u16 words, u16 *data);
60STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
59static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
61 u16 words, u16 *data);
60 u16 words, u16 *data);
62STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
63STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
64STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
61static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
62static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
63static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
65 u16 *data);
64 u16 *data);
66STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
67STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
68STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
69STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
70STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
71STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
65static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
66static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
67static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
68static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
69static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
70static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
72 u16 *speed, u16 *duplex);
71 u16 *speed, u16 *duplex);
73STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
74STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
75STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
76STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
77STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
72static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
73static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
74static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
75static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
76static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
78static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
79static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
80static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
81static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
82static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
77static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
78static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
79static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
80static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
81static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
83STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
84 u32 offset, u8* data);
85static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
86 u8 size, u16* data);
82static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
83 u8 size, u16* data);
87STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
84static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
88 u32 offset, u16 *data);
89static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
90 u32 offset, u8 byte);
85 u32 offset, u16 *data);
86static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
87 u32 offset, u8 byte);
91STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
88static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
92 u32 offset, u8 data);
93static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
94 u8 size, u16 data);
89 u32 offset, u8 data);
90static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
91 u8 size, u16 data);
95STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
96STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
92static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
93static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
97
98/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
99/* Offset 04h HSFSTS */
100union ich8_hws_flash_status {
101 struct ich8_hsfsts {
102 u16 flcdone :1; /* bit 0 Flash Cycle Done */
103 u16 flcerr :1; /* bit 1 Flash Cycle Error */
104 u16 dael :1; /* bit 2 Direct Access error Log */

--- 42 unchanged lines hidden (view full) ---

147};
148
149/**
150 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
151 * @hw: pointer to the HW structure
152 *
153 * Initialize family-specific PHY parameters and function pointers.
154 **/
94
95/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
96/* Offset 04h HSFSTS */
97union ich8_hws_flash_status {
98 struct ich8_hsfsts {
99 u16 flcdone :1; /* bit 0 Flash Cycle Done */
100 u16 flcerr :1; /* bit 1 Flash Cycle Error */
101 u16 dael :1; /* bit 2 Direct Access error Log */

--- 42 unchanged lines hidden (view full) ---

144};
145
146/**
147 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
148 * @hw: pointer to the HW structure
149 *
150 * Initialize family-specific PHY parameters and function pointers.
151 **/
155STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
152static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
156{
157 struct e1000_phy_info *phy = &hw->phy;
153{
154 struct e1000_phy_info *phy = &hw->phy;
158 struct e1000_functions *func = &hw->func;
159 s32 ret_val = E1000_SUCCESS;
160 u16 i = 0;
161
162 DEBUGFUNC("e1000_init_phy_params_ich8lan");
163
155 s32 ret_val = E1000_SUCCESS;
156 u16 i = 0;
157
158 DEBUGFUNC("e1000_init_phy_params_ich8lan");
159
164 phy->addr = 1;
165 phy->reset_delay_us = 100;
160 phy->addr = 1;
161 phy->reset_delay_us = 100;
166
162
167 func->acquire_phy = e1000_acquire_swflag_ich8lan;
168 func->check_polarity = e1000_check_polarity_ife_ich8lan;
169 func->check_reset_block = e1000_check_reset_block_ich8lan;
170 func->force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan;
171 func->get_cable_length = e1000_get_cable_length_igp_2;
172 func->get_cfg_done = e1000_get_cfg_done_ich8lan;
173 func->get_phy_info = e1000_get_phy_info_ich8lan;
174 func->read_phy_reg = e1000_read_phy_reg_igp;
175 func->release_phy = e1000_release_swflag_ich8lan;
176 func->reset_phy = e1000_phy_hw_reset_ich8lan;
177 func->set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
178 func->set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
179 func->write_phy_reg = e1000_write_phy_reg_igp;
180 func->power_up_phy = e1000_power_up_phy_copper;
181 func->power_down_phy = e1000_power_down_phy_copper_ich8lan;
163 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
164 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
165 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
166 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan;
167 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
168 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
169 phy->ops.get_info = e1000_get_phy_info_ich8lan;
170 phy->ops.read_reg = e1000_read_phy_reg_igp;
171 phy->ops.release = e1000_release_swflag_ich8lan;
172 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
173 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
174 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
175 phy->ops.write_reg = e1000_write_phy_reg_igp;
176 phy->ops.power_up = e1000_power_up_phy_copper;
177 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
182
183 /*
184 * We may need to do this twice - once for IGP and if that fails,
185 * we'll set BM func pointers and try again
186 */
187 ret_val = e1000_determine_phy_address(hw);
188 if (ret_val) {
178
179 /*
180 * We may need to do this twice - once for IGP and if that fails,
181 * we'll set BM func pointers and try again
182 */
183 ret_val = e1000_determine_phy_address(hw);
184 if (ret_val) {
189 func->write_phy_reg = e1000_write_phy_reg_bm;
190 func->read_phy_reg = e1000_read_phy_reg_bm;
185 phy->ops.write_reg = e1000_write_phy_reg_bm;
186 phy->ops.read_reg = e1000_read_phy_reg_bm;
191 ret_val = e1000_determine_phy_address(hw);
192 if (ret_val) {
193 DEBUGOUT("Cannot determine PHY address. Erroring out\n");
194 goto out;
195 }
196 }
197
198 phy->id = 0;

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214 case IFE_PLUS_E_PHY_ID:
215 case IFE_C_E_PHY_ID:
216 phy->type = e1000_phy_ife;
217 phy->autoneg_mask = E1000_ALL_NOT_GIG;
218 break;
219 case BME1000_E_PHY_ID:
220 phy->type = e1000_phy_bm;
221 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
187 ret_val = e1000_determine_phy_address(hw);
188 if (ret_val) {
189 DEBUGOUT("Cannot determine PHY address. Erroring out\n");
190 goto out;
191 }
192 }
193
194 phy->id = 0;

--- 15 unchanged lines hidden (view full) ---

210 case IFE_PLUS_E_PHY_ID:
211 case IFE_C_E_PHY_ID:
212 phy->type = e1000_phy_ife;
213 phy->autoneg_mask = E1000_ALL_NOT_GIG;
214 break;
215 case BME1000_E_PHY_ID:
216 phy->type = e1000_phy_bm;
217 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
222 func->read_phy_reg = e1000_read_phy_reg_bm;
223 func->write_phy_reg = e1000_write_phy_reg_bm;
224 func->commit_phy = e1000_phy_sw_reset_generic;
218 phy->ops.read_reg = e1000_read_phy_reg_bm;
219 phy->ops.write_reg = e1000_write_phy_reg_bm;
220 phy->ops.commit = e1000_phy_sw_reset_generic;
225 break;
226 default:
227 ret_val = -E1000_ERR_PHY;
228 goto out;
229 }
230
231out:
232 return ret_val;
233}
234
235/**
236 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
237 * @hw: pointer to the HW structure
238 *
239 * Initialize family-specific NVM parameters and function
240 * pointers.
241 **/
221 break;
222 default:
223 ret_val = -E1000_ERR_PHY;
224 goto out;
225 }
226
227out:
228 return ret_val;
229}
230
231/**
232 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
233 * @hw: pointer to the HW structure
234 *
235 * Initialize family-specific NVM parameters and function
236 * pointers.
237 **/
242STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
238static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
243{
244 struct e1000_nvm_info *nvm = &hw->nvm;
239{
240 struct e1000_nvm_info *nvm = &hw->nvm;
245 struct e1000_functions *func = &hw->func;
246 struct e1000_dev_spec_ich8lan *dev_spec;
247 u32 gfpreg, sector_base_addr, sector_end_addr;
248 s32 ret_val = E1000_SUCCESS;
249 u16 i;
250
251 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
252
253 /* Can't read flash registers if the register set isn't mapped. */

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294
295 /* Clear shadow ram */
296 for (i = 0; i < nvm->word_size; i++) {
297 dev_spec->shadow_ram[i].modified = FALSE;
298 dev_spec->shadow_ram[i].value = 0xFFFF;
299 }
300
301 /* Function Pointers */
241 struct e1000_dev_spec_ich8lan *dev_spec;
242 u32 gfpreg, sector_base_addr, sector_end_addr;
243 s32 ret_val = E1000_SUCCESS;
244 u16 i;
245
246 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
247
248 /* Can't read flash registers if the register set isn't mapped. */

--- 40 unchanged lines hidden (view full) ---

289
290 /* Clear shadow ram */
291 for (i = 0; i < nvm->word_size; i++) {
292 dev_spec->shadow_ram[i].modified = FALSE;
293 dev_spec->shadow_ram[i].value = 0xFFFF;
294 }
295
296 /* Function Pointers */
302 func->acquire_nvm = e1000_acquire_swflag_ich8lan;
303 func->read_nvm = e1000_read_nvm_ich8lan;
304 func->release_nvm = e1000_release_swflag_ich8lan;
305 func->update_nvm = e1000_update_nvm_checksum_ich8lan;
306 func->valid_led_default = e1000_valid_led_default_ich8lan;
307 func->validate_nvm = e1000_validate_nvm_checksum_ich8lan;
308 func->write_nvm = e1000_write_nvm_ich8lan;
297 nvm->ops.acquire = e1000_acquire_swflag_ich8lan;
298 nvm->ops.read = e1000_read_nvm_ich8lan;
299 nvm->ops.release = e1000_release_swflag_ich8lan;
300 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
301 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
302 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
303 nvm->ops.write = e1000_write_nvm_ich8lan;
309
310out:
311 return ret_val;
312}
313
314/**
315 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
316 * @hw: pointer to the HW structure
317 *
318 * Initialize family-specific MAC parameters and function
319 * pointers.
320 **/
304
305out:
306 return ret_val;
307}
308
309/**
310 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
311 * @hw: pointer to the HW structure
312 *
313 * Initialize family-specific MAC parameters and function
314 * pointers.
315 **/
321STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
316static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
322{
323 struct e1000_mac_info *mac = &hw->mac;
317{
318 struct e1000_mac_info *mac = &hw->mac;
324 struct e1000_functions *func = &hw->func;
325 s32 ret_val = E1000_SUCCESS;
326
327 DEBUGFUNC("e1000_init_mac_params_ich8lan");
328
329 /* Set media type function pointer */
330 hw->phy.media_type = e1000_media_type_copper;
331
332 /* Set mta register count */

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338 /* Set if part includes ASF firmware */
339 mac->asf_firmware_present = TRUE;
340 /* Set if manageability features are enabled. */
341 mac->arc_subsystem_valid = TRUE;
342
343 /* Function pointers */
344
345 /* bus type/speed/width */
319 s32 ret_val = E1000_SUCCESS;
320
321 DEBUGFUNC("e1000_init_mac_params_ich8lan");
322
323 /* Set media type function pointer */
324 hw->phy.media_type = e1000_media_type_copper;
325
326 /* Set mta register count */

--- 5 unchanged lines hidden (view full) ---

332 /* Set if part includes ASF firmware */
333 mac->asf_firmware_present = TRUE;
334 /* Set if manageability features are enabled. */
335 mac->arc_subsystem_valid = TRUE;
336
337 /* Function pointers */
338
339 /* bus type/speed/width */
346 func->get_bus_info = e1000_get_bus_info_ich8lan;
340 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
347 /* reset */
341 /* reset */
348 func->reset_hw = e1000_reset_hw_ich8lan;
342 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
349 /* hw initialization */
343 /* hw initialization */
350 func->init_hw = e1000_init_hw_ich8lan;
344 mac->ops.init_hw = e1000_init_hw_ich8lan;
351 /* link setup */
345 /* link setup */
352 func->setup_link = e1000_setup_link_ich8lan;
346 mac->ops.setup_link = e1000_setup_link_ich8lan;
353 /* physical interface setup */
347 /* physical interface setup */
354 func->setup_physical_interface = e1000_setup_copper_link_ich8lan;
348 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
355 /* check for link */
349 /* check for link */
356 func->check_for_link = e1000_check_for_copper_link_generic;
350 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
357 /* check management mode */
351 /* check management mode */
358 func->check_mng_mode = e1000_check_mng_mode_ich8lan;
352 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
359 /* link info */
353 /* link info */
360 func->get_link_up_info = e1000_get_link_up_info_ich8lan;
354 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
361 /* multicast address update */
355 /* multicast address update */
362 func->update_mc_addr_list = e1000_update_mc_addr_list_generic;
356 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
363 /* setting MTA */
357 /* setting MTA */
364 func->mta_set = e1000_mta_set_generic;
358 mac->ops.mta_set = e1000_mta_set_generic;
365 /* blink LED */
359 /* blink LED */
366 func->blink_led = e1000_blink_led_generic;
360 mac->ops.blink_led = e1000_blink_led_generic;
367 /* setup LED */
361 /* setup LED */
368 func->setup_led = e1000_setup_led_generic;
362 mac->ops.setup_led = e1000_setup_led_generic;
369 /* cleanup LED */
363 /* cleanup LED */
370 func->cleanup_led = e1000_cleanup_led_ich8lan;
364 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
371 /* turn on/off LED */
365 /* turn on/off LED */
372 func->led_on = e1000_led_on_ich8lan;
373 func->led_off = e1000_led_off_ich8lan;
366 mac->ops.led_on = e1000_led_on_ich8lan;
367 mac->ops.led_off = e1000_led_off_ich8lan;
374 /* remove device */
368 /* remove device */
375 func->remove_device = e1000_remove_device_generic;
369 mac->ops.remove_device = e1000_remove_device_generic;
376 /* clear hardware counters */
370 /* clear hardware counters */
377 func->clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
371 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
378
379 hw->dev_spec_size = sizeof(struct e1000_dev_spec_ich8lan);
380
381 /* Device-specific structure allocation */
382 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size);
383 if (ret_val)
384 goto out;
385

--- 11 unchanged lines hidden (view full) ---

397 * @hw: pointer to the HW structure
398 *
399 * Initialize family-specific function pointers for PHY, MAC, and NVM.
400 **/
401void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
402{
403 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
404
372
373 hw->dev_spec_size = sizeof(struct e1000_dev_spec_ich8lan);
374
375 /* Device-specific structure allocation */
376 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size);
377 if (ret_val)
378 goto out;
379

--- 11 unchanged lines hidden (view full) ---

391 * @hw: pointer to the HW structure
392 *
393 * Initialize family-specific function pointers for PHY, MAC, and NVM.
394 **/
395void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
396{
397 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
398
405 hw->func.init_mac_params = e1000_init_mac_params_ich8lan;
406 hw->func.init_nvm_params = e1000_init_nvm_params_ich8lan;
407 hw->func.init_phy_params = e1000_init_phy_params_ich8lan;
399 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
400 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
401 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
408}
409
410/**
411 * e1000_acquire_swflag_ich8lan - Acquire software control flag
412 * @hw: pointer to the HW structure
413 *
414 * Acquires the software control flag for performing NVM and PHY
415 * operations. This is a function pointer entry point only called by
416 * read/write routines for the PHY and NVM parts.
417 **/
402}
403
404/**
405 * e1000_acquire_swflag_ich8lan - Acquire software control flag
406 * @hw: pointer to the HW structure
407 *
408 * Acquires the software control flag for performing NVM and PHY
409 * operations. This is a function pointer entry point only called by
410 * read/write routines for the PHY and NVM parts.
411 **/
418STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
412static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
419{
420 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
421 s32 ret_val = E1000_SUCCESS;
422
423 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
424
425 while (timeout) {
426 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);

--- 22 unchanged lines hidden (view full) ---

449/**
450 * e1000_release_swflag_ich8lan - Release software control flag
451 * @hw: pointer to the HW structure
452 *
453 * Releases the software control flag for performing NVM and PHY operations.
454 * This is a function pointer entry point only called by read/write
455 * routines for the PHY and NVM parts.
456 **/
413{
414 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
415 s32 ret_val = E1000_SUCCESS;
416
417 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
418
419 while (timeout) {
420 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);

--- 22 unchanged lines hidden (view full) ---

443/**
444 * e1000_release_swflag_ich8lan - Release software control flag
445 * @hw: pointer to the HW structure
446 *
447 * Releases the software control flag for performing NVM and PHY operations.
448 * This is a function pointer entry point only called by read/write
449 * routines for the PHY and NVM parts.
450 **/
457STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
451static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
458{
459 u32 extcnf_ctrl;
460
461 DEBUGFUNC("e1000_release_swflag_ich8lan");
462
463 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
464 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
465 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);

--- 4 unchanged lines hidden (view full) ---

470/**
471 * e1000_check_mng_mode_ich8lan - Checks management mode
472 * @hw: pointer to the HW structure
473 *
474 * This checks if the adapter has manageability enabled.
475 * This is a function pointer entry point only called by read/write
476 * routines for the PHY and NVM parts.
477 **/
452{
453 u32 extcnf_ctrl;
454
455 DEBUGFUNC("e1000_release_swflag_ich8lan");
456
457 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
458 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
459 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);

--- 4 unchanged lines hidden (view full) ---

464/**
465 * e1000_check_mng_mode_ich8lan - Checks management mode
466 * @hw: pointer to the HW structure
467 *
468 * This checks if the adapter has manageability enabled.
469 * This is a function pointer entry point only called by read/write
470 * routines for the PHY and NVM parts.
471 **/
478STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
472static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
479{
480 u32 fwsm;
481
482 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
483
484 fwsm = E1000_READ_REG(hw, E1000_FWSM);
485
486 return ((fwsm & E1000_FWSM_MODE_MASK) ==
487 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
488}
489
490/**
491 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
492 * @hw: pointer to the HW structure
493 *
494 * Checks if firmware is blocking the reset of the PHY.
495 * This is a function pointer entry point only called by
496 * reset routines.
497 **/
473{
474 u32 fwsm;
475
476 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
477
478 fwsm = E1000_READ_REG(hw, E1000_FWSM);
479
480 return ((fwsm & E1000_FWSM_MODE_MASK) ==
481 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
482}
483
484/**
485 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
486 * @hw: pointer to the HW structure
487 *
488 * Checks if firmware is blocking the reset of the PHY.
489 * This is a function pointer entry point only called by
490 * reset routines.
491 **/
498STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
492static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
499{
500 u32 fwsm;
501
502 DEBUGFUNC("e1000_check_reset_block_ich8lan");
503
504 fwsm = E1000_READ_REG(hw, E1000_FWSM);
505
506 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
507 : E1000_BLK_PHY_RESET;
508}
509
510/**
511 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
512 * @hw: pointer to the HW structure
513 *
514 * Forces the speed and duplex settings of the PHY.
515 * This is a function pointer entry point only called by
516 * PHY setup routines.
517 **/
493{
494 u32 fwsm;
495
496 DEBUGFUNC("e1000_check_reset_block_ich8lan");
497
498 fwsm = E1000_READ_REG(hw, E1000_FWSM);
499
500 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
501 : E1000_BLK_PHY_RESET;
502}
503
504/**
505 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
506 * @hw: pointer to the HW structure
507 *
508 * Forces the speed and duplex settings of the PHY.
509 * This is a function pointer entry point only called by
510 * PHY setup routines.
511 **/
518STATIC s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
512static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
519{
520 struct e1000_phy_info *phy = &hw->phy;
521 s32 ret_val;
522 u16 data;
523 bool link;
524
525 DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan");
526
527 if (phy->type != e1000_phy_ife) {
528 ret_val = e1000_phy_force_speed_duplex_igp(hw);
529 goto out;
530 }
531
513{
514 struct e1000_phy_info *phy = &hw->phy;
515 s32 ret_val;
516 u16 data;
517 bool link;
518
519 DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan");
520
521 if (phy->type != e1000_phy_ife) {
522 ret_val = e1000_phy_force_speed_duplex_igp(hw);
523 goto out;
524 }
525
532 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &data);
526 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
533 if (ret_val)
534 goto out;
535
536 e1000_phy_force_speed_duplex_setup(hw, &data);
537
527 if (ret_val)
528 goto out;
529
530 e1000_phy_force_speed_duplex_setup(hw, &data);
531
538 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, data);
532 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
539 if (ret_val)
540 goto out;
541
542 /* Disable MDI-X support for 10/100 */
533 if (ret_val)
534 goto out;
535
536 /* Disable MDI-X support for 10/100 */
543 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
537 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
544 if (ret_val)
545 goto out;
546
547 data &= ~IFE_PMC_AUTO_MDIX;
548 data &= ~IFE_PMC_FORCE_MDIX;
549
538 if (ret_val)
539 goto out;
540
541 data &= ~IFE_PMC_AUTO_MDIX;
542 data &= ~IFE_PMC_FORCE_MDIX;
543
550 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, data);
544 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
551 if (ret_val)
552 goto out;
553
554 DEBUGOUT1("IFE PMC: %X\n", data);
555
556 usec_delay(1);
557
558 if (phy->autoneg_wait_to_complete) {

--- 26 unchanged lines hidden (view full) ---

585/**
586 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
587 * @hw: pointer to the HW structure
588 *
589 * Resets the PHY
590 * This is a function pointer entry point called by drivers
591 * or other shared routines.
592 **/
545 if (ret_val)
546 goto out;
547
548 DEBUGOUT1("IFE PMC: %X\n", data);
549
550 usec_delay(1);
551
552 if (phy->autoneg_wait_to_complete) {

--- 26 unchanged lines hidden (view full) ---

579/**
580 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
581 * @hw: pointer to the HW structure
582 *
583 * Resets the PHY
584 * This is a function pointer entry point called by drivers
585 * or other shared routines.
586 **/
593STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
587static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
594{
595 struct e1000_phy_info *phy = &hw->phy;
588{
589 struct e1000_phy_info *phy = &hw->phy;
590 struct e1000_nvm_info *nvm = &hw->nvm;
596 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
597 s32 ret_val;
598 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
599 u16 word_addr, reg_data, reg_addr, phy_page = 0;
600
601 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
602
603 ret_val = e1000_phy_hw_reset_generic(hw);

--- 61 unchanged lines hidden (view full) ---

665 * Configure LCD from extended configuration
666 * region.
667 */
668
669 /* cnf_base_addr is in DWORD */
670 word_addr = (u16)(cnf_base_addr << 1);
671
672 for (i = 0; i < cnf_size; i++) {
591 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
592 s32 ret_val;
593 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
594 u16 word_addr, reg_data, reg_addr, phy_page = 0;
595
596 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
597
598 ret_val = e1000_phy_hw_reset_generic(hw);

--- 61 unchanged lines hidden (view full) ---

660 * Configure LCD from extended configuration
661 * region.
662 */
663
664 /* cnf_base_addr is in DWORD */
665 word_addr = (u16)(cnf_base_addr << 1);
666
667 for (i = 0; i < cnf_size; i++) {
673 ret_val = e1000_read_nvm(hw,
668 ret_val = nvm->ops.read(hw,
674 (word_addr + i * 2),
675 1,
676 &reg_data);
677 if (ret_val)
678 goto out;
679
669 (word_addr + i * 2),
670 1,
671 &reg_data);
672 if (ret_val)
673 goto out;
674
680 ret_val = e1000_read_nvm(hw,
675 ret_val = nvm->ops.read(hw,
681 (word_addr + i * 2 + 1),
682 1,
683 &reg_addr);
684 if (ret_val)
685 goto out;
686
687 /* Save off the PHY page for future writes. */
688 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
689 phy_page = reg_data;
690 continue;
691 }
692
693 reg_addr |= phy_page;
694
676 (word_addr + i * 2 + 1),
677 1,
678 &reg_addr);
679 if (ret_val)
680 goto out;
681
682 /* Save off the PHY page for future writes. */
683 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
684 phy_page = reg_data;
685 continue;
686 }
687
688 reg_addr |= phy_page;
689
695 ret_val = e1000_write_phy_reg(hw,
690 ret_val = phy->ops.write_reg(hw,
696 (u32)reg_addr,
697 reg_data);
698 if (ret_val)
699 goto out;
700 }
701 }
702
703out:
704 return ret_val;
705}
706
707/**
708 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
709 * @hw: pointer to the HW structure
710 *
711 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
712 * This is a function pointer entry point called by drivers
713 * or other shared routines.
714 **/
691 (u32)reg_addr,
692 reg_data);
693 if (ret_val)
694 goto out;
695 }
696 }
697
698out:
699 return ret_val;
700}
701
702/**
703 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
704 * @hw: pointer to the HW structure
705 *
706 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
707 * This is a function pointer entry point called by drivers
708 * or other shared routines.
709 **/
715STATIC s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
710static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
716{
717 s32 ret_val = -E1000_ERR_PHY_TYPE;
718
719 DEBUGFUNC("e1000_get_phy_info_ich8lan");
720
721 switch (hw->phy.type) {
722 case e1000_phy_ife:
723 ret_val = e1000_get_phy_info_ife_ich8lan(hw);

--- 31 unchanged lines hidden (view full) ---

755 goto out;
756
757 if (!link) {
758 DEBUGOUT("Phy info is only valid if link is up\n");
759 ret_val = -E1000_ERR_CONFIG;
760 goto out;
761 }
762
711{
712 s32 ret_val = -E1000_ERR_PHY_TYPE;
713
714 DEBUGFUNC("e1000_get_phy_info_ich8lan");
715
716 switch (hw->phy.type) {
717 case e1000_phy_ife:
718 ret_val = e1000_get_phy_info_ife_ich8lan(hw);

--- 31 unchanged lines hidden (view full) ---

750 goto out;
751
752 if (!link) {
753 DEBUGOUT("Phy info is only valid if link is up\n");
754 ret_val = -E1000_ERR_CONFIG;
755 goto out;
756 }
757
763 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
758 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
764 if (ret_val)
765 goto out;
766 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
767 ? FALSE : TRUE;
768
769 if (phy->polarity_correction) {
770 ret_val = e1000_check_polarity_ife_ich8lan(hw);
771 if (ret_val)
772 goto out;
773 } else {
774 /* Polarity is forced */
775 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
776 ? e1000_rev_polarity_reversed
777 : e1000_rev_polarity_normal;
778 }
779
759 if (ret_val)
760 goto out;
761 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
762 ? FALSE : TRUE;
763
764 if (phy->polarity_correction) {
765 ret_val = e1000_check_polarity_ife_ich8lan(hw);
766 if (ret_val)
767 goto out;
768 } else {
769 /* Polarity is forced */
770 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
771 ? e1000_rev_polarity_reversed
772 : e1000_rev_polarity_normal;
773 }
774
780 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
775 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
781 if (ret_val)
782 goto out;
783
784 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
785
786 /* The following parameters are undefined for 10/100 operation. */
787 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
788 phy->local_rx = e1000_1000t_rx_status_undefined;

--- 6 unchanged lines hidden (view full) ---

795/**
796 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
797 * @hw: pointer to the HW structure
798 *
799 * Polarity is determined on the polarity reversal feature being enabled.
800 * This function is only called by other family-specific
801 * routines.
802 **/
776 if (ret_val)
777 goto out;
778
779 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
780
781 /* The following parameters are undefined for 10/100 operation. */
782 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
783 phy->local_rx = e1000_1000t_rx_status_undefined;

--- 6 unchanged lines hidden (view full) ---

790/**
791 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
792 * @hw: pointer to the HW structure
793 *
794 * Polarity is determined on the polarity reversal feature being enabled.
795 * This function is only called by other family-specific
796 * routines.
797 **/
803STATIC s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
798static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
804{
805 struct e1000_phy_info *phy = &hw->phy;
806 s32 ret_val;
807 u16 phy_data, offset, mask;
808
809 DEBUGFUNC("e1000_check_polarity_ife_ich8lan");
810
811 /*
812 * Polarity is determined based on the reversal feature
813 * being enabled.
814 */
815 if (phy->polarity_correction) {
816 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
817 mask = IFE_PESC_POLARITY_REVERSED;
818 } else {
819 offset = IFE_PHY_SPECIAL_CONTROL;
820 mask = IFE_PSC_FORCE_POLARITY;
821 }
822
799{
800 struct e1000_phy_info *phy = &hw->phy;
801 s32 ret_val;
802 u16 phy_data, offset, mask;
803
804 DEBUGFUNC("e1000_check_polarity_ife_ich8lan");
805
806 /*
807 * Polarity is determined based on the reversal feature
808 * being enabled.
809 */
810 if (phy->polarity_correction) {
811 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
812 mask = IFE_PESC_POLARITY_REVERSED;
813 } else {
814 offset = IFE_PHY_SPECIAL_CONTROL;
815 mask = IFE_PSC_FORCE_POLARITY;
816 }
817
823 ret_val = e1000_read_phy_reg(hw, offset, &phy_data);
818 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
824
825 if (!ret_val)
826 phy->cable_polarity = (phy_data & mask)
827 ? e1000_rev_polarity_reversed
828 : e1000_rev_polarity_normal;
829
830 return ret_val;
831}

--- 6 unchanged lines hidden (view full) ---

838 * Sets the LPLU D0 state according to the active flag. When
839 * activating LPLU this function also disables smart speed
840 * and vice versa. LPLU will not be activated unless the
841 * device autonegotiation advertisement meets standards of
842 * either 10 or 10/100 or 10/100/1000 at all duplexes.
843 * This is a function pointer entry point only called by
844 * PHY setup routines.
845 **/
819
820 if (!ret_val)
821 phy->cable_polarity = (phy_data & mask)
822 ? e1000_rev_polarity_reversed
823 : e1000_rev_polarity_normal;
824
825 return ret_val;
826}

--- 6 unchanged lines hidden (view full) ---

833 * Sets the LPLU D0 state according to the active flag. When
834 * activating LPLU this function also disables smart speed
835 * and vice versa. LPLU will not be activated unless the
836 * device autonegotiation advertisement meets standards of
837 * either 10 or 10/100 or 10/100/1000 at all duplexes.
838 * This is a function pointer entry point only called by
839 * PHY setup routines.
840 **/
846STATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
841static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
847 bool active)
848{
849 struct e1000_phy_info *phy = &hw->phy;
850 u32 phy_ctrl;
851 s32 ret_val = E1000_SUCCESS;
852 u16 data;
853
854 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");

--- 11 unchanged lines hidden (view full) ---

866 * Call gig speed drop workaround on LPLU before accessing
867 * any PHY registers
868 */
869 if ((hw->mac.type == e1000_ich8lan) &&
870 (hw->phy.type == e1000_phy_igp_3))
871 e1000_gig_downshift_workaround_ich8lan(hw);
872
873 /* When LPLU is enabled, we should disable SmartSpeed */
842 bool active)
843{
844 struct e1000_phy_info *phy = &hw->phy;
845 u32 phy_ctrl;
846 s32 ret_val = E1000_SUCCESS;
847 u16 data;
848
849 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");

--- 11 unchanged lines hidden (view full) ---

861 * Call gig speed drop workaround on LPLU before accessing
862 * any PHY registers
863 */
864 if ((hw->mac.type == e1000_ich8lan) &&
865 (hw->phy.type == e1000_phy_igp_3))
866 e1000_gig_downshift_workaround_ich8lan(hw);
867
868 /* When LPLU is enabled, we should disable SmartSpeed */
874 ret_val = e1000_read_phy_reg(hw,
869 ret_val = phy->ops.read_reg(hw,
875 IGP01E1000_PHY_PORT_CONFIG,
876 &data);
877 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
870 IGP01E1000_PHY_PORT_CONFIG,
871 &data);
872 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
878 ret_val = e1000_write_phy_reg(hw,
873 ret_val = phy->ops.write_reg(hw,
879 IGP01E1000_PHY_PORT_CONFIG,
880 data);
881 if (ret_val)
882 goto out;
883 } else {
884 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
885 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
886
887 /*
888 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
889 * during Dx states where the power conservation is most
890 * important. During driver activity we should enable
891 * SmartSpeed, so performance is maintained.
892 */
893 if (phy->smart_speed == e1000_smart_speed_on) {
874 IGP01E1000_PHY_PORT_CONFIG,
875 data);
876 if (ret_val)
877 goto out;
878 } else {
879 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
880 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
881
882 /*
883 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
884 * during Dx states where the power conservation is most
885 * important. During driver activity we should enable
886 * SmartSpeed, so performance is maintained.
887 */
888 if (phy->smart_speed == e1000_smart_speed_on) {
894 ret_val = e1000_read_phy_reg(hw,
889 ret_val = phy->ops.read_reg(hw,
895 IGP01E1000_PHY_PORT_CONFIG,
896 &data);
897 if (ret_val)
898 goto out;
899
900 data |= IGP01E1000_PSCFR_SMART_SPEED;
890 IGP01E1000_PHY_PORT_CONFIG,
891 &data);
892 if (ret_val)
893 goto out;
894
895 data |= IGP01E1000_PSCFR_SMART_SPEED;
901 ret_val = e1000_write_phy_reg(hw,
896 ret_val = phy->ops.write_reg(hw,
902 IGP01E1000_PHY_PORT_CONFIG,
903 data);
904 if (ret_val)
905 goto out;
906 } else if (phy->smart_speed == e1000_smart_speed_off) {
897 IGP01E1000_PHY_PORT_CONFIG,
898 data);
899 if (ret_val)
900 goto out;
901 } else if (phy->smart_speed == e1000_smart_speed_off) {
907 ret_val = e1000_read_phy_reg(hw,
902 ret_val = phy->ops.read_reg(hw,
908 IGP01E1000_PHY_PORT_CONFIG,
909 &data);
910 if (ret_val)
911 goto out;
912
913 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
903 IGP01E1000_PHY_PORT_CONFIG,
904 &data);
905 if (ret_val)
906 goto out;
907
908 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
914 ret_val = e1000_write_phy_reg(hw,
909 ret_val = phy->ops.write_reg(hw,
915 IGP01E1000_PHY_PORT_CONFIG,
916 data);
917 if (ret_val)
918 goto out;
919 }
920 }
921
922out:

--- 8 unchanged lines hidden (view full) ---

931 * Sets the LPLU D3 state according to the active flag. When
932 * activating LPLU this function also disables smart speed
933 * and vice versa. LPLU will not be activated unless the
934 * device autonegotiation advertisement meets standards of
935 * either 10 or 10/100 or 10/100/1000 at all duplexes.
936 * This is a function pointer entry point only called by
937 * PHY setup routines.
938 **/
910 IGP01E1000_PHY_PORT_CONFIG,
911 data);
912 if (ret_val)
913 goto out;
914 }
915 }
916
917out:

--- 8 unchanged lines hidden (view full) ---

926 * Sets the LPLU D3 state according to the active flag. When
927 * activating LPLU this function also disables smart speed
928 * and vice versa. LPLU will not be activated unless the
929 * device autonegotiation advertisement meets standards of
930 * either 10 or 10/100 or 10/100/1000 at all duplexes.
931 * This is a function pointer entry point only called by
932 * PHY setup routines.
933 **/
939STATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
934static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
940 bool active)
941{
942 struct e1000_phy_info *phy = &hw->phy;
943 u32 phy_ctrl;
944 s32 ret_val = E1000_SUCCESS;
945 u16 data;
946
947 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");

--- 5 unchanged lines hidden (view full) ---

953 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
954 /*
955 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
956 * during Dx states where the power conservation is most
957 * important. During driver activity we should enable
958 * SmartSpeed, so performance is maintained.
959 */
960 if (phy->smart_speed == e1000_smart_speed_on) {
935 bool active)
936{
937 struct e1000_phy_info *phy = &hw->phy;
938 u32 phy_ctrl;
939 s32 ret_val = E1000_SUCCESS;
940 u16 data;
941
942 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");

--- 5 unchanged lines hidden (view full) ---

948 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
949 /*
950 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
951 * during Dx states where the power conservation is most
952 * important. During driver activity we should enable
953 * SmartSpeed, so performance is maintained.
954 */
955 if (phy->smart_speed == e1000_smart_speed_on) {
961 ret_val = e1000_read_phy_reg(hw,
956 ret_val = phy->ops.read_reg(hw,
962 IGP01E1000_PHY_PORT_CONFIG,
963 &data);
964 if (ret_val)
965 goto out;
966
967 data |= IGP01E1000_PSCFR_SMART_SPEED;
957 IGP01E1000_PHY_PORT_CONFIG,
958 &data);
959 if (ret_val)
960 goto out;
961
962 data |= IGP01E1000_PSCFR_SMART_SPEED;
968 ret_val = e1000_write_phy_reg(hw,
963 ret_val = phy->ops.write_reg(hw,
969 IGP01E1000_PHY_PORT_CONFIG,
970 data);
971 if (ret_val)
972 goto out;
973 } else if (phy->smart_speed == e1000_smart_speed_off) {
964 IGP01E1000_PHY_PORT_CONFIG,
965 data);
966 if (ret_val)
967 goto out;
968 } else if (phy->smart_speed == e1000_smart_speed_off) {
974 ret_val = e1000_read_phy_reg(hw,
969 ret_val = phy->ops.read_reg(hw,
975 IGP01E1000_PHY_PORT_CONFIG,
976 &data);
977 if (ret_val)
978 goto out;
979
980 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
970 IGP01E1000_PHY_PORT_CONFIG,
971 &data);
972 if (ret_val)
973 goto out;
974
975 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
981 ret_val = e1000_write_phy_reg(hw,
976 ret_val = phy->ops.write_reg(hw,
982 IGP01E1000_PHY_PORT_CONFIG,
983 data);
984 if (ret_val)
985 goto out;
986 }
987 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
988 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
989 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {

--- 4 unchanged lines hidden (view full) ---

994 * Call gig speed drop workaround on LPLU before accessing
995 * any PHY registers
996 */
997 if ((hw->mac.type == e1000_ich8lan) &&
998 (hw->phy.type == e1000_phy_igp_3))
999 e1000_gig_downshift_workaround_ich8lan(hw);
1000
1001 /* When LPLU is enabled, we should disable SmartSpeed */
977 IGP01E1000_PHY_PORT_CONFIG,
978 data);
979 if (ret_val)
980 goto out;
981 }
982 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
983 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
984 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {

--- 4 unchanged lines hidden (view full) ---

989 * Call gig speed drop workaround on LPLU before accessing
990 * any PHY registers
991 */
992 if ((hw->mac.type == e1000_ich8lan) &&
993 (hw->phy.type == e1000_phy_igp_3))
994 e1000_gig_downshift_workaround_ich8lan(hw);
995
996 /* When LPLU is enabled, we should disable SmartSpeed */
1002 ret_val = e1000_read_phy_reg(hw,
997 ret_val = phy->ops.read_reg(hw,
1003 IGP01E1000_PHY_PORT_CONFIG,
1004 &data);
1005 if (ret_val)
1006 goto out;
1007
1008 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
998 IGP01E1000_PHY_PORT_CONFIG,
999 &data);
1000 if (ret_val)
1001 goto out;
1002
1003 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1009 ret_val = e1000_write_phy_reg(hw,
1004 ret_val = phy->ops.write_reg(hw,
1010 IGP01E1000_PHY_PORT_CONFIG,
1011 data);
1012 }
1013
1014out:
1015 return ret_val;
1016}
1017
1018/**
1019 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1020 * @hw: pointer to the HW structure
1021 * @bank: pointer to the variable that returns the active bank
1022 *
1023 * Reads signature byte from the NVM using the flash access registers.
1024 **/
1005 IGP01E1000_PHY_PORT_CONFIG,
1006 data);
1007 }
1008
1009out:
1010 return ret_val;
1011}
1012
1013/**
1014 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1015 * @hw: pointer to the HW structure
1016 * @bank: pointer to the variable that returns the active bank
1017 *
1018 * Reads signature byte from the NVM using the flash access registers.
1019 **/
1025STATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1020static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1026{
1027 s32 ret_val = E1000_SUCCESS;
1021{
1022 s32 ret_val = E1000_SUCCESS;
1028 struct e1000_nvm_info *nvm = &hw->nvm;
1029 /* flash bank size is in words */
1030 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1031 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1032 u8 bank_high_byte = 0;
1033
1034 if (hw->mac.type != e1000_ich10lan) {
1035 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL)
1036 *bank = 1;
1037 else
1038 *bank = 0;
1039 } else if (hw->dev_spec != NULL) {
1040 /*
1041 * Make sure the signature for bank 0 is valid,
1042 * if not check for bank1
1043 */
1044 e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);
1045 if ((bank_high_byte & 0xC0) == 0x80) {
1046 *bank = 0;
1047 } else {
1048 /*
1049 * find if segment 1 is valid by verifying
1050 * bit 15:14 = 10b in word 0x13
1051 */
1052 e1000_read_flash_byte_ich8lan(hw,
1053 act_offset + bank1_offset,
1054 &bank_high_byte);
1055
1056 /* bank1 has a valid signature equivalent to SEC1V */
1057 if ((bank_high_byte & 0xC0) == 0x80) {
1058 *bank = 1;
1059 } else {
1060 DEBUGOUT("ERROR: EEPROM not present\n");
1061 ret_val = -E1000_ERR_NVM;
1062 }
1063 }
1064 } else {
1065 DEBUGOUT("DEV SPEC is NULL\n");
1066 ret_val = -E1000_ERR_NVM;
1067 }
1023 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL)
1024 *bank = 1;
1025 else
1026 *bank = 0;
1068
1069 return ret_val;
1070}
1071
1072/**
1073 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1074 * @hw: pointer to the HW structure
1075 * @offset: The offset (in bytes) of the word(s) to read.
1076 * @words: Size of data to read in words
1077 * @data: Pointer to the word(s) to read at offset.
1078 *
1079 * Reads a word(s) from the NVM using the flash access registers.
1080 **/
1027
1028 return ret_val;
1029}
1030
1031/**
1032 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1033 * @hw: pointer to the HW structure
1034 * @offset: The offset (in bytes) of the word(s) to read.
1035 * @words: Size of data to read in words
1036 * @data: Pointer to the word(s) to read at offset.
1037 *
1038 * Reads a word(s) from the NVM using the flash access registers.
1039 **/
1081STATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1040static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1082 u16 *data)
1083{
1084 struct e1000_nvm_info *nvm = &hw->nvm;
1085 struct e1000_dev_spec_ich8lan *dev_spec;
1086 u32 act_offset;
1087 s32 ret_val = E1000_SUCCESS;
1088 u32 bank = 0;
1089 u16 i, word;

--- 10 unchanged lines hidden (view full) ---

1100
1101 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1102 (words == 0)) {
1103 DEBUGOUT("nvm parameter(s) out of bounds\n");
1104 ret_val = -E1000_ERR_NVM;
1105 goto out;
1106 }
1107
1041 u16 *data)
1042{
1043 struct e1000_nvm_info *nvm = &hw->nvm;
1044 struct e1000_dev_spec_ich8lan *dev_spec;
1045 u32 act_offset;
1046 s32 ret_val = E1000_SUCCESS;
1047 u32 bank = 0;
1048 u16 i, word;

--- 10 unchanged lines hidden (view full) ---

1059
1060 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1061 (words == 0)) {
1062 DEBUGOUT("nvm parameter(s) out of bounds\n");
1063 ret_val = -E1000_ERR_NVM;
1064 goto out;
1065 }
1066
1108 ret_val = e1000_acquire_nvm(hw);
1067 ret_val = nvm->ops.acquire(hw);
1109 if (ret_val)
1110 goto out;
1111
1112 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1113 if (ret_val != E1000_SUCCESS)
1114 goto out;
1115
1116 act_offset = (bank) ? nvm->flash_bank_size : 0;

--- 8 unchanged lines hidden (view full) ---

1125 act_offset + i,
1126 &word);
1127 if (ret_val)
1128 break;
1129 data[i] = word;
1130 }
1131 }
1132
1068 if (ret_val)
1069 goto out;
1070
1071 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1072 if (ret_val != E1000_SUCCESS)
1073 goto out;
1074
1075 act_offset = (bank) ? nvm->flash_bank_size : 0;

--- 8 unchanged lines hidden (view full) ---

1084 act_offset + i,
1085 &word);
1086 if (ret_val)
1087 break;
1088 data[i] = word;
1089 }
1090 }
1091
1133 e1000_release_nvm(hw);
1092 nvm->ops.release(hw);
1134
1135out:
1136 return ret_val;
1137}
1138
1139/**
1140 * e1000_flash_cycle_init_ich8lan - Initialize flash
1141 * @hw: pointer to the HW structure

--- 113 unchanged lines hidden (view full) ---

1255 * e1000_read_flash_word_ich8lan - Read word from flash
1256 * @hw: pointer to the HW structure
1257 * @offset: offset to data location
1258 * @data: pointer to the location for storing the data
1259 *
1260 * Reads the flash word at offset into data. Offset is converted
1261 * to bytes before read.
1262 **/
1093
1094out:
1095 return ret_val;
1096}
1097
1098/**
1099 * e1000_flash_cycle_init_ich8lan - Initialize flash
1100 * @hw: pointer to the HW structure

--- 113 unchanged lines hidden (view full) ---

1214 * e1000_read_flash_word_ich8lan - Read word from flash
1215 * @hw: pointer to the HW structure
1216 * @offset: offset to data location
1217 * @data: pointer to the location for storing the data
1218 *
1219 * Reads the flash word at offset into data. Offset is converted
1220 * to bytes before read.
1221 **/
1263STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1222static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1264 u16 *data)
1265{
1266 s32 ret_val;
1267
1268 DEBUGFUNC("e1000_read_flash_word_ich8lan");
1269
1270 if (!data) {
1271 ret_val = -E1000_ERR_NVM;

--- 5 unchanged lines hidden (view full) ---

1277
1278 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1279
1280out:
1281 return ret_val;
1282}
1283
1284/**
1223 u16 *data)
1224{
1225 s32 ret_val;
1226
1227 DEBUGFUNC("e1000_read_flash_word_ich8lan");
1228
1229 if (!data) {
1230 ret_val = -E1000_ERR_NVM;

--- 5 unchanged lines hidden (view full) ---

1236
1237 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1238
1239out:
1240 return ret_val;
1241}
1242
1243/**
1285 * e1000_read_flash_byte_ich8lan - Read byte from flash
1286 * @hw: pointer to the HW structure
1287 * @offset: The offset of the byte to read.
1288 * @data: Pointer to a byte to store the value read.
1289 *
1290 * Reads a single byte from the NVM using the flash access registers.
1291 **/
1292STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1293 u8* data)
1294{
1295 s32 ret_val = E1000_SUCCESS;
1296 u16 word = 0;
1297
1298 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1299 if (ret_val)
1300 goto out;
1301
1302 *data = (u8)word;
1303
1304out:
1305 return ret_val;
1306}
1307
1308/**
1309 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1310 * @hw: pointer to the HW structure
1311 * @offset: The offset (in bytes) of the byte or word to read.
1312 * @size: Size of data to read, 1=byte 2=word
1313 * @data: Pointer to the word to store the value read.
1314 *
1315 * Reads a byte or word from the NVM using the flash access registers.
1316 **/

--- 75 unchanged lines hidden (view full) ---

1392 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1393 * @hw: pointer to the HW structure
1394 * @offset: The offset (in bytes) of the word(s) to write.
1395 * @words: Size of data to write in words
1396 * @data: Pointer to the word(s) to write at offset.
1397 *
1398 * Writes a byte or word to the NVM using the flash access registers.
1399 **/
1244 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1245 * @hw: pointer to the HW structure
1246 * @offset: The offset (in bytes) of the byte or word to read.
1247 * @size: Size of data to read, 1=byte 2=word
1248 * @data: Pointer to the word to store the value read.
1249 *
1250 * Reads a byte or word from the NVM using the flash access registers.
1251 **/

--- 75 unchanged lines hidden (view full) ---

1327 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1328 * @hw: pointer to the HW structure
1329 * @offset: The offset (in bytes) of the word(s) to write.
1330 * @words: Size of data to write in words
1331 * @data: Pointer to the word(s) to write at offset.
1332 *
1333 * Writes a byte or word to the NVM using the flash access registers.
1334 **/
1400STATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1335static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1401 u16 *data)
1402{
1403 struct e1000_nvm_info *nvm = &hw->nvm;
1404 struct e1000_dev_spec_ich8lan *dev_spec;
1405 s32 ret_val = E1000_SUCCESS;
1406 u16 i;
1407
1408 DEBUGFUNC("e1000_write_nvm_ich8lan");

--- 8 unchanged lines hidden (view full) ---

1417
1418 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1419 (words == 0)) {
1420 DEBUGOUT("nvm parameter(s) out of bounds\n");
1421 ret_val = -E1000_ERR_NVM;
1422 goto out;
1423 }
1424
1336 u16 *data)
1337{
1338 struct e1000_nvm_info *nvm = &hw->nvm;
1339 struct e1000_dev_spec_ich8lan *dev_spec;
1340 s32 ret_val = E1000_SUCCESS;
1341 u16 i;
1342
1343 DEBUGFUNC("e1000_write_nvm_ich8lan");

--- 8 unchanged lines hidden (view full) ---

1352
1353 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1354 (words == 0)) {
1355 DEBUGOUT("nvm parameter(s) out of bounds\n");
1356 ret_val = -E1000_ERR_NVM;
1357 goto out;
1358 }
1359
1425 ret_val = e1000_acquire_nvm(hw);
1360 ret_val = nvm->ops.acquire(hw);
1426 if (ret_val)
1427 goto out;
1428
1429 for (i = 0; i < words; i++) {
1430 dev_spec->shadow_ram[offset+i].modified = TRUE;
1431 dev_spec->shadow_ram[offset+i].value = data[i];
1432 }
1433
1361 if (ret_val)
1362 goto out;
1363
1364 for (i = 0; i < words; i++) {
1365 dev_spec->shadow_ram[offset+i].modified = TRUE;
1366 dev_spec->shadow_ram[offset+i].value = data[i];
1367 }
1368
1434 e1000_release_nvm(hw);
1369 nvm->ops.release(hw);
1435
1436out:
1437 return ret_val;
1438}
1439
1440/**
1441 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1442 * @hw: pointer to the HW structure
1443 *
1444 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1445 * which writes the checksum to the shadow ram. The changes in the shadow
1446 * ram are then committed to the EEPROM by processing each bank at a time
1447 * checking for the modified bit and writing only the pending changes.
1448 * After a successful commit, the shadow ram is cleared and is ready for
1449 * future writes.
1450 **/
1370
1371out:
1372 return ret_val;
1373}
1374
1375/**
1376 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1377 * @hw: pointer to the HW structure
1378 *
1379 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1380 * which writes the checksum to the shadow ram. The changes in the shadow
1381 * ram are then committed to the EEPROM by processing each bank at a time
1382 * checking for the modified bit and writing only the pending changes.
1383 * After a successful commit, the shadow ram is cleared and is ready for
1384 * future writes.
1385 **/
1451STATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1386static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1452{
1453 struct e1000_nvm_info *nvm = &hw->nvm;
1454 struct e1000_dev_spec_ich8lan *dev_spec;
1455 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1456 s32 ret_val;
1457 u16 data;
1458
1459 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
1460
1461 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
1462
1463 ret_val = e1000_update_nvm_checksum_generic(hw);
1464 if (ret_val)
1465 goto out;
1466
1467 if (nvm->type != e1000_nvm_flash_sw)
1468 goto out;
1469
1387{
1388 struct e1000_nvm_info *nvm = &hw->nvm;
1389 struct e1000_dev_spec_ich8lan *dev_spec;
1390 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1391 s32 ret_val;
1392 u16 data;
1393
1394 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
1395
1396 dev_spec = (struct e1000_dev_spec_ich8lan *)hw->dev_spec;
1397
1398 ret_val = e1000_update_nvm_checksum_generic(hw);
1399 if (ret_val)
1400 goto out;
1401
1402 if (nvm->type != e1000_nvm_flash_sw)
1403 goto out;
1404
1470 ret_val = e1000_acquire_nvm(hw);
1405 ret_val = nvm->ops.acquire(hw);
1471 if (ret_val)
1472 goto out;
1473
1474 /*
1475 * We're writing to the opposite bank so if we're on bank 1,
1476 * write to bank 0 etc. We also need to erase the segment that
1477 * is going to be written
1478 */

--- 56 unchanged lines hidden (view full) ---

1535 }
1536
1537 /*
1538 * Don't bother writing the segment valid bits if sector
1539 * programming failed.
1540 */
1541 if (ret_val) {
1542 DEBUGOUT("Flash commit failed.\n");
1406 if (ret_val)
1407 goto out;
1408
1409 /*
1410 * We're writing to the opposite bank so if we're on bank 1,
1411 * write to bank 0 etc. We also need to erase the segment that
1412 * is going to be written
1413 */

--- 56 unchanged lines hidden (view full) ---

1470 }
1471
1472 /*
1473 * Don't bother writing the segment valid bits if sector
1474 * programming failed.
1475 */
1476 if (ret_val) {
1477 DEBUGOUT("Flash commit failed.\n");
1543 e1000_release_nvm(hw);
1478 nvm->ops.release(hw);
1544 goto out;
1545 }
1546
1547 /*
1548 * Finally validate the new segment by setting bit 15:14
1549 * to 10b in word 0x13 , this can be done without an
1550 * erase as well since these bits are 11 to start with
1551 * and we need to change bit 14 to 0b
1552 */
1553 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1554 e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1555 data &= 0xBFFF;
1556 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1557 act_offset * 2 + 1,
1558 (u8)(data >> 8));
1559 if (ret_val) {
1479 goto out;
1480 }
1481
1482 /*
1483 * Finally validate the new segment by setting bit 15:14
1484 * to 10b in word 0x13 , this can be done without an
1485 * erase as well since these bits are 11 to start with
1486 * and we need to change bit 14 to 0b
1487 */
1488 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1489 e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1490 data &= 0xBFFF;
1491 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1492 act_offset * 2 + 1,
1493 (u8)(data >> 8));
1494 if (ret_val) {
1560 e1000_release_nvm(hw);
1495 nvm->ops.release(hw);
1561 goto out;
1562 }
1563
1564 /*
1565 * And invalidate the previously valid segment by setting
1566 * its signature word (0x13) high_byte to 0b. This can be
1567 * done without an erase because flash erase sets all bits
1568 * to 1's. We can write 1's to 0's without an erase
1569 */
1570 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1571 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1572 if (ret_val) {
1496 goto out;
1497 }
1498
1499 /*
1500 * And invalidate the previously valid segment by setting
1501 * its signature word (0x13) high_byte to 0b. This can be
1502 * done without an erase because flash erase sets all bits
1503 * to 1's. We can write 1's to 0's without an erase
1504 */
1505 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1506 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1507 if (ret_val) {
1573 e1000_release_nvm(hw);
1508 nvm->ops.release(hw);
1574 goto out;
1575 }
1576
1577 /* Great! Everything worked, we can now clear the cached entries. */
1578 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1579 dev_spec->shadow_ram[i].modified = FALSE;
1580 dev_spec->shadow_ram[i].value = 0xFFFF;
1581 }
1582
1509 goto out;
1510 }
1511
1512 /* Great! Everything worked, we can now clear the cached entries. */
1513 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1514 dev_spec->shadow_ram[i].modified = FALSE;
1515 dev_spec->shadow_ram[i].value = 0xFFFF;
1516 }
1517
1583 e1000_release_nvm(hw);
1518 nvm->ops.release(hw);
1584
1585 /*
1586 * Reload the EEPROM, or else modifications will not appear
1587 * until after the next adapter reset.
1588 */
1519
1520 /*
1521 * Reload the EEPROM, or else modifications will not appear
1522 * until after the next adapter reset.
1523 */
1589 e1000_reload_nvm(hw);
1524 nvm->ops.reload(hw);
1590 msec_delay(10);
1591
1592out:
1593 return ret_val;
1594}
1595
1596/**
1597 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1598 * @hw: pointer to the HW structure
1599 *
1600 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1601 * If the bit is 0, that the EEPROM had been modified, but the checksum was
1602 * not calculated, in which case we need to calculate the checksum and set
1603 * bit 6.
1604 **/
1525 msec_delay(10);
1526
1527out:
1528 return ret_val;
1529}
1530
1531/**
1532 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1533 * @hw: pointer to the HW structure
1534 *
1535 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1536 * If the bit is 0, that the EEPROM had been modified, but the checksum was
1537 * not calculated, in which case we need to calculate the checksum and set
1538 * bit 6.
1539 **/
1605STATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1540static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1606{
1607 s32 ret_val = E1000_SUCCESS;
1608 u16 data;
1609
1610 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
1611
1612 /*
1613 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1614 * needs to be fixed. This bit is an indication that the NVM
1615 * was prepared by OEM software and did not calculate the
1616 * checksum...a likely scenario.
1617 */
1541{
1542 s32 ret_val = E1000_SUCCESS;
1543 u16 data;
1544
1545 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
1546
1547 /*
1548 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1549 * needs to be fixed. This bit is an indication that the NVM
1550 * was prepared by OEM software and did not calculate the
1551 * checksum...a likely scenario.
1552 */
1618 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1553 ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data);
1619 if (ret_val)
1620 goto out;
1621
1622 if ((data & 0x40) == 0) {
1623 data |= 0x40;
1554 if (ret_val)
1555 goto out;
1556
1557 if ((data & 0x40) == 0) {
1558 data |= 0x40;
1624 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1559 ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data);
1625 if (ret_val)
1626 goto out;
1560 if (ret_val)
1561 goto out;
1627 ret_val = e1000_update_nvm_checksum(hw);
1562 ret_val = hw->nvm.ops.update(hw);
1628 if (ret_val)
1629 goto out;
1630 }
1631
1632 ret_val = e1000_validate_nvm_checksum_generic(hw);
1633
1634out:
1635 return ret_val;

--- 84 unchanged lines hidden (view full) ---

1720/**
1721 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1722 * @hw: pointer to the HW structure
1723 * @offset: The index of the byte to read.
1724 * @data: The byte to write to the NVM.
1725 *
1726 * Writes a single byte to the NVM using the flash access registers.
1727 **/
1563 if (ret_val)
1564 goto out;
1565 }
1566
1567 ret_val = e1000_validate_nvm_checksum_generic(hw);
1568
1569out:
1570 return ret_val;

--- 84 unchanged lines hidden (view full) ---

1655/**
1656 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1657 * @hw: pointer to the HW structure
1658 * @offset: The index of the byte to read.
1659 * @data: The byte to write to the NVM.
1660 *
1661 * Writes a single byte to the NVM using the flash access registers.
1662 **/
1728STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1663static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1729 u8 data)
1730{
1731 u16 word = (u16)data;
1732
1733 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
1734
1735 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1736}

--- 38 unchanged lines hidden (view full) ---

1775/**
1776 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1777 * @hw: pointer to the HW structure
1778 * @bank: 0 for first bank, 1 for second bank, etc.
1779 *
1780 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1781 * bank N is 4096 * N + flash_reg_addr.
1782 **/
1664 u8 data)
1665{
1666 u16 word = (u16)data;
1667
1668 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
1669
1670 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1671}

--- 38 unchanged lines hidden (view full) ---

1710/**
1711 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1712 * @hw: pointer to the HW structure
1713 * @bank: 0 for first bank, 1 for second bank, etc.
1714 *
1715 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1716 * bank N is 4096 * N + flash_reg_addr.
1717 **/
1783STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1718static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1784{
1785 struct e1000_nvm_info *nvm = &hw->nvm;
1786 union ich8_hws_flash_status hsfsts;
1787 union ich8_hws_flash_ctrl hsflctl;
1788 u32 flash_linear_addr;
1789 /* bank size is in 16bit words - adjust to bytes */
1790 u32 flash_bank_size = nvm->flash_bank_size * 2;
1791 s32 ret_val = E1000_SUCCESS;

--- 109 unchanged lines hidden (view full) ---

1901 * e1000_valid_led_default_ich8lan - Set the default LED settings
1902 * @hw: pointer to the HW structure
1903 * @data: Pointer to the LED settings
1904 *
1905 * Reads the LED default settings from the NVM to data. If the NVM LED
1906 * settings is all 0's or F's, set the LED default to a valid LED default
1907 * setting.
1908 **/
1719{
1720 struct e1000_nvm_info *nvm = &hw->nvm;
1721 union ich8_hws_flash_status hsfsts;
1722 union ich8_hws_flash_ctrl hsflctl;
1723 u32 flash_linear_addr;
1724 /* bank size is in 16bit words - adjust to bytes */
1725 u32 flash_bank_size = nvm->flash_bank_size * 2;
1726 s32 ret_val = E1000_SUCCESS;

--- 109 unchanged lines hidden (view full) ---

1836 * e1000_valid_led_default_ich8lan - Set the default LED settings
1837 * @hw: pointer to the HW structure
1838 * @data: Pointer to the LED settings
1839 *
1840 * Reads the LED default settings from the NVM to data. If the NVM LED
1841 * settings is all 0's or F's, set the LED default to a valid LED default
1842 * setting.
1843 **/
1909STATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1844static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1910{
1911 s32 ret_val;
1912
1913 DEBUGFUNC("e1000_valid_led_default_ich8lan");
1914
1845{
1846 s32 ret_val;
1847
1848 DEBUGFUNC("e1000_valid_led_default_ich8lan");
1849
1915 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1850 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1916 if (ret_val) {
1917 DEBUGOUT("NVM Read Error\n");
1918 goto out;
1919 }
1920
1921 if (*data == ID_LED_RESERVED_0000 ||
1922 *data == ID_LED_RESERVED_FFFF)
1923 *data = ID_LED_DEFAULT_ICH8LAN;

--- 4 unchanged lines hidden (view full) ---

1928
1929/**
1930 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1931 * @hw: pointer to the HW structure
1932 *
1933 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1934 * register, so the the bus width is hard coded.
1935 **/
1851 if (ret_val) {
1852 DEBUGOUT("NVM Read Error\n");
1853 goto out;
1854 }
1855
1856 if (*data == ID_LED_RESERVED_0000 ||
1857 *data == ID_LED_RESERVED_FFFF)
1858 *data = ID_LED_DEFAULT_ICH8LAN;

--- 4 unchanged lines hidden (view full) ---

1863
1864/**
1865 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1866 * @hw: pointer to the HW structure
1867 *
1868 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1869 * register, so the the bus width is hard coded.
1870 **/
1936STATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1871static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1937{
1938 struct e1000_bus_info *bus = &hw->bus;
1939 s32 ret_val;
1940
1941 DEBUGFUNC("e1000_get_bus_info_ich8lan");
1942
1943 ret_val = e1000_get_bus_info_pcie_generic(hw);
1944

--- 11 unchanged lines hidden (view full) ---

1956
1957/**
1958 * e1000_reset_hw_ich8lan - Reset the hardware
1959 * @hw: pointer to the HW structure
1960 *
1961 * Does a full reset of the hardware which includes a reset of the PHY and
1962 * MAC.
1963 **/
1872{
1873 struct e1000_bus_info *bus = &hw->bus;
1874 s32 ret_val;
1875
1876 DEBUGFUNC("e1000_get_bus_info_ich8lan");
1877
1878 ret_val = e1000_get_bus_info_pcie_generic(hw);
1879

--- 11 unchanged lines hidden (view full) ---

1891
1892/**
1893 * e1000_reset_hw_ich8lan - Reset the hardware
1894 * @hw: pointer to the HW structure
1895 *
1896 * Does a full reset of the hardware which includes a reset of the PHY and
1897 * MAC.
1898 **/
1964STATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1899static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1965{
1966 u32 ctrl, icr, kab;
1967 s32 ret_val;
1968
1969 DEBUGFUNC("e1000_reset_hw_ich8lan");
1970
1971 /*
1972 * Prevent the PCI-E bus from sticking if there is no TLP connection

--- 23 unchanged lines hidden (view full) ---

1996 /* Set Tx and Rx buffer allocation to 8k apiece. */
1997 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
1998 /* Set Packet Buffer Size to 16k. */
1999 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
2000 }
2001
2002 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2003
1900{
1901 u32 ctrl, icr, kab;
1902 s32 ret_val;
1903
1904 DEBUGFUNC("e1000_reset_hw_ich8lan");
1905
1906 /*
1907 * Prevent the PCI-E bus from sticking if there is no TLP connection

--- 23 unchanged lines hidden (view full) ---

1931 /* Set Tx and Rx buffer allocation to 8k apiece. */
1932 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
1933 /* Set Packet Buffer Size to 16k. */
1934 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
1935 }
1936
1937 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1938
2004 if (!e1000_check_reset_block(hw) && !hw->phy.reset_disable) {
1939 if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) {
2005 /*
2006 * PHY HW reset requires MAC CORE reset at the same
2007 * time to make sure the interface between MAC and the
2008 * external PHY is reset.
2009 */
2010 ctrl |= E1000_CTRL_PHY_RST;
2011 }
2012 ret_val = e1000_acquire_swflag_ich8lan(hw);

--- 28 unchanged lines hidden (view full) ---

2041 * Prepares the hardware for transmit and receive by doing the following:
2042 * - initialize hardware bits
2043 * - initialize LED identification
2044 * - setup receive address registers
2045 * - setup flow control
2046 * - setup transmit descriptors
2047 * - clear statistics
2048 **/
1940 /*
1941 * PHY HW reset requires MAC CORE reset at the same
1942 * time to make sure the interface between MAC and the
1943 * external PHY is reset.
1944 */
1945 ctrl |= E1000_CTRL_PHY_RST;
1946 }
1947 ret_val = e1000_acquire_swflag_ich8lan(hw);

--- 28 unchanged lines hidden (view full) ---

1976 * Prepares the hardware for transmit and receive by doing the following:
1977 * - initialize hardware bits
1978 * - initialize LED identification
1979 * - setup receive address registers
1980 * - setup flow control
1981 * - setup transmit descriptors
1982 * - clear statistics
1983 **/
2049STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1984static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2050{
2051 struct e1000_mac_info *mac = &hw->mac;
2052 u32 ctrl_ext, txdctl, snoop;
2053 s32 ret_val;
2054 u16 i;
2055
2056 DEBUGFUNC("e1000_init_hw_ich8lan");
2057

--- 10 unchanged lines hidden (view full) ---

2068 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
2069
2070 /* Zero out the Multicast HASH table */
2071 DEBUGOUT("Zeroing the MTA\n");
2072 for (i = 0; i < mac->mta_reg_count; i++)
2073 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2074
2075 /* Setup link and flow control */
1985{
1986 struct e1000_mac_info *mac = &hw->mac;
1987 u32 ctrl_ext, txdctl, snoop;
1988 s32 ret_val;
1989 u16 i;
1990
1991 DEBUGFUNC("e1000_init_hw_ich8lan");
1992

--- 10 unchanged lines hidden (view full) ---

2003 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
2004
2005 /* Zero out the Multicast HASH table */
2006 DEBUGOUT("Zeroing the MTA\n");
2007 for (i = 0; i < mac->mta_reg_count; i++)
2008 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2009
2010 /* Setup link and flow control */
2076 ret_val = e1000_setup_link(hw);
2011 ret_val = mac->ops.setup_link(hw);
2077
2078 /* Set the transmit descriptor write-back policy for both queues */
2079 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
2080 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2081 E1000_TXDCTL_FULL_TX_DESC_WB;
2082 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2083 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2084 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);

--- 91 unchanged lines hidden (view full) ---

2176 * @hw: pointer to the HW structure
2177 *
2178 * Determines which flow control settings to use, then configures flow
2179 * control. Calls the appropriate media-specific link configuration
2180 * function. Assuming the adapter has a valid link partner, a valid link
2181 * should be established. Assumes the hardware has previously been reset
2182 * and the transmitter and receiver are not enabled.
2183 **/
2012
2013 /* Set the transmit descriptor write-back policy for both queues */
2014 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
2015 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2016 E1000_TXDCTL_FULL_TX_DESC_WB;
2017 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2018 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2019 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);

--- 91 unchanged lines hidden (view full) ---

2111 * @hw: pointer to the HW structure
2112 *
2113 * Determines which flow control settings to use, then configures flow
2114 * control. Calls the appropriate media-specific link configuration
2115 * function. Assuming the adapter has a valid link partner, a valid link
2116 * should be established. Assumes the hardware has previously been reset
2117 * and the transmitter and receiver are not enabled.
2118 **/
2184STATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2119static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2185{
2120{
2186 struct e1000_functions *func = &hw->func;
2187 s32 ret_val = E1000_SUCCESS;
2188
2189 DEBUGFUNC("e1000_setup_link_ich8lan");
2190
2121 s32 ret_val = E1000_SUCCESS;
2122
2123 DEBUGFUNC("e1000_setup_link_ich8lan");
2124
2191 if (e1000_check_reset_block(hw))
2125 if (hw->phy.ops.check_reset_block(hw))
2192 goto out;
2193
2194 /*
2195 * ICH parts do not have a word in the NVM to determine
2196 * the default flow control setting, so we explicitly
2197 * set it to full.
2198 */
2199 if (hw->fc.type == e1000_fc_default)
2200 hw->fc.type = e1000_fc_full;
2201
2202 hw->fc.original_type = hw->fc.type;
2203
2204 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type);
2205
2206 /* Continue to configure the copper link. */
2126 goto out;
2127
2128 /*
2129 * ICH parts do not have a word in the NVM to determine
2130 * the default flow control setting, so we explicitly
2131 * set it to full.
2132 */
2133 if (hw->fc.type == e1000_fc_default)
2134 hw->fc.type = e1000_fc_full;
2135
2136 hw->fc.original_type = hw->fc.type;
2137
2138 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type);
2139
2140 /* Continue to configure the copper link. */
2207 ret_val = func->setup_physical_interface(hw);
2141 ret_val = hw->mac.ops.setup_physical_interface(hw);
2208 if (ret_val)
2209 goto out;
2210
2211 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
2212
2213 ret_val = e1000_set_fc_watermarks_generic(hw);
2214
2215out:
2216 return ret_val;
2217}
2218
2219/**
2220 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2221 * @hw: pointer to the HW structure
2222 *
2223 * Configures the kumeran interface to the PHY to wait the appropriate time
2224 * when polling the PHY, then call the generic setup_copper_link to finish
2225 * configuring the copper link.
2226 **/
2142 if (ret_val)
2143 goto out;
2144
2145 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
2146
2147 ret_val = e1000_set_fc_watermarks_generic(hw);
2148
2149out:
2150 return ret_val;
2151}
2152
2153/**
2154 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2155 * @hw: pointer to the HW structure
2156 *
2157 * Configures the kumeran interface to the PHY to wait the appropriate time
2158 * when polling the PHY, then call the generic setup_copper_link to finish
2159 * configuring the copper link.
2160 **/
2227STATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2161static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2228{
2229 u32 ctrl;
2230 s32 ret_val;
2231 u16 reg_data;
2232
2233 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
2234
2235 ctrl = E1000_READ_REG(hw, E1000_CTRL);

--- 23 unchanged lines hidden (view full) ---

2259 goto out;
2260 } else if (hw->phy.type == e1000_phy_bm) {
2261 ret_val = e1000_copper_link_setup_m88(hw);
2262 if (ret_val)
2263 goto out;
2264 }
2265
2266 if (hw->phy.type == e1000_phy_ife) {
2162{
2163 u32 ctrl;
2164 s32 ret_val;
2165 u16 reg_data;
2166
2167 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
2168
2169 ctrl = E1000_READ_REG(hw, E1000_CTRL);

--- 23 unchanged lines hidden (view full) ---

2193 goto out;
2194 } else if (hw->phy.type == e1000_phy_bm) {
2195 ret_val = e1000_copper_link_setup_m88(hw);
2196 if (ret_val)
2197 goto out;
2198 }
2199
2200 if (hw->phy.type == e1000_phy_ife) {
2267 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
2201 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2202 &reg_data);
2268 if (ret_val)
2269 goto out;
2270
2271 reg_data &= ~IFE_PMC_AUTO_MDIX;
2272
2273 switch (hw->phy.mdix) {
2274 case 1:
2275 reg_data &= ~IFE_PMC_FORCE_MDIX;
2276 break;
2277 case 2:
2278 reg_data |= IFE_PMC_FORCE_MDIX;
2279 break;
2280 case 0:
2281 default:
2282 reg_data |= IFE_PMC_AUTO_MDIX;
2283 break;
2284 }
2203 if (ret_val)
2204 goto out;
2205
2206 reg_data &= ~IFE_PMC_AUTO_MDIX;
2207
2208 switch (hw->phy.mdix) {
2209 case 1:
2210 reg_data &= ~IFE_PMC_FORCE_MDIX;
2211 break;
2212 case 2:
2213 reg_data |= IFE_PMC_FORCE_MDIX;
2214 break;
2215 case 0:
2216 default:
2217 reg_data |= IFE_PMC_AUTO_MDIX;
2218 break;
2219 }
2285 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, reg_data);
2220 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2221 reg_data);
2286 if (ret_val)
2287 goto out;
2288 }
2289 ret_val = e1000_setup_copper_link_generic(hw);
2290
2291out:
2292 return ret_val;
2293}
2294
2295/**
2296 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2297 * @hw: pointer to the HW structure
2298 * @speed: pointer to store current link speed
2299 * @duplex: pointer to store the current link duplex
2300 *
2301 * Calls the generic get_speed_and_duplex to retrieve the current link
2302 * information and then calls the Kumeran lock loss workaround for links at
2303 * gigabit speeds.
2304 **/
2222 if (ret_val)
2223 goto out;
2224 }
2225 ret_val = e1000_setup_copper_link_generic(hw);
2226
2227out:
2228 return ret_val;
2229}
2230
2231/**
2232 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2233 * @hw: pointer to the HW structure
2234 * @speed: pointer to store current link speed
2235 * @duplex: pointer to store the current link duplex
2236 *
2237 * Calls the generic get_speed_and_duplex to retrieve the current link
2238 * information and then calls the Kumeran lock loss workaround for links at
2239 * gigabit speeds.
2240 **/
2305STATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2241static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2306 u16 *duplex)
2307{
2308 s32 ret_val;
2309
2310 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
2311
2312 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
2313 if (ret_val)

--- 53 unchanged lines hidden (view full) ---

2367 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2368 if (!link) {
2369 ret_val = E1000_SUCCESS;
2370 goto out;
2371 }
2372
2373 for (i = 0; i < 10; i++) {
2374 /* read once to clear */
2242 u16 *duplex)
2243{
2244 s32 ret_val;
2245
2246 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
2247
2248 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
2249 if (ret_val)

--- 53 unchanged lines hidden (view full) ---

2303 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2304 if (!link) {
2305 ret_val = E1000_SUCCESS;
2306 goto out;
2307 }
2308
2309 for (i = 0; i < 10; i++) {
2310 /* read once to clear */
2375 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &data);
2311 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
2376 if (ret_val)
2377 goto out;
2378 /* and again to get new status */
2312 if (ret_val)
2313 goto out;
2314 /* and again to get new status */
2379 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &data);
2315 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
2380 if (ret_val)
2381 goto out;
2382
2383 /* check for PCS lock */
2384 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) {
2385 ret_val = E1000_SUCCESS;
2386 goto out;
2387 }
2388
2389 /* Issue PHY reset */
2316 if (ret_val)
2317 goto out;
2318
2319 /* check for PCS lock */
2320 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) {
2321 ret_val = E1000_SUCCESS;
2322 goto out;
2323 }
2324
2325 /* Issue PHY reset */
2390 e1000_phy_hw_reset(hw);
2326 hw->phy.ops.reset(hw);
2391 msec_delay_irq(5);
2392 }
2393 /* Disable GigE link negotiation */
2394 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2395 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2396 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2397 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2398

--- 75 unchanged lines hidden (view full) ---

2474 /*
2475 * Call gig speed drop workaround on Gig disable before
2476 * accessing any PHY registers
2477 */
2478 if (hw->mac.type == e1000_ich8lan)
2479 e1000_gig_downshift_workaround_ich8lan(hw);
2480
2481 /* Write VR power-down enable */
2327 msec_delay_irq(5);
2328 }
2329 /* Disable GigE link negotiation */
2330 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2331 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2332 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2333 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2334

--- 75 unchanged lines hidden (view full) ---

2410 /*
2411 * Call gig speed drop workaround on Gig disable before
2412 * accessing any PHY registers
2413 */
2414 if (hw->mac.type == e1000_ich8lan)
2415 e1000_gig_downshift_workaround_ich8lan(hw);
2416
2417 /* Write VR power-down enable */
2482 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data);
2418 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
2483 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2419 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2484 e1000_write_phy_reg(hw,
2420 hw->phy.ops.write_reg(hw,
2485 IGP3_VR_CTRL,
2486 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2487
2488 /* Read it back and test */
2421 IGP3_VR_CTRL,
2422 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2423
2424 /* Read it back and test */
2489 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &data);
2425 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
2490 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2491 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2492 break;
2493
2494 /* Issue PHY reset and repeat at most one more time */
2495 reg = E1000_READ_REG(hw, E1000_CTRL);
2496 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
2497 retry++;

--- 44 unchanged lines hidden (view full) ---

2542 * e1000_disable_gig_wol_ich8lan - disable gig during WoL
2543 * @hw: pointer to the HW structure
2544 *
2545 * During S0 to Sx transition, it is possible the link remains at gig
2546 * instead of negotiating to a lower speed. Before going to Sx, set
2547 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2548 * to a lower speed.
2549 *
2426 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2427 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2428 break;
2429
2430 /* Issue PHY reset and repeat at most one more time */
2431 reg = E1000_READ_REG(hw, E1000_CTRL);
2432 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
2433 retry++;

--- 44 unchanged lines hidden (view full) ---

2478 * e1000_disable_gig_wol_ich8lan - disable gig during WoL
2479 * @hw: pointer to the HW structure
2480 *
2481 * During S0 to Sx transition, it is possible the link remains at gig
2482 * instead of negotiating to a lower speed. Before going to Sx, set
2483 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2484 * to a lower speed.
2485 *
2550 * Should only be called for ICH9m and ICH10 devices.
2486 * Should only be called for ICH9.
2551 **/
2552void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2553{
2554 u32 phy_ctrl;
2555
2487 **/
2488void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2489{
2490 u32 phy_ctrl;
2491
2556 if ((hw->mac.type == e1000_ich10lan) ||
2557 ((hw->mac.type == e1000_ich9lan) &&
2558 ((hw->device_id == E1000_DEV_ID_ICH9_IGP_M) ||
2559 (hw->device_id == E1000_DEV_ID_ICH9_IGP_M_AMT)))) {
2492 if (hw->mac.type == e1000_ich9lan) {
2560 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2561 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2562 E1000_PHY_CTRL_GBE_DISABLE;
2563 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2564 }
2565
2566 return;
2567}
2568
2569/**
2570 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2571 * @hw: pointer to the HW structure
2572 *
2573 * Return the LED back to the default configuration.
2574 **/
2493 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2494 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2495 E1000_PHY_CTRL_GBE_DISABLE;
2496 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2497 }
2498
2499 return;
2500}
2501
2502/**
2503 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2504 * @hw: pointer to the HW structure
2505 *
2506 * Return the LED back to the default configuration.
2507 **/
2575STATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2508static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2576{
2577 s32 ret_val = E1000_SUCCESS;
2578
2579 DEBUGFUNC("e1000_cleanup_led_ich8lan");
2580
2581 if (hw->phy.type == e1000_phy_ife)
2509{
2510 s32 ret_val = E1000_SUCCESS;
2511
2512 DEBUGFUNC("e1000_cleanup_led_ich8lan");
2513
2514 if (hw->phy.type == e1000_phy_ife)
2582 ret_val = e1000_write_phy_reg(hw,
2515 ret_val = hw->phy.ops.write_reg(hw,
2583 IFE_PHY_SPECIAL_CONTROL_LED,
2584 0);
2585 else
2586 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
2587
2588 return ret_val;
2589}
2590
2591/**
2592 * e1000_led_on_ich8lan - Turn LEDs on
2593 * @hw: pointer to the HW structure
2594 *
2595 * Turn on the LEDs.
2596 **/
2516 IFE_PHY_SPECIAL_CONTROL_LED,
2517 0);
2518 else
2519 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
2520
2521 return ret_val;
2522}
2523
2524/**
2525 * e1000_led_on_ich8lan - Turn LEDs on
2526 * @hw: pointer to the HW structure
2527 *
2528 * Turn on the LEDs.
2529 **/
2597STATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2530static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2598{
2599 s32 ret_val = E1000_SUCCESS;
2600
2601 DEBUGFUNC("e1000_led_on_ich8lan");
2602
2603 if (hw->phy.type == e1000_phy_ife)
2531{
2532 s32 ret_val = E1000_SUCCESS;
2533
2534 DEBUGFUNC("e1000_led_on_ich8lan");
2535
2536 if (hw->phy.type == e1000_phy_ife)
2604 ret_val = e1000_write_phy_reg(hw,
2537 ret_val = hw->phy.ops.write_reg(hw,
2605 IFE_PHY_SPECIAL_CONTROL_LED,
2606 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2607 else
2608 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
2609
2610 return ret_val;
2611}
2612
2613/**
2614 * e1000_led_off_ich8lan - Turn LEDs off
2615 * @hw: pointer to the HW structure
2616 *
2617 * Turn off the LEDs.
2618 **/
2538 IFE_PHY_SPECIAL_CONTROL_LED,
2539 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2540 else
2541 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
2542
2543 return ret_val;
2544}
2545
2546/**
2547 * e1000_led_off_ich8lan - Turn LEDs off
2548 * @hw: pointer to the HW structure
2549 *
2550 * Turn off the LEDs.
2551 **/
2619STATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2552static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2620{
2621 s32 ret_val = E1000_SUCCESS;
2622
2623 DEBUGFUNC("e1000_led_off_ich8lan");
2624
2625 if (hw->phy.type == e1000_phy_ife)
2553{
2554 s32 ret_val = E1000_SUCCESS;
2555
2556 DEBUGFUNC("e1000_led_off_ich8lan");
2557
2558 if (hw->phy.type == e1000_phy_ife)
2626 ret_val = e1000_write_phy_reg(hw,
2559 ret_val = hw->phy.ops.write_reg(hw,
2627 IFE_PHY_SPECIAL_CONTROL_LED,
2628 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2629 else
2630 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2631
2632 return ret_val;
2633}
2634
2635/**
2636 * e1000_get_cfg_done_ich8lan - Read config done bit
2637 * @hw: pointer to the HW structure
2638 *
2639 * Read the management control register for the config done bit for
2640 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2641 * to read the config done bit, so an error is *ONLY* logged and returns
2642 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
2643 * would not be able to be reset or change link.
2644 **/
2560 IFE_PHY_SPECIAL_CONTROL_LED,
2561 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2562 else
2563 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2564
2565 return ret_val;
2566}
2567
2568/**
2569 * e1000_get_cfg_done_ich8lan - Read config done bit
2570 * @hw: pointer to the HW structure
2571 *
2572 * Read the management control register for the config done bit for
2573 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2574 * to read the config done bit, so an error is *ONLY* logged and returns
2575 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
2576 * would not be able to be reset or change link.
2577 **/
2645STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2578static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2646{
2647 s32 ret_val = E1000_SUCCESS;
2579{
2580 s32 ret_val = E1000_SUCCESS;
2648 u32 bank = 0;
2649
2650 e1000_get_cfg_done_generic(hw);
2651
2652 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2581
2582 e1000_get_cfg_done_generic(hw);
2583
2584 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2653 if (hw->mac.type != e1000_ich10lan) {
2654 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
2655 (hw->phy.type == e1000_phy_igp_3)) {
2656 e1000_phy_init_script_igp3(hw);
2657 }
2658 } else {
2659 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
2660 /* Maybe we should do a basic Boazman config */
2661 DEBUGOUT("EEPROM not present\n");
2662 ret_val = -E1000_ERR_CONFIG;
2663 }
2585 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
2586 (hw->phy.type == e1000_phy_igp_3)) {
2587 e1000_phy_init_script_igp3(hw);
2664 }
2665
2666 return ret_val;
2667}
2668
2669/**
2670 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
2671 * @hw: pointer to the HW structure
2672 *
2673 * In the case of a PHY power down to save power, or to turn off link during a
2674 * driver unload, or wake on lan is not enabled, remove the link.
2675 **/
2588 }
2589
2590 return ret_val;
2591}
2592
2593/**
2594 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
2595 * @hw: pointer to the HW structure
2596 *
2597 * In the case of a PHY power down to save power, or to turn off link during a
2598 * driver unload, or wake on lan is not enabled, remove the link.
2599 **/
2676STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
2600static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
2677{
2601{
2602 struct e1000_phy_info *phy = &hw->phy;
2603 struct e1000_mac_info *mac = &hw->mac;
2604
2678 /* If the management interface is not enabled, then power down */
2605 /* If the management interface is not enabled, then power down */
2679 if (!(e1000_check_mng_mode(hw) || e1000_check_reset_block(hw)))
2606 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
2680 e1000_power_down_phy_copper(hw);
2681
2682 return;
2683}
2684
2685/**
2686 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2687 * @hw: pointer to the HW structure
2688 *
2689 * Clears hardware counters specific to the silicon family and calls
2690 * clear_hw_cntrs_generic to clear all general purpose counters.
2691 **/
2607 e1000_power_down_phy_copper(hw);
2608
2609 return;
2610}
2611
2612/**
2613 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2614 * @hw: pointer to the HW structure
2615 *
2616 * Clears hardware counters specific to the silicon family and calls
2617 * clear_hw_cntrs_generic to clear all general purpose counters.
2618 **/
2692STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2619static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2693{
2694 volatile u32 temp;
2695
2696 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
2697
2698 e1000_clear_hw_cntrs_base_generic(hw);
2699
2700 temp = E1000_READ_REG(hw, E1000_ALGNERRC);

--- 14 unchanged lines hidden --- 		2620{
2621 volatile u32 temp;
2622
2623 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
2624
2625 e1000_clear_hw_cntrs_base_generic(hw);
2626
2627 temp = E1000_READ_REG(hw, E1000_ALGNERRC);

--- 14 unchanged lines hidden ---