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e1000_hw.h (190872) e1000_hw.h (194865)
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_hw.h 190872 2009-04-10 00:05:46Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_hw.h 194865 2009-06-24 17:41:29Z jfv $*/
34
35#ifndef _E1000_HW_H_
36#define _E1000_HW_H_
37
38#include "e1000_osdep.h"
39#include "e1000_regs.h"
40#include "e1000_defines.h"
41

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90#define E1000_DEV_ID_82572EI_FIBER 0x107E
91#define E1000_DEV_ID_82572EI_SERDES 0x107F
92#define E1000_DEV_ID_82572EI 0x10B9
93#define E1000_DEV_ID_82573E 0x108B
94#define E1000_DEV_ID_82573E_IAMT 0x108C
95#define E1000_DEV_ID_82573L 0x109A
96#define E1000_DEV_ID_82574L 0x10D3
97#define E1000_DEV_ID_82574LA 0x10F6
34
35#ifndef _E1000_HW_H_
36#define _E1000_HW_H_
37
38#include "e1000_osdep.h"
39#include "e1000_regs.h"
40#include "e1000_defines.h"
41

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90#define E1000_DEV_ID_82572EI_FIBER 0x107E
91#define E1000_DEV_ID_82572EI_SERDES 0x107F
92#define E1000_DEV_ID_82572EI 0x10B9
93#define E1000_DEV_ID_82573E 0x108B
94#define E1000_DEV_ID_82573E_IAMT 0x108C
95#define E1000_DEV_ID_82573L 0x109A
96#define E1000_DEV_ID_82574L 0x10D3
97#define E1000_DEV_ID_82574LA 0x10F6
98#define E1000_DEV_ID_82583V 0x150C
98#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
99#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
100#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
101#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
102#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
103#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
104#define E1000_DEV_ID_ICH8_IGP_C 0x104B
105#define E1000_DEV_ID_ICH8_IFE 0x104C

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115#define E1000_DEV_ID_ICH9_IFE 0x10C0
116#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
117#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
118#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
119#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
120#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
121#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
122#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
99#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
100#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
101#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
102#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
103#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
104#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
105#define E1000_DEV_ID_ICH8_IGP_C 0x104B
106#define E1000_DEV_ID_ICH8_IFE 0x104C

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116#define E1000_DEV_ID_ICH9_IFE 0x10C0
117#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
118#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
119#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
120#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
121#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
122#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
123#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
124#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
125#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
126#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
127#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
123#define E1000_DEV_ID_82576 0x10C9
124#define E1000_DEV_ID_82576_FIBER 0x10E6
125#define E1000_DEV_ID_82576_SERDES 0x10E7
126#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
127#define E1000_DEV_ID_82576_NS 0x150A
128#define E1000_DEV_ID_82576 0x10C9
129#define E1000_DEV_ID_82576_FIBER 0x10E6
130#define E1000_DEV_ID_82576_SERDES 0x10E7
131#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
132#define E1000_DEV_ID_82576_NS 0x150A
133#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
128#define E1000_DEV_ID_82575EB_COPPER 0x10A7
129#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
130#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
131#define E1000_DEV_ID_82575GB_QUAD_COPPER_PM 0x10E2
132#define E1000_REVISION_0 0
133#define E1000_REVISION_1 1
134#define E1000_REVISION_2 2
135#define E1000_REVISION_3 3

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154 e1000_82541,
155 e1000_82541_rev_2,
156 e1000_82547,
157 e1000_82547_rev_2,
158 e1000_82571,
159 e1000_82572,
160 e1000_82573,
161 e1000_82574,
134#define E1000_DEV_ID_82575EB_COPPER 0x10A7
135#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
136#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
137#define E1000_DEV_ID_82575GB_QUAD_COPPER_PM 0x10E2
138#define E1000_REVISION_0 0
139#define E1000_REVISION_1 1
140#define E1000_REVISION_2 2
141#define E1000_REVISION_3 3

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160 e1000_82541,
161 e1000_82541_rev_2,
162 e1000_82547,
163 e1000_82547_rev_2,
164 e1000_82571,
165 e1000_82572,
166 e1000_82573,
167 e1000_82574,
168 e1000_82583,
162 e1000_80003es2lan,
163 e1000_ich8lan,
164 e1000_ich9lan,
165 e1000_ich10lan,
169 e1000_80003es2lan,
170 e1000_ich8lan,
171 e1000_ich9lan,
172 e1000_ich10lan,
173 e1000_pchlan,
166 e1000_82575,
167 e1000_82576,
168 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
169};
170
171enum e1000_media_type {
172 e1000_media_type_unknown = 0,
173 e1000_media_type_copper = 1,

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198 e1000_phy_none,
199 e1000_phy_m88,
200 e1000_phy_igp,
201 e1000_phy_igp_2,
202 e1000_phy_gg82563,
203 e1000_phy_igp_3,
204 e1000_phy_ife,
205 e1000_phy_bm,
174 e1000_82575,
175 e1000_82576,
176 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
177};
178
179enum e1000_media_type {
180 e1000_media_type_unknown = 0,
181 e1000_media_type_copper = 1,

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206 e1000_phy_none,
207 e1000_phy_m88,
208 e1000_phy_igp,
209 e1000_phy_igp_2,
210 e1000_phy_gg82563,
211 e1000_phy_igp_3,
212 e1000_phy_ife,
213 e1000_phy_bm,
214 e1000_phy_82578,
215 e1000_phy_82577,
206 e1000_phy_vf,
207};
208
209enum e1000_bus_type {
210 e1000_bus_type_unknown = 0,
211 e1000_bus_type_pci,
212 e1000_bus_type_pcix,
213 e1000_bus_type_pci_express,

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642 u32 txcw;
643
644 u16 current_ifs_val;
645 u16 ifs_max_val;
646 u16 ifs_min_val;
647 u16 ifs_ratio;
648 u16 ifs_step_size;
649 u16 mta_reg_count;
216 e1000_phy_vf,
217};
218
219enum e1000_bus_type {
220 e1000_bus_type_unknown = 0,
221 e1000_bus_type_pci,
222 e1000_bus_type_pcix,
223 e1000_bus_type_pci_express,

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652 u32 txcw;
653
654 u16 current_ifs_val;
655 u16 ifs_max_val;
656 u16 ifs_min_val;
657 u16 ifs_ratio;
658 u16 ifs_step_size;
659 u16 mta_reg_count;
650#define MAX_MTA_REG 128 /* this must be the maximum size of the MTA register
651 * table in all supported adapters
652 */
660
661 /* Maximum size of the MTA register table in all supported adapters */
662 #define MAX_MTA_REG 128
653 u32 mta_shadow[MAX_MTA_REG];
654 u16 rar_entry_count;
655
656 u8 forced_speed_duplex;
657
658 bool adaptive_ifs;
659 bool arc_subsystem_valid;
660 bool asf_firmware_present;

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750struct e1000_dev_spec_82543 {
751 u32 tbi_compatibility;
752 bool dma_fairness;
753 bool init_phy_disabled;
754};
755
756struct e1000_dev_spec_82571 {
757 bool laa_is_present;
663 u32 mta_shadow[MAX_MTA_REG];
664 u16 rar_entry_count;
665
666 u8 forced_speed_duplex;
667
668 bool adaptive_ifs;
669 bool arc_subsystem_valid;
670 bool asf_firmware_present;

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760struct e1000_dev_spec_82543 {
761 u32 tbi_compatibility;
762 bool dma_fairness;
763 bool init_phy_disabled;
764};
765
766struct e1000_dev_spec_82571 {
767 bool laa_is_present;
768 u32 smb_counter;
758};
759
760struct e1000_shadow_ram {
761 u16 value;
762 bool modified;
763};
764
765#define E1000_SHADOW_RAM_WORDS 2048

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818#include "e1000_80003es2lan.h"
819#include "e1000_ich8lan.h"
820#include "e1000_82575.h"
821
822/* These functions must be implemented by drivers */
823void e1000_pci_clear_mwi(struct e1000_hw *hw);
824void e1000_pci_set_mwi(struct e1000_hw *hw);
825s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
769};
770
771struct e1000_shadow_ram {
772 u16 value;
773 bool modified;
774};
775
776#define E1000_SHADOW_RAM_WORDS 2048

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829#include "e1000_80003es2lan.h"
830#include "e1000_ich8lan.h"
831#include "e1000_82575.h"
832
833/* These functions must be implemented by drivers */
834void e1000_pci_clear_mwi(struct e1000_hw *hw);
835void e1000_pci_set_mwi(struct e1000_hw *hw);
836s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
837s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
826void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
827void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
828
829#endif
838void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
839void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
840
841#endif