1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
| 1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
|
89#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
90#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
91#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
92#define E1000_DEV_ID_82572EI_COPPER 0x107D
93#define E1000_DEV_ID_82572EI_FIBER 0x107E
94#define E1000_DEV_ID_82572EI_SERDES 0x107F
95#define E1000_DEV_ID_82572EI 0x10B9
96#define E1000_DEV_ID_82573E 0x108B
97#define E1000_DEV_ID_82573E_IAMT 0x108C
98#define E1000_DEV_ID_82573L 0x109A
99#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
100#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
101#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
102#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
103#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
104#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
105#define E1000_DEV_ID_ICH8_IGP_C 0x104B
106#define E1000_DEV_ID_ICH8_IFE 0x104C
107#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
108#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
109#define E1000_DEV_ID_ICH8_IGP_M 0x104D
110#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
111#define E1000_DEV_ID_ICH9_IGP_C 0x294C
112#define E1000_DEV_ID_ICH9_IFE 0x10C0
113#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
114#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
115#define E1000_DEV_ID_82575EB_COPPER 0x10A7
116#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
117#define E1000_DEV_ID_82575EM_COPPER 0x10AA
118#define E1000_DEV_ID_82575EM_FIBER_SERDES 0x10AC
119#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
120
121#define E1000_REVISION_0 0
122#define E1000_REVISION_1 1
123#define E1000_REVISION_2 2
124#define E1000_REVISION_3 3
125#define E1000_REVISION_4 4
126
127#define E1000_FUNC_0 0
128#define E1000_FUNC_1 1
129
130typedef enum {
131 e1000_undefined = 0,
132#ifndef NO_82542_SUPPORT
133 e1000_82542,
134#endif
135 e1000_82543,
136 e1000_82544,
137 e1000_82540,
138 e1000_82545,
139 e1000_82545_rev_3,
140 e1000_82546,
141 e1000_82546_rev_3,
142 e1000_82541,
143 e1000_82541_rev_2,
144 e1000_82547,
145 e1000_82547_rev_2,
146 e1000_82571,
147 e1000_82572,
148 e1000_82573,
149 e1000_80003es2lan,
150 e1000_ich8lan,
151 e1000_ich9lan,
152 e1000_82575,
| 88#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
89#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
90#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
91#define E1000_DEV_ID_82572EI_COPPER 0x107D
92#define E1000_DEV_ID_82572EI_FIBER 0x107E
93#define E1000_DEV_ID_82572EI_SERDES 0x107F
94#define E1000_DEV_ID_82572EI 0x10B9
95#define E1000_DEV_ID_82573E 0x108B
96#define E1000_DEV_ID_82573E_IAMT 0x108C
97#define E1000_DEV_ID_82573L 0x109A
98#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
99#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
100#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
101#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
102#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
103#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
104#define E1000_DEV_ID_ICH8_IGP_C 0x104B
105#define E1000_DEV_ID_ICH8_IFE 0x104C
106#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
107#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
108#define E1000_DEV_ID_ICH8_IGP_M 0x104D
109#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
110#define E1000_DEV_ID_ICH9_IGP_C 0x294C
111#define E1000_DEV_ID_ICH9_IFE 0x10C0
112#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
113#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
114#define E1000_DEV_ID_82575EB_COPPER 0x10A7
115#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
116#define E1000_DEV_ID_82575EM_COPPER 0x10AA
117#define E1000_DEV_ID_82575EM_FIBER_SERDES 0x10AC
118#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
119
120#define E1000_REVISION_0 0
121#define E1000_REVISION_1 1
122#define E1000_REVISION_2 2
123#define E1000_REVISION_3 3
124#define E1000_REVISION_4 4
125
126#define E1000_FUNC_0 0
127#define E1000_FUNC_1 1
128
129typedef enum {
130 e1000_undefined = 0,
131#ifndef NO_82542_SUPPORT
132 e1000_82542,
133#endif
134 e1000_82543,
135 e1000_82544,
136 e1000_82540,
137 e1000_82545,
138 e1000_82545_rev_3,
139 e1000_82546,
140 e1000_82546_rev_3,
141 e1000_82541,
142 e1000_82541_rev_2,
143 e1000_82547,
144 e1000_82547_rev_2,
145 e1000_82571,
146 e1000_82572,
147 e1000_82573,
148 e1000_80003es2lan,
149 e1000_ich8lan,
150 e1000_ich9lan,
151 e1000_82575,
|
154} e1000_mac_type;
155
156typedef enum {
157 e1000_media_type_unknown = 0,
158 e1000_media_type_copper = 1,
159 e1000_media_type_fiber = 2,
160 e1000_media_type_internal_serdes = 3,
161 e1000_num_media_types
162} e1000_media_type;
163
164typedef enum {
165 e1000_nvm_unknown = 0,
166 e1000_nvm_none,
167 e1000_nvm_eeprom_spi,
168 e1000_nvm_eeprom_microwire,
169 e1000_nvm_flash_hw,
170 e1000_nvm_flash_sw
171} e1000_nvm_type;
172
173typedef enum {
174 e1000_nvm_override_none = 0,
175 e1000_nvm_override_spi_small,
176 e1000_nvm_override_spi_large,
177 e1000_nvm_override_microwire_small,
178 e1000_nvm_override_microwire_large
179} e1000_nvm_override;
180
181typedef enum {
182 e1000_phy_unknown = 0,
183 e1000_phy_none,
184 e1000_phy_m88,
185 e1000_phy_igp,
186 e1000_phy_igp_2,
187 e1000_phy_gg82563,
188 e1000_phy_igp_3,
189 e1000_phy_ife,
190} e1000_phy_type;
191
192typedef enum {
193 e1000_bus_type_unknown = 0,
194 e1000_bus_type_pci,
195 e1000_bus_type_pcix,
196 e1000_bus_type_pci_express,
197 e1000_bus_type_reserved
198} e1000_bus_type;
199
200typedef enum {
201 e1000_bus_speed_unknown = 0,
202 e1000_bus_speed_33,
203 e1000_bus_speed_66,
204 e1000_bus_speed_100,
205 e1000_bus_speed_120,
206 e1000_bus_speed_133,
207 e1000_bus_speed_2500,
208 e1000_bus_speed_reserved
209} e1000_bus_speed;
210
211typedef enum {
212 e1000_bus_width_unknown = 0,
213 e1000_bus_width_pcie_x1,
214 e1000_bus_width_pcie_x2,
215 e1000_bus_width_pcie_x4 = 4,
216 e1000_bus_width_32,
217 e1000_bus_width_64,
218 e1000_bus_width_reserved
219} e1000_bus_width;
220
221typedef enum {
222 e1000_1000t_rx_status_not_ok = 0,
223 e1000_1000t_rx_status_ok,
224 e1000_1000t_rx_status_undefined = 0xFF
225} e1000_1000t_rx_status;
226
227typedef enum {
228 e1000_rev_polarity_normal = 0,
229 e1000_rev_polarity_reversed,
230 e1000_rev_polarity_undefined = 0xFF
231} e1000_rev_polarity;
232
233typedef enum {
234 e1000_fc_none = 0,
235 e1000_fc_rx_pause,
236 e1000_fc_tx_pause,
237 e1000_fc_full,
238 e1000_fc_default = 0xFF
239} e1000_fc_mode;
240
241typedef enum {
242 e1000_ffe_config_enabled = 0,
243 e1000_ffe_config_active,
244 e1000_ffe_config_blocked
245} e1000_ffe_config;
246
247typedef enum {
248 e1000_dsp_config_disabled = 0,
249 e1000_dsp_config_enabled,
250 e1000_dsp_config_activated,
251 e1000_dsp_config_undefined = 0xFF
252} e1000_dsp_config;
253
254/* Receive Descriptor */
255struct e1000_rx_desc {
256 u64 buffer_addr; /* Address of the descriptor's data buffer */
257 u16 length; /* Length of data DMAed into data buffer */
258 u16 csum; /* Packet checksum */
259 u8 status; /* Descriptor status */
260 u8 errors; /* Descriptor Errors */
261 u16 special;
262};
263
264/* Receive Descriptor - Extended */
265union e1000_rx_desc_extended {
266 struct {
267 u64 buffer_addr;
268 u64 reserved;
269 } read;
270 struct {
271 struct {
272 u32 mrq; /* Multiple Rx Queues */
273 union {
274 u32 rss; /* RSS Hash */
275 struct {
276 u16 ip_id; /* IP id */
277 u16 csum; /* Packet Checksum */
278 } csum_ip;
279 } hi_dword;
280 } lower;
281 struct {
282 u32 status_error; /* ext status/error */
283 u16 length;
284 u16 vlan; /* VLAN tag */
285 } upper;
286 } wb; /* writeback */
287};
288
289#define MAX_PS_BUFFERS 4
290/* Receive Descriptor - Packet Split */
291union e1000_rx_desc_packet_split {
292 struct {
293 /* one buffer for protocol header(s), three data buffers */
294 u64 buffer_addr[MAX_PS_BUFFERS];
295 } read;
296 struct {
297 struct {
298 u32 mrq; /* Multiple Rx Queues */
299 union {
300 u32 rss; /* RSS Hash */
301 struct {
302 u16 ip_id; /* IP id */
303 u16 csum; /* Packet Checksum */
304 } csum_ip;
305 } hi_dword;
306 } lower;
307 struct {
308 u32 status_error; /* ext status/error */
309 u16 length0; /* length of buffer 0 */
310 u16 vlan; /* VLAN tag */
311 } middle;
312 struct {
313 u16 header_status;
314 u16 length[3]; /* length of buffers 1-3 */
315 } upper;
316 u64 reserved;
317 } wb; /* writeback */
318};
319
320/* Transmit Descriptor */
321struct e1000_tx_desc {
322 u64 buffer_addr; /* Address of the descriptor's data buffer */
323 union {
324 u32 data;
325 struct {
326 u16 length; /* Data buffer length */
327 u8 cso; /* Checksum offset */
328 u8 cmd; /* Descriptor control */
329 } flags;
330 } lower;
331 union {
332 u32 data;
333 struct {
334 u8 status; /* Descriptor status */
335 u8 css; /* Checksum start */
336 u16 special;
337 } fields;
338 } upper;
339};
340
341/* Offload Context Descriptor */
342struct e1000_context_desc {
343 union {
344 u32 ip_config;
345 struct {
346 u8 ipcss; /* IP checksum start */
347 u8 ipcso; /* IP checksum offset */
348 u16 ipcse; /* IP checksum end */
349 } ip_fields;
350 } lower_setup;
351 union {
352 u32 tcp_config;
353 struct {
354 u8 tucss; /* TCP checksum start */
355 u8 tucso; /* TCP checksum offset */
356 u16 tucse; /* TCP checksum end */
357 } tcp_fields;
358 } upper_setup;
359 u32 cmd_and_length;
360 union {
361 u32 data;
362 struct {
363 u8 status; /* Descriptor status */
364 u8 hdr_len; /* Header length */
365 u16 mss; /* Maximum segment size */
366 } fields;
367 } tcp_seg_setup;
368};
369
370/* Offload data descriptor */
371struct e1000_data_desc {
372 u64 buffer_addr; /* Address of the descriptor's buffer address */
373 union {
374 u32 data;
375 struct {
376 u16 length; /* Data buffer length */
377 u8 typ_len_ext;
378 u8 cmd;
379 } flags;
380 } lower;
381 union {
382 u32 data;
383 struct {
384 u8 status; /* Descriptor status */
385 u8 popts; /* Packet Options */
386 u16 special; /* */
387 } fields;
388 } upper;
389};
390
391/* Statistics counters collected by the MAC */
392struct e1000_hw_stats {
393 u64 crcerrs;
394 u64 algnerrc;
395 u64 symerrs;
396 u64 rxerrc;
397 u64 mpc;
398 u64 scc;
399 u64 ecol;
400 u64 mcc;
401 u64 latecol;
402 u64 colc;
403 u64 dc;
404 u64 tncrs;
405 u64 sec;
406 u64 cexterr;
407 u64 rlec;
408 u64 xonrxc;
409 u64 xontxc;
410 u64 xoffrxc;
411 u64 xofftxc;
412 u64 fcruc;
413 u64 prc64;
414 u64 prc127;
415 u64 prc255;
416 u64 prc511;
417 u64 prc1023;
418 u64 prc1522;
419 u64 gprc;
420 u64 bprc;
421 u64 mprc;
422 u64 gptc;
423 u64 gorcl;
424 u64 gorch;
425 u64 gotcl;
426 u64 gotch;
427 u64 rnbc;
428 u64 ruc;
429 u64 rfc;
430 u64 roc;
431 u64 rjc;
432 u64 mgprc;
433 u64 mgpdc;
434 u64 mgptc;
435 u64 torl;
436 u64 torh;
437 u64 totl;
438 u64 toth;
439 u64 tpr;
440 u64 tpt;
441 u64 ptc64;
442 u64 ptc127;
443 u64 ptc255;
444 u64 ptc511;
445 u64 ptc1023;
446 u64 ptc1522;
447 u64 mptc;
448 u64 bptc;
449 u64 tsctc;
450 u64 tsctfc;
451 u64 iac;
452 u64 icrxptc;
453 u64 icrxatc;
454 u64 ictxptc;
455 u64 ictxatc;
456 u64 ictxqec;
457 u64 ictxqmtc;
458 u64 icrxdmtc;
459 u64 icrxoc;
460 u64 cbtmpc;
461 u64 htdpmc;
462 u64 cbrdpc;
463 u64 cbrmpc;
464 u64 rpthc;
465 u64 hgptc;
466 u64 htcbdpc;
467 u64 hgorcl;
468 u64 hgorch;
469 u64 hgotcl;
470 u64 hgotch;
471 u64 lenerrs;
472 u64 scvpc;
473 u64 hrmpc;
474};
475
476struct e1000_phy_stats {
477 u32 idle_errors;
478 u32 receive_errors;
479};
480
481struct e1000_host_mng_dhcp_cookie {
482 u32 signature;
483 u8 status;
484 u8 reserved0;
485 u16 vlan_id;
486 u32 reserved1;
487 u16 reserved2;
488 u8 reserved3;
489 u8 checksum;
490};
491
492/* Host Interface "Rev 1" */
493struct e1000_host_command_header {
494 u8 command_id;
495 u8 command_length;
496 u8 command_options;
497 u8 checksum;
498};
499
500#define E1000_HI_MAX_DATA_LENGTH 252
501struct e1000_host_command_info {
502 struct e1000_host_command_header command_header;
503 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
504};
505
506/* Host Interface "Rev 2" */
507struct e1000_host_mng_command_header {
508 u8 command_id;
509 u8 checksum;
510 u16 reserved1;
511 u16 reserved2;
512 u16 command_length;
513};
514
515#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
516struct e1000_host_mng_command_info {
517 struct e1000_host_mng_command_header command_header;
518 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
519};
520
521#include "e1000_mac.h"
522#include "e1000_phy.h"
523#include "e1000_nvm.h"
524#include "e1000_manage.h"
525
526struct e1000_functions {
527 /* Function pointers for the MAC. */
528 s32 (*init_mac_params)(struct e1000_hw *);
529 s32 (*blink_led)(struct e1000_hw *);
530 s32 (*check_for_link)(struct e1000_hw *);
531 boolean_t (*check_mng_mode)(struct e1000_hw *hw);
532 s32 (*cleanup_led)(struct e1000_hw *);
533 void (*clear_hw_cntrs)(struct e1000_hw *);
534 void (*clear_vfta)(struct e1000_hw *);
535 s32 (*get_bus_info)(struct e1000_hw *);
536 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
537 s32 (*led_on)(struct e1000_hw *);
538 s32 (*led_off)(struct e1000_hw *);
539 void (*mc_addr_list_update)(struct e1000_hw *, u8 *, u32, u32,
540 u32);
541 void (*remove_device)(struct e1000_hw *);
542 s32 (*reset_hw)(struct e1000_hw *);
543 s32 (*init_hw)(struct e1000_hw *);
544 s32 (*setup_link)(struct e1000_hw *);
545 s32 (*setup_physical_interface)(struct e1000_hw *);
546 s32 (*setup_led)(struct e1000_hw *);
547 void (*write_vfta)(struct e1000_hw *, u32, u32);
548 void (*mta_set)(struct e1000_hw *, u32);
549 void (*config_collision_dist)(struct e1000_hw*);
550 void (*rar_set)(struct e1000_hw*, u8*, u32);
551 s32 (*validate_mdi_setting)(struct e1000_hw*);
552 s32 (*mng_host_if_write)(struct e1000_hw*, u8*, u16, u16, u8*);
553 s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
554 struct e1000_host_mng_command_header*);
555 s32 (*mng_enable_host_if)(struct e1000_hw*);
556 s32 (*wait_autoneg)(struct e1000_hw*);
557
558 /* Function pointers for the PHY. */
559 s32 (*init_phy_params)(struct e1000_hw *);
560 s32 (*acquire_phy)(struct e1000_hw *);
561 s32 (*check_polarity)(struct e1000_hw *);
562 s32 (*check_reset_block)(struct e1000_hw *);
563 s32 (*commit_phy)(struct e1000_hw *);
564 s32 (*force_speed_duplex)(struct e1000_hw *);
565 s32 (*get_cfg_done)(struct e1000_hw *hw);
566 s32 (*get_cable_length)(struct e1000_hw *);
567 s32 (*get_phy_info)(struct e1000_hw *);
568 s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
569 void (*release_phy)(struct e1000_hw *);
570 s32 (*reset_phy)(struct e1000_hw *);
571 s32 (*set_d0_lplu_state)(struct e1000_hw *, boolean_t);
572 s32 (*set_d3_lplu_state)(struct e1000_hw *, boolean_t);
573 s32 (*write_phy_reg)(struct e1000_hw *, u32, u16);
574
575 /* Function pointers for the NVM. */
576 s32 (*init_nvm_params)(struct e1000_hw *);
577 s32 (*acquire_nvm)(struct e1000_hw *);
578 s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
579 void (*release_nvm)(struct e1000_hw *);
580 void (*reload_nvm)(struct e1000_hw *);
581 s32 (*update_nvm)(struct e1000_hw *);
582 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
583 s32 (*validate_nvm)(struct e1000_hw *);
584 s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
585};
586
587struct e1000_mac_info {
588 u8 addr[6];
589 u8 perm_addr[6];
590
591 e1000_mac_type type;
592 e1000_fc_mode fc;
593 e1000_fc_mode original_fc;
594
595 u32 collision_delta;
596 u32 ledctl_default;
597 u32 ledctl_mode1;
598 u32 ledctl_mode2;
599 u32 max_frame_size;
600 u32 mc_filter_type;
601 u32 min_frame_size;
602 u32 tx_packet_delta;
603 u32 txcw;
604
605 u16 current_ifs_val;
606 u16 ifs_max_val;
607 u16 ifs_min_val;
608 u16 ifs_ratio;
609 u16 ifs_step_size;
610 u16 mta_reg_count;
611 u16 rar_entry_count;
612 u16 fc_high_water;
613 u16 fc_low_water;
614 u16 fc_pause_time;
615
616 u8 forced_speed_duplex;
617
618 boolean_t adaptive_ifs;
619 boolean_t arc_subsystem_valid;
620 boolean_t asf_firmware_present;
621 boolean_t autoneg;
622 boolean_t autoneg_failed;
623 boolean_t disable_av;
624 boolean_t disable_hw_init_bits;
625 boolean_t fc_send_xon;
626 boolean_t fc_strict_ieee;
627 boolean_t get_link_status;
628 boolean_t ifs_params_forced;
629 boolean_t in_ifs_mode;
630 boolean_t report_tx_early;
631 boolean_t serdes_has_link;
632 boolean_t tx_pkt_filtering;
633};
634
635struct e1000_phy_info {
636 e1000_phy_type type;
637
638 e1000_1000t_rx_status local_rx;
639 e1000_1000t_rx_status remote_rx;
640 e1000_ms_type ms_type;
641 e1000_ms_type original_ms_type;
642 e1000_rev_polarity cable_polarity;
643 e1000_smart_speed smart_speed;
644
645 u32 addr;
646 u32 id;
647 u32 reset_delay_us; /* in usec */
648 u32 revision;
649
650 u16 autoneg_advertised;
651 u16 autoneg_mask;
652 u16 cable_length;
653 u16 max_cable_length;
654 u16 min_cable_length;
655
656 u8 mdix;
657
658 boolean_t disable_polarity_correction;
659 boolean_t is_mdix;
660 boolean_t polarity_correction;
661 boolean_t reset_disable;
662 boolean_t speed_downgraded;
663 boolean_t wait_for_link;
664};
665
666struct e1000_nvm_info {
667 e1000_nvm_type type;
668 e1000_nvm_override override;
669
670 u32 flash_bank_size;
671 u32 flash_base_addr;
672
673 u16 word_size;
674 u16 delay_usec;
675 u16 address_bits;
676 u16 opcode_bits;
677 u16 page_size;
678};
679
680struct e1000_bus_info {
681 e1000_bus_type type;
682 e1000_bus_speed speed;
683 e1000_bus_width width;
684
685 u32 snoop;
686
687 u16 func;
688 u16 pci_cmd_word;
689};
690
691struct e1000_hw {
692 void *back;
693 void *dev_spec;
694
695 u8 *hw_addr;
696 u8 *flash_address;
697 unsigned long io_base;
698
699 struct e1000_functions func;
700 struct e1000_mac_info mac;
701 struct e1000_phy_info phy;
702 struct e1000_nvm_info nvm;
703 struct e1000_bus_info bus;
704 struct e1000_host_mng_dhcp_cookie mng_cookie;
705
706 e1000_media_type media_type;
707
708 u32 dev_spec_size;
709
710 u16 device_id;
711 u16 subsystem_vendor_id;
712 u16 subsystem_device_id;
713 u16 vendor_id;
714
715 u8 revision_id;
716};
717
718/* These functions must be implemented by drivers */
719void e1000_pci_clear_mwi(struct e1000_hw *hw);
720void e1000_pci_set_mwi(struct e1000_hw *hw);
721s32 e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size);
722s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
723void e1000_free_dev_spec_struct(struct e1000_hw *hw);
724void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
725void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
726
727#endif
| 153} e1000_mac_type;
154
155typedef enum {
156 e1000_media_type_unknown = 0,
157 e1000_media_type_copper = 1,
158 e1000_media_type_fiber = 2,
159 e1000_media_type_internal_serdes = 3,
160 e1000_num_media_types
161} e1000_media_type;
162
163typedef enum {
164 e1000_nvm_unknown = 0,
165 e1000_nvm_none,
166 e1000_nvm_eeprom_spi,
167 e1000_nvm_eeprom_microwire,
168 e1000_nvm_flash_hw,
169 e1000_nvm_flash_sw
170} e1000_nvm_type;
171
172typedef enum {
173 e1000_nvm_override_none = 0,
174 e1000_nvm_override_spi_small,
175 e1000_nvm_override_spi_large,
176 e1000_nvm_override_microwire_small,
177 e1000_nvm_override_microwire_large
178} e1000_nvm_override;
179
180typedef enum {
181 e1000_phy_unknown = 0,
182 e1000_phy_none,
183 e1000_phy_m88,
184 e1000_phy_igp,
185 e1000_phy_igp_2,
186 e1000_phy_gg82563,
187 e1000_phy_igp_3,
188 e1000_phy_ife,
189} e1000_phy_type;
190
191typedef enum {
192 e1000_bus_type_unknown = 0,
193 e1000_bus_type_pci,
194 e1000_bus_type_pcix,
195 e1000_bus_type_pci_express,
196 e1000_bus_type_reserved
197} e1000_bus_type;
198
199typedef enum {
200 e1000_bus_speed_unknown = 0,
201 e1000_bus_speed_33,
202 e1000_bus_speed_66,
203 e1000_bus_speed_100,
204 e1000_bus_speed_120,
205 e1000_bus_speed_133,
206 e1000_bus_speed_2500,
207 e1000_bus_speed_reserved
208} e1000_bus_speed;
209
210typedef enum {
211 e1000_bus_width_unknown = 0,
212 e1000_bus_width_pcie_x1,
213 e1000_bus_width_pcie_x2,
214 e1000_bus_width_pcie_x4 = 4,
215 e1000_bus_width_32,
216 e1000_bus_width_64,
217 e1000_bus_width_reserved
218} e1000_bus_width;
219
220typedef enum {
221 e1000_1000t_rx_status_not_ok = 0,
222 e1000_1000t_rx_status_ok,
223 e1000_1000t_rx_status_undefined = 0xFF
224} e1000_1000t_rx_status;
225
226typedef enum {
227 e1000_rev_polarity_normal = 0,
228 e1000_rev_polarity_reversed,
229 e1000_rev_polarity_undefined = 0xFF
230} e1000_rev_polarity;
231
232typedef enum {
233 e1000_fc_none = 0,
234 e1000_fc_rx_pause,
235 e1000_fc_tx_pause,
236 e1000_fc_full,
237 e1000_fc_default = 0xFF
238} e1000_fc_mode;
239
240typedef enum {
241 e1000_ffe_config_enabled = 0,
242 e1000_ffe_config_active,
243 e1000_ffe_config_blocked
244} e1000_ffe_config;
245
246typedef enum {
247 e1000_dsp_config_disabled = 0,
248 e1000_dsp_config_enabled,
249 e1000_dsp_config_activated,
250 e1000_dsp_config_undefined = 0xFF
251} e1000_dsp_config;
252
253/* Receive Descriptor */
254struct e1000_rx_desc {
255 u64 buffer_addr; /* Address of the descriptor's data buffer */
256 u16 length; /* Length of data DMAed into data buffer */
257 u16 csum; /* Packet checksum */
258 u8 status; /* Descriptor status */
259 u8 errors; /* Descriptor Errors */
260 u16 special;
261};
262
263/* Receive Descriptor - Extended */
264union e1000_rx_desc_extended {
265 struct {
266 u64 buffer_addr;
267 u64 reserved;
268 } read;
269 struct {
270 struct {
271 u32 mrq; /* Multiple Rx Queues */
272 union {
273 u32 rss; /* RSS Hash */
274 struct {
275 u16 ip_id; /* IP id */
276 u16 csum; /* Packet Checksum */
277 } csum_ip;
278 } hi_dword;
279 } lower;
280 struct {
281 u32 status_error; /* ext status/error */
282 u16 length;
283 u16 vlan; /* VLAN tag */
284 } upper;
285 } wb; /* writeback */
286};
287
288#define MAX_PS_BUFFERS 4
289/* Receive Descriptor - Packet Split */
290union e1000_rx_desc_packet_split {
291 struct {
292 /* one buffer for protocol header(s), three data buffers */
293 u64 buffer_addr[MAX_PS_BUFFERS];
294 } read;
295 struct {
296 struct {
297 u32 mrq; /* Multiple Rx Queues */
298 union {
299 u32 rss; /* RSS Hash */
300 struct {
301 u16 ip_id; /* IP id */
302 u16 csum; /* Packet Checksum */
303 } csum_ip;
304 } hi_dword;
305 } lower;
306 struct {
307 u32 status_error; /* ext status/error */
308 u16 length0; /* length of buffer 0 */
309 u16 vlan; /* VLAN tag */
310 } middle;
311 struct {
312 u16 header_status;
313 u16 length[3]; /* length of buffers 1-3 */
314 } upper;
315 u64 reserved;
316 } wb; /* writeback */
317};
318
319/* Transmit Descriptor */
320struct e1000_tx_desc {
321 u64 buffer_addr; /* Address of the descriptor's data buffer */
322 union {
323 u32 data;
324 struct {
325 u16 length; /* Data buffer length */
326 u8 cso; /* Checksum offset */
327 u8 cmd; /* Descriptor control */
328 } flags;
329 } lower;
330 union {
331 u32 data;
332 struct {
333 u8 status; /* Descriptor status */
334 u8 css; /* Checksum start */
335 u16 special;
336 } fields;
337 } upper;
338};
339
340/* Offload Context Descriptor */
341struct e1000_context_desc {
342 union {
343 u32 ip_config;
344 struct {
345 u8 ipcss; /* IP checksum start */
346 u8 ipcso; /* IP checksum offset */
347 u16 ipcse; /* IP checksum end */
348 } ip_fields;
349 } lower_setup;
350 union {
351 u32 tcp_config;
352 struct {
353 u8 tucss; /* TCP checksum start */
354 u8 tucso; /* TCP checksum offset */
355 u16 tucse; /* TCP checksum end */
356 } tcp_fields;
357 } upper_setup;
358 u32 cmd_and_length;
359 union {
360 u32 data;
361 struct {
362 u8 status; /* Descriptor status */
363 u8 hdr_len; /* Header length */
364 u16 mss; /* Maximum segment size */
365 } fields;
366 } tcp_seg_setup;
367};
368
369/* Offload data descriptor */
370struct e1000_data_desc {
371 u64 buffer_addr; /* Address of the descriptor's buffer address */
372 union {
373 u32 data;
374 struct {
375 u16 length; /* Data buffer length */
376 u8 typ_len_ext;
377 u8 cmd;
378 } flags;
379 } lower;
380 union {
381 u32 data;
382 struct {
383 u8 status; /* Descriptor status */
384 u8 popts; /* Packet Options */
385 u16 special; /* */
386 } fields;
387 } upper;
388};
389
390/* Statistics counters collected by the MAC */
391struct e1000_hw_stats {
392 u64 crcerrs;
393 u64 algnerrc;
394 u64 symerrs;
395 u64 rxerrc;
396 u64 mpc;
397 u64 scc;
398 u64 ecol;
399 u64 mcc;
400 u64 latecol;
401 u64 colc;
402 u64 dc;
403 u64 tncrs;
404 u64 sec;
405 u64 cexterr;
406 u64 rlec;
407 u64 xonrxc;
408 u64 xontxc;
409 u64 xoffrxc;
410 u64 xofftxc;
411 u64 fcruc;
412 u64 prc64;
413 u64 prc127;
414 u64 prc255;
415 u64 prc511;
416 u64 prc1023;
417 u64 prc1522;
418 u64 gprc;
419 u64 bprc;
420 u64 mprc;
421 u64 gptc;
422 u64 gorcl;
423 u64 gorch;
424 u64 gotcl;
425 u64 gotch;
426 u64 rnbc;
427 u64 ruc;
428 u64 rfc;
429 u64 roc;
430 u64 rjc;
431 u64 mgprc;
432 u64 mgpdc;
433 u64 mgptc;
434 u64 torl;
435 u64 torh;
436 u64 totl;
437 u64 toth;
438 u64 tpr;
439 u64 tpt;
440 u64 ptc64;
441 u64 ptc127;
442 u64 ptc255;
443 u64 ptc511;
444 u64 ptc1023;
445 u64 ptc1522;
446 u64 mptc;
447 u64 bptc;
448 u64 tsctc;
449 u64 tsctfc;
450 u64 iac;
451 u64 icrxptc;
452 u64 icrxatc;
453 u64 ictxptc;
454 u64 ictxatc;
455 u64 ictxqec;
456 u64 ictxqmtc;
457 u64 icrxdmtc;
458 u64 icrxoc;
459 u64 cbtmpc;
460 u64 htdpmc;
461 u64 cbrdpc;
462 u64 cbrmpc;
463 u64 rpthc;
464 u64 hgptc;
465 u64 htcbdpc;
466 u64 hgorcl;
467 u64 hgorch;
468 u64 hgotcl;
469 u64 hgotch;
470 u64 lenerrs;
471 u64 scvpc;
472 u64 hrmpc;
473};
474
475struct e1000_phy_stats {
476 u32 idle_errors;
477 u32 receive_errors;
478};
479
480struct e1000_host_mng_dhcp_cookie {
481 u32 signature;
482 u8 status;
483 u8 reserved0;
484 u16 vlan_id;
485 u32 reserved1;
486 u16 reserved2;
487 u8 reserved3;
488 u8 checksum;
489};
490
491/* Host Interface "Rev 1" */
492struct e1000_host_command_header {
493 u8 command_id;
494 u8 command_length;
495 u8 command_options;
496 u8 checksum;
497};
498
499#define E1000_HI_MAX_DATA_LENGTH 252
500struct e1000_host_command_info {
501 struct e1000_host_command_header command_header;
502 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
503};
504
505/* Host Interface "Rev 2" */
506struct e1000_host_mng_command_header {
507 u8 command_id;
508 u8 checksum;
509 u16 reserved1;
510 u16 reserved2;
511 u16 command_length;
512};
513
514#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
515struct e1000_host_mng_command_info {
516 struct e1000_host_mng_command_header command_header;
517 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
518};
519
520#include "e1000_mac.h"
521#include "e1000_phy.h"
522#include "e1000_nvm.h"
523#include "e1000_manage.h"
524
525struct e1000_functions {
526 /* Function pointers for the MAC. */
527 s32 (*init_mac_params)(struct e1000_hw *);
528 s32 (*blink_led)(struct e1000_hw *);
529 s32 (*check_for_link)(struct e1000_hw *);
530 boolean_t (*check_mng_mode)(struct e1000_hw *hw);
531 s32 (*cleanup_led)(struct e1000_hw *);
532 void (*clear_hw_cntrs)(struct e1000_hw *);
533 void (*clear_vfta)(struct e1000_hw *);
534 s32 (*get_bus_info)(struct e1000_hw *);
535 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
536 s32 (*led_on)(struct e1000_hw *);
537 s32 (*led_off)(struct e1000_hw *);
538 void (*mc_addr_list_update)(struct e1000_hw *, u8 *, u32, u32,
539 u32);
540 void (*remove_device)(struct e1000_hw *);
541 s32 (*reset_hw)(struct e1000_hw *);
542 s32 (*init_hw)(struct e1000_hw *);
543 s32 (*setup_link)(struct e1000_hw *);
544 s32 (*setup_physical_interface)(struct e1000_hw *);
545 s32 (*setup_led)(struct e1000_hw *);
546 void (*write_vfta)(struct e1000_hw *, u32, u32);
547 void (*mta_set)(struct e1000_hw *, u32);
548 void (*config_collision_dist)(struct e1000_hw*);
549 void (*rar_set)(struct e1000_hw*, u8*, u32);
550 s32 (*validate_mdi_setting)(struct e1000_hw*);
551 s32 (*mng_host_if_write)(struct e1000_hw*, u8*, u16, u16, u8*);
552 s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
553 struct e1000_host_mng_command_header*);
554 s32 (*mng_enable_host_if)(struct e1000_hw*);
555 s32 (*wait_autoneg)(struct e1000_hw*);
556
557 /* Function pointers for the PHY. */
558 s32 (*init_phy_params)(struct e1000_hw *);
559 s32 (*acquire_phy)(struct e1000_hw *);
560 s32 (*check_polarity)(struct e1000_hw *);
561 s32 (*check_reset_block)(struct e1000_hw *);
562 s32 (*commit_phy)(struct e1000_hw *);
563 s32 (*force_speed_duplex)(struct e1000_hw *);
564 s32 (*get_cfg_done)(struct e1000_hw *hw);
565 s32 (*get_cable_length)(struct e1000_hw *);
566 s32 (*get_phy_info)(struct e1000_hw *);
567 s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
568 void (*release_phy)(struct e1000_hw *);
569 s32 (*reset_phy)(struct e1000_hw *);
570 s32 (*set_d0_lplu_state)(struct e1000_hw *, boolean_t);
571 s32 (*set_d3_lplu_state)(struct e1000_hw *, boolean_t);
572 s32 (*write_phy_reg)(struct e1000_hw *, u32, u16);
573
574 /* Function pointers for the NVM. */
575 s32 (*init_nvm_params)(struct e1000_hw *);
576 s32 (*acquire_nvm)(struct e1000_hw *);
577 s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
578 void (*release_nvm)(struct e1000_hw *);
579 void (*reload_nvm)(struct e1000_hw *);
580 s32 (*update_nvm)(struct e1000_hw *);
581 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
582 s32 (*validate_nvm)(struct e1000_hw *);
583 s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
584};
585
586struct e1000_mac_info {
587 u8 addr[6];
588 u8 perm_addr[6];
589
590 e1000_mac_type type;
591 e1000_fc_mode fc;
592 e1000_fc_mode original_fc;
593
594 u32 collision_delta;
595 u32 ledctl_default;
596 u32 ledctl_mode1;
597 u32 ledctl_mode2;
598 u32 max_frame_size;
599 u32 mc_filter_type;
600 u32 min_frame_size;
601 u32 tx_packet_delta;
602 u32 txcw;
603
604 u16 current_ifs_val;
605 u16 ifs_max_val;
606 u16 ifs_min_val;
607 u16 ifs_ratio;
608 u16 ifs_step_size;
609 u16 mta_reg_count;
610 u16 rar_entry_count;
611 u16 fc_high_water;
612 u16 fc_low_water;
613 u16 fc_pause_time;
614
615 u8 forced_speed_duplex;
616
617 boolean_t adaptive_ifs;
618 boolean_t arc_subsystem_valid;
619 boolean_t asf_firmware_present;
620 boolean_t autoneg;
621 boolean_t autoneg_failed;
622 boolean_t disable_av;
623 boolean_t disable_hw_init_bits;
624 boolean_t fc_send_xon;
625 boolean_t fc_strict_ieee;
626 boolean_t get_link_status;
627 boolean_t ifs_params_forced;
628 boolean_t in_ifs_mode;
629 boolean_t report_tx_early;
630 boolean_t serdes_has_link;
631 boolean_t tx_pkt_filtering;
632};
633
634struct e1000_phy_info {
635 e1000_phy_type type;
636
637 e1000_1000t_rx_status local_rx;
638 e1000_1000t_rx_status remote_rx;
639 e1000_ms_type ms_type;
640 e1000_ms_type original_ms_type;
641 e1000_rev_polarity cable_polarity;
642 e1000_smart_speed smart_speed;
643
644 u32 addr;
645 u32 id;
646 u32 reset_delay_us; /* in usec */
647 u32 revision;
648
649 u16 autoneg_advertised;
650 u16 autoneg_mask;
651 u16 cable_length;
652 u16 max_cable_length;
653 u16 min_cable_length;
654
655 u8 mdix;
656
657 boolean_t disable_polarity_correction;
658 boolean_t is_mdix;
659 boolean_t polarity_correction;
660 boolean_t reset_disable;
661 boolean_t speed_downgraded;
662 boolean_t wait_for_link;
663};
664
665struct e1000_nvm_info {
666 e1000_nvm_type type;
667 e1000_nvm_override override;
668
669 u32 flash_bank_size;
670 u32 flash_base_addr;
671
672 u16 word_size;
673 u16 delay_usec;
674 u16 address_bits;
675 u16 opcode_bits;
676 u16 page_size;
677};
678
679struct e1000_bus_info {
680 e1000_bus_type type;
681 e1000_bus_speed speed;
682 e1000_bus_width width;
683
684 u32 snoop;
685
686 u16 func;
687 u16 pci_cmd_word;
688};
689
690struct e1000_hw {
691 void *back;
692 void *dev_spec;
693
694 u8 *hw_addr;
695 u8 *flash_address;
696 unsigned long io_base;
697
698 struct e1000_functions func;
699 struct e1000_mac_info mac;
700 struct e1000_phy_info phy;
701 struct e1000_nvm_info nvm;
702 struct e1000_bus_info bus;
703 struct e1000_host_mng_dhcp_cookie mng_cookie;
704
705 e1000_media_type media_type;
706
707 u32 dev_spec_size;
708
709 u16 device_id;
710 u16 subsystem_vendor_id;
711 u16 subsystem_device_id;
712 u16 vendor_id;
713
714 u8 revision_id;
715};
716
717/* These functions must be implemented by drivers */
718void e1000_pci_clear_mwi(struct e1000_hw *hw);
719void e1000_pci_set_mwi(struct e1000_hw *hw);
720s32 e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size);
721s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
722void e1000_free_dev_spec_struct(struct e1000_hw *hw);
723void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
724void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
725
726#endif
|