| e1000_defines.h (235527) | e1000_defines.h (238262) |
|---|---|
| 1/****************************************************************************** 2 | 1/****************************************************************************** 2 |
| 3 Copyright (c) 2001-2011, Intel Corporation | 3 Copyright (c) 2001-2012, Intel Corporation |
| 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 13 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 --- 13 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: stable/9/sys/dev/e1000/e1000_defines.h 235527 2012-05-16 22:22:52Z jfv $*/ | 33/*$FreeBSD: stable/9/sys/dev/e1000/e1000_defines.h 238262 2012-07-08 20:35:56Z jfv $*/ |
| 34 35#ifndef _E1000_DEFINES_H_ 36#define _E1000_DEFINES_H_ 37 38/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 39#define REQ_TX_DESCRIPTOR_MULTIPLE 8 40#define REQ_RX_DESCRIPTOR_MULTIPLE 8 41 --- 1297 unchanged lines hidden (view full) --- 1339#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 1340#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 1341#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1342#define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ 1343#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 1344#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1345#define E1000_EECD_SECVAL_SHIFT 22 1346#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) | 34 35#ifndef _E1000_DEFINES_H_ 36#define _E1000_DEFINES_H_ 37 38/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 39#define REQ_TX_DESCRIPTOR_MULTIPLE 8 40#define REQ_RX_DESCRIPTOR_MULTIPLE 8 41 --- 1297 unchanged lines hidden (view full) --- 1339#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 1340#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 1341#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1342#define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ 1343#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 1344#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1345#define E1000_EECD_SECVAL_SHIFT 22 1346#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) |
| 1347#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 1348#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */ 1349#define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ 1350#define E1000_FLUDONE_ATTEMPTS 20000 1351#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 1352#define E1000_I210_FIFO_SEL_RX 0x00 1353#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 1354#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 1355#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 1356#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 |
|
| 1347 1348#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */ 1349#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */ 1350#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ 1351#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1352#define E1000_NVM_RW_REG_START 1 /* Start operation */ 1353#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1354#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 1355#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 1356#define E1000_FLASH_UPDATES 2000 1357 1358/* NVM Word Offsets */ 1359#define NVM_COMPAT 0x0003 1360#define NVM_ID_LED_SETTINGS 0x0004 1361#define NVM_VERSION 0x0005 1362#define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ 1363#define NVM_PHY_CLASS_WORD 0x0007 | 1357 1358#define E1000_NVM_SWDPIN0 0x0001 /* SWDPIN 0 NVM Value */ 1359#define E1000_NVM_LED_LOGIC 0x0020 /* Led Logic Word */ 1360#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ 1361#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1362#define E1000_NVM_RW_REG_START 1 /* Start operation */ 1363#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1364#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 1365#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 1366#define E1000_FLASH_UPDATES 2000 1367 1368/* NVM Word Offsets */ 1369#define NVM_COMPAT 0x0003 1370#define NVM_ID_LED_SETTINGS 0x0004 1371#define NVM_VERSION 0x0005 1372#define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ 1373#define NVM_PHY_CLASS_WORD 0x0007 |
| 1374#define NVM_ETRACK_WORD 0x0042 1375#define NVM_COMB_VER_OFF 0x0083 1376#define NVM_COMB_VER_PTR 0x003d 1377 1378#define NVM_MAC_ADDR 0x0000 1379#define NVM_SUB_DEV_ID 0x000B 1380#define NVM_SUB_VEN_ID 0x000C 1381#define NVM_DEV_ID 0x000D 1382#define NVM_VEN_ID 0x000E 1383#define NVM_INIT_CTRL_2 0x000F 1384#define NVM_INIT_CTRL_4 0x0013 1385#define NVM_LED_1_CFG 0x001C 1386#define NVM_LED_0_2_CFG 0x001F 1387 |
|
| 1364#define NVM_INIT_CONTROL1_REG 0x000A 1365#define NVM_INIT_CONTROL2_REG 0x000F 1366#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 1367#define NVM_INIT_CONTROL3_PORT_B 0x0014 1368#define NVM_INIT_3GIO_3 0x001A 1369#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 1370#define NVM_INIT_CONTROL3_PORT_A 0x0024 1371#define NVM_CFG 0x0012 1372#define NVM_FLASH_VERSION 0x0032 1373#define NVM_ALT_MAC_ADDR_PTR 0x0037 1374#define NVM_CHECKSUM_REG 0x003F 1375#define NVM_COMPATIBILITY_REG_3 0x0003 1376#define NVM_COMPATIBILITY_BIT_MASK 0x8000 1377 1378#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 1379#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 1380#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 1381#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 1382 | 1388#define NVM_INIT_CONTROL1_REG 0x000A 1389#define NVM_INIT_CONTROL2_REG 0x000F 1390#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 1391#define NVM_INIT_CONTROL3_PORT_B 0x0014 1392#define NVM_INIT_3GIO_3 0x001A 1393#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 1394#define NVM_INIT_CONTROL3_PORT_A 0x0024 1395#define NVM_CFG 0x0012 1396#define NVM_FLASH_VERSION 0x0032 1397#define NVM_ALT_MAC_ADDR_PTR 0x0037 1398#define NVM_CHECKSUM_REG 0x003F 1399#define NVM_COMPATIBILITY_REG_3 0x0003 1400#define NVM_COMPATIBILITY_BIT_MASK 0x8000 1401 1402#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 1403#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 1404#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 1405#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 1406 |
| 1383#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0) | 1407#define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0) |
| 1384 1385/* Mask bits for fields in Word 0x24 of the NVM */ 1386#define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 1387#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */ | 1408 1409/* Mask bits for fields in Word 0x24 of the NVM */ 1410#define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 1411#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */ |
| 1388/* Offset of Link Mode bits for 82575 up to Kawela */ | 1412/* Offset of Link Mode bits for 82575/82576 */ |
| 1389#define NVM_WORD24_LNK_MODE_OFFSET 8 1390/* Offset of Link Mode bits for 82580 up */ 1391#define NVM_WORD24_82580_LNK_MODE_OFFSET 4 1392 1393 1394/* Mask bits for fields in Word 0x0f of the NVM */ 1395#define NVM_WORD0F_PAUSE_MASK 0x3000 1396#define NVM_WORD0F_PAUSE 0x1000 --- 123 unchanged lines hidden (view full) --- 1520#define IFE_C_E_PHY_ID 0x02A80310 1521#define BME1000_E_PHY_ID 0x01410CB0 1522#define BME1000_E_PHY_ID_R2 0x01410CB1 1523#define I82577_E_PHY_ID 0x01540050 1524#define I82578_E_PHY_ID 0x004DD040 1525#define I82579_E_PHY_ID 0x01540090 1526#define I82580_I_PHY_ID 0x015403A0 1527#define I350_I_PHY_ID 0x015403B0 | 1413#define NVM_WORD24_LNK_MODE_OFFSET 8 1414/* Offset of Link Mode bits for 82580 up */ 1415#define NVM_WORD24_82580_LNK_MODE_OFFSET 4 1416 1417 1418/* Mask bits for fields in Word 0x0f of the NVM */ 1419#define NVM_WORD0F_PAUSE_MASK 0x3000 1420#define NVM_WORD0F_PAUSE 0x1000 --- 123 unchanged lines hidden (view full) --- 1544#define IFE_C_E_PHY_ID 0x02A80310 1545#define BME1000_E_PHY_ID 0x01410CB0 1546#define BME1000_E_PHY_ID_R2 0x01410CB1 1547#define I82577_E_PHY_ID 0x01540050 1548#define I82578_E_PHY_ID 0x004DD040 1549#define I82579_E_PHY_ID 0x01540090 1550#define I82580_I_PHY_ID 0x015403A0 1551#define I350_I_PHY_ID 0x015403B0 |
| 1552#define I210_I_PHY_ID 0x01410C00 |
|
| 1528#define IGP04E1000_E_PHY_ID 0x02A80391 1529#define M88_VENDOR 0x0141 1530 1531/* M88E1000 Specific Registers */ 1532#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ 1533#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ 1534#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Reg */ 1535#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Reg */ --- 246 unchanged lines hidden (view full) --- 1782#define E1000_DMACR_DMACWT_MASK 0x00003FFF 1783/* DMA Coalescing Rx Threshold */ 1784#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 1785#define E1000_DMACR_DMACTHR_SHIFT 16 1786/* Lx when no PCIe transactions */ 1787#define E1000_DMACR_DMAC_LX_MASK 0x30000000 1788#define E1000_DMACR_DMAC_LX_SHIFT 28 1789#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ | 1553#define IGP04E1000_E_PHY_ID 0x02A80391 1554#define M88_VENDOR 0x0141 1555 1556/* M88E1000 Specific Registers */ 1557#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ 1558#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ 1559#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Reg */ 1560#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Reg */ --- 246 unchanged lines hidden (view full) --- 1807#define E1000_DMACR_DMACWT_MASK 0x00003FFF 1808/* DMA Coalescing Rx Threshold */ 1809#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 1810#define E1000_DMACR_DMACTHR_SHIFT 16 1811/* Lx when no PCIe transactions */ 1812#define E1000_DMACR_DMAC_LX_MASK 0x30000000 1813#define E1000_DMACR_DMAC_LX_SHIFT 28 1814#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ |
| 1815/* DMA Coalescing BMC-to-OS Watchdog Enable */ 1816#define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 |
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| 1790 1791/* DMA Coalescing Transmit Threshold */ 1792#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF 1793 1794#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 1795 1796/* Rx Traffic Rate Threshold */ 1797#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF --- 4 unchanged lines hidden (view full) --- 1802#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF 1803 1804/* Flow ctrl Rx Threshold High val */ 1805#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 1806#define E1000_FCRTC_RTH_COAL_SHIFT 4 1807/* Lx power decision based on DMA coal */ 1808#define E1000_PCIEMISC_LX_DECISION 0x00000080 1809 | 1817 1818/* DMA Coalescing Transmit Threshold */ 1819#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF 1820 1821#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 1822 1823/* Rx Traffic Rate Threshold */ 1824#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF --- 4 unchanged lines hidden (view full) --- 1829#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF 1830 1831/* Flow ctrl Rx Threshold High val */ 1832#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 1833#define E1000_FCRTC_RTH_COAL_SHIFT 4 1834/* Lx power decision based on DMA coal */ 1835#define E1000_PCIEMISC_LX_DECISION 0x00000080 1836 |
| 1810#define E1000_LTRC_EEEMS_EN 0x00000005 /* Enable EEE LTR max send */ | |
| 1811#define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ | 1837#define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ |
| 1838#define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ 1839#define E1000_LTRC_EEEMS_EN 0x00000020 /* Enable EEE LTR max send */ |
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| 1812/* Minimum time for 1000BASE-T where no data will be transmit following move out 1813 * of EEE LPI Tx state 1814 */ 1815#define E1000_TW_SYSTEM_1000_MASK 0x000000FF 1816/* Minimum time for 100BASE-T where no data will be transmit following move out 1817 * of EEE LPI Tx state 1818 */ 1819#define E1000_TW_SYSTEM_100_MASK 0x0000FF00 1820#define E1000_TW_SYSTEM_100_SHIFT 8 1821#define E1000_LTRMINV_LTRV_MASK 0x000003FF /* LTR minimum value */ 1822#define E1000_LTRMAXV_LTRV_MASK 0x000003FF /* LTR maximum value */ 1823#define E1000_LTRMINV_SCALE_MASK 0x00001C00 /* LTR minimum scale */ 1824#define E1000_LTRMINV_SCALE_SHIFT 10 1825/* Reg val to set scale to 1024 nsec */ 1826#define E1000_LTRMINV_SCALE_1024 2 1827/* Reg val to set scale to 32768 nsec */ 1828#define E1000_LTRMINV_SCALE_32768 3 | 1840/* Minimum time for 1000BASE-T where no data will be transmit following move out 1841 * of EEE LPI Tx state 1842 */ 1843#define E1000_TW_SYSTEM_1000_MASK 0x000000FF 1844/* Minimum time for 100BASE-T where no data will be transmit following move out 1845 * of EEE LPI Tx state 1846 */ 1847#define E1000_TW_SYSTEM_100_MASK 0x0000FF00 1848#define E1000_TW_SYSTEM_100_SHIFT 8 1849#define E1000_LTRMINV_LTRV_MASK 0x000003FF /* LTR minimum value */ 1850#define E1000_LTRMAXV_LTRV_MASK 0x000003FF /* LTR maximum value */ 1851#define E1000_LTRMINV_SCALE_MASK 0x00001C00 /* LTR minimum scale */ 1852#define E1000_LTRMINV_SCALE_SHIFT 10 1853/* Reg val to set scale to 1024 nsec */ 1854#define E1000_LTRMINV_SCALE_1024 2 1855/* Reg val to set scale to 32768 nsec */ 1856#define E1000_LTRMINV_SCALE_32768 3 |
| 1857#define E1000_LTRMINV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */ |
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| 1829#define E1000_LTRMAXV_SCALE_MASK 0x00001C00 /* LTR maximum scale */ 1830#define E1000_LTRMAXV_SCALE_SHIFT 10 1831/* Reg val to set scale to 1024 nsec */ 1832#define E1000_LTRMAXV_SCALE_1024 2 1833/* Reg val to set scale to 32768 nsec */ 1834#define E1000_LTRMAXV_SCALE_32768 3 | 1858#define E1000_LTRMAXV_SCALE_MASK 0x00001C00 /* LTR maximum scale */ 1859#define E1000_LTRMAXV_SCALE_SHIFT 10 1860/* Reg val to set scale to 1024 nsec */ 1861#define E1000_LTRMAXV_SCALE_1024 2 1862/* Reg val to set scale to 32768 nsec */ 1863#define E1000_LTRMAXV_SCALE_32768 3 |
| 1864#define E1000_LTRMAXV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */ |
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| 1835#define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */ 1836#define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */ 1837 1838/* Proxy Filer Control */ 1839#define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ 1840#define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */ 1841#define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ 1842#define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ --- 18 unchanged lines hidden --- | 1865#define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */ 1866#define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */ 1867 1868/* Proxy Filer Control */ 1869#define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ 1870#define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */ 1871#define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ 1872#define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ --- 18 unchanged lines hidden --- |