| e1000_defines.h (194865) | e1000_defines.h (200243) |
|---|---|
| 1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ | 1/****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 --- 16 unchanged lines hidden (view full) --- 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ |
| 33/*$FreeBSD: head/sys/dev/e1000/e1000_defines.h 194865 2009-06-24 17:41:29Z jfv $*/ | 33/*$FreeBSD: head/sys/dev/e1000/e1000_defines.h 200243 2009-12-08 01:07:44Z jfv $*/ |
| 34 35#ifndef _E1000_DEFINES_H_ 36#define _E1000_DEFINES_H_ 37 38/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 39#define REQ_TX_DESCRIPTOR_MULTIPLE 8 40#define REQ_RX_DESCRIPTOR_MULTIPLE 8 41 --- 99 unchanged lines hidden (view full) --- 141#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 142#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 143#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 144/* Reserved (bits 4,5) in >= 82575 */ 145#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */ 146#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */ 147#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 148#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */ | 34 35#ifndef _E1000_DEFINES_H_ 36#define _E1000_DEFINES_H_ 37 38/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 39#define REQ_TX_DESCRIPTOR_MULTIPLE 8 40#define REQ_RX_DESCRIPTOR_MULTIPLE 8 41 --- 99 unchanged lines hidden (view full) --- 141#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 142#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 143#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 144/* Reserved (bits 4,5) in >= 82575 */ 145#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */ 146#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */ 147#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 148#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */ |
| 149#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */ | 149#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ |
| 150/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ 151#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 152#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 153#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ | 150/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ 151#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 152#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 153#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ |
| 154#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ | 154#define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */ |
| 155#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 156#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 157#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 158/* Physical Func Reset Done Indication */ 159#define E1000_CTRL_EXT_PFRSTD 0x00004000 160#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 161#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 162#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ 163#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 | 155#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 156#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 157#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 158/* Physical Func Reset Done Indication */ 159#define E1000_CTRL_EXT_PFRSTD 0x00004000 160#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 161#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 162#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ 163#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
| 164#define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /*82580 bit 24:22*/ 165#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 |
|
| 164#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 165#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 166#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 167#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 168#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 169#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 170#define E1000_CTRL_EXT_EIAME 0x01000000 171#define E1000_CTRL_EXT_IRCA 0x00000001 --- 209 unchanged lines hidden (view full) --- 381#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 382#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 383 384/* SWFW_SYNC Definitions */ 385#define E1000_SWFW_EEP_SM 0x01 386#define E1000_SWFW_PHY0_SM 0x02 387#define E1000_SWFW_PHY1_SM 0x04 388#define E1000_SWFW_CSR_SM 0x08 | 166#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 167#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 168#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 169#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 170#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 171#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 172#define E1000_CTRL_EXT_EIAME 0x01000000 173#define E1000_CTRL_EXT_IRCA 0x00000001 --- 209 unchanged lines hidden (view full) --- 383#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 384#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 385 386/* SWFW_SYNC Definitions */ 387#define E1000_SWFW_EEP_SM 0x01 388#define E1000_SWFW_PHY0_SM 0x02 389#define E1000_SWFW_PHY1_SM 0x04 390#define E1000_SWFW_CSR_SM 0x08 |
| 391#define E1000_SWFW_PHY2_SM 0x20 392#define E1000_SWFW_PHY3_SM 0x40 |
|
| 389 390/* FACTPS Definitions */ 391#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */ 392/* Device Control */ 393#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 394#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 395#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 396#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ --- 295 unchanged lines hidden (view full) --- 692#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 693 694#define ETHERNET_FCS_SIZE 4 695#define MAX_JUMBO_FRAME_SIZE 0x3F00 696 697/* Extended Configuration Control and Size */ 698#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 699#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 | 393 394/* FACTPS Definitions */ 395#define E1000_FACTPS_LFS 0x40000000 /* LAN Function Select */ 396/* Device Control */ 397#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 398#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 399#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 400#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ --- 295 unchanged lines hidden (view full) --- 696#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 697 698#define ETHERNET_FCS_SIZE 4 699#define MAX_JUMBO_FRAME_SIZE 0x3F00 700 701/* Extended Configuration Control and Size */ 702#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 703#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 |
| 704#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 |
|
| 700#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 701#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 702#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 703#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 704#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 705 706#define E1000_PHY_CTRL_SPD_EN 0x00000001 707#define E1000_PHY_CTRL_D0A_LPLU 0x00000002 --- 56 unchanged lines hidden (view full) --- 764#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 765#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 766#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 767#define E1000_ICR_TXD_LOW 0x00008000 768#define E1000_ICR_SRPD 0x00010000 769#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 770#define E1000_ICR_MNG 0x00040000 /* Manageability event */ 771#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ | 705#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 706#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 707#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 708#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 709#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 710 711#define E1000_PHY_CTRL_SPD_EN 0x00000001 712#define E1000_PHY_CTRL_D0A_LPLU 0x00000002 --- 56 unchanged lines hidden (view full) --- 769#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 770#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 771#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 772#define E1000_ICR_TXD_LOW 0x00008000 773#define E1000_ICR_SRPD 0x00010000 774#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 775#define E1000_ICR_MNG 0x00040000 /* Manageability event */ 776#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ |
| 777#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ |
|
| 772#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver 773 * should claim the interrupt */ 774#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */ 775#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */ 776#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */ 777#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 778#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */ 779#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */ --- 4 unchanged lines hidden (view full) --- 784 * an interrupt */ 785#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 786#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ 787#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 788#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 789#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 790#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 791#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ | 778#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver 779 * should claim the interrupt */ 780#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */ 781#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */ 782#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */ 783#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 784#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */ 785#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */ --- 4 unchanged lines hidden (view full) --- 790 * an interrupt */ 791#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 792#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ 793#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 794#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 795#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 796#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 797#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ |
| 798#define E1000_ICR_FER 0x00400000 /* Fatal Error */ |
|
| 792 793/* PBA ECC Register */ 794#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 795#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 796#define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ 797#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 798#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ 799 --- 55 unchanged lines hidden (view full) --- 855#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 856#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 857#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 858#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 859#define E1000_IMS_SRPD E1000_ICR_SRPD 860#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 861#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 862#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ | 799 800/* PBA ECC Register */ 801#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 802#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 803#define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ 804#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 805#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ 806 --- 55 unchanged lines hidden (view full) --- 862#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 863#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 864#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 865#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 866#define E1000_IMS_SRPD E1000_ICR_SRPD 867#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 868#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 869#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ |
| 870#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ |
|
| 863#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO 864 * parity error */ 865#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO 866 * parity error */ 867#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer 868 * parity error */ 869#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity 870 * error */ --- 5 unchanged lines hidden (view full) --- 876#define E1000_IMS_PHYINT E1000_ICR_PHYINT 877#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 878#define E1000_IMS_EPRST E1000_ICR_EPRST 879#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 880#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 881#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 882#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 883#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ | 871#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO 872 * parity error */ 873#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO 874 * parity error */ 875#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer 876 * parity error */ 877#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity 878 * error */ --- 5 unchanged lines hidden (view full) --- 884#define E1000_IMS_PHYINT E1000_ICR_PHYINT 885#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 886#define E1000_IMS_EPRST E1000_ICR_EPRST 887#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 888#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 889#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 890#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 891#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ |
| 892#define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */ |
|
| 884 885/* Extended Interrupt Mask Set */ 886#define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 887#define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 888#define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 889#define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 890#define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 891#define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ --- 16 unchanged lines hidden (view full) --- 908#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 909#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 910#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 911#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 912#define E1000_ICS_SRPD E1000_ICR_SRPD 913#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 914#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 915#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ | 893 894/* Extended Interrupt Mask Set */ 895#define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 896#define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 897#define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 898#define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 899#define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 900#define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ --- 16 unchanged lines hidden (view full) --- 917#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 918#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 919#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 920#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 921#define E1000_ICS_SRPD E1000_ICR_SRPD 922#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 923#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 924#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ |
| 925#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ |
|
| 916#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO 917 * parity error */ 918#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO 919 * parity error */ 920#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer 921 * parity error */ 922#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity 923 * error */ --- 65 unchanged lines hidden (view full) --- 989#define E1000_ERR_PHY_TYPE 6 990#define E1000_ERR_RESET 9 991#define E1000_ERR_MASTER_REQUESTS_PENDING 10 992#define E1000_ERR_HOST_INTERFACE_COMMAND 11 993#define E1000_BLK_PHY_RESET 12 994#define E1000_ERR_SWFW_SYNC 13 995#define E1000_NOT_IMPLEMENTED 14 996#define E1000_ERR_MBX 15 | 926#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO 927 * parity error */ 928#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO 929 * parity error */ 930#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer 931 * parity error */ 932#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity 933 * error */ --- 65 unchanged lines hidden (view full) --- 999#define E1000_ERR_PHY_TYPE 6 1000#define E1000_ERR_RESET 9 1001#define E1000_ERR_MASTER_REQUESTS_PENDING 10 1002#define E1000_ERR_HOST_INTERFACE_COMMAND 11 1003#define E1000_BLK_PHY_RESET 12 1004#define E1000_ERR_SWFW_SYNC 13 1005#define E1000_NOT_IMPLEMENTED 14 1006#define E1000_ERR_MBX 15 |
| 1007#define E1000_ERFUSE_FAILURE 16 |
|
| 997 998/* Loop limit on how long we wait for auto-negotiation to complete */ 999#define FIBER_LINK_UP_LIMIT 50 1000#define COPPER_LINK_UP_LIMIT 10 1001#define PHY_AUTO_NEG_LIMIT 45 1002#define PHY_FORCE_LIMIT 20 1003/* Number of 100 microseconds we wait for PCI Express master disable */ 1004#define MASTER_DISABLE_TIMEOUT 800 --- 26 unchanged lines hidden (view full) --- 1031#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 1032#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 1033#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 1034#define E1000_RXCW_CC 0x10000000 /* Receive config change */ 1035#define E1000_RXCW_C 0x20000000 /* Receive config */ 1036#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 1037#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 1038 | 1008 1009/* Loop limit on how long we wait for auto-negotiation to complete */ 1010#define FIBER_LINK_UP_LIMIT 50 1011#define COPPER_LINK_UP_LIMIT 10 1012#define PHY_AUTO_NEG_LIMIT 45 1013#define PHY_FORCE_LIMIT 20 1014/* Number of 100 microseconds we wait for PCI Express master disable */ 1015#define MASTER_DISABLE_TIMEOUT 800 --- 26 unchanged lines hidden (view full) --- 1042#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 1043#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 1044#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 1045#define E1000_RXCW_CC 0x10000000 /* Receive config change */ 1046#define E1000_RXCW_C 0x20000000 /* Receive config */ 1047#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 1048#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 1049 |
| 1050#define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */ 1051#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */ |
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| 1039 | 1052 |
| 1053#define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */ 1054#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */ 1055#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 1056#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 1057#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 1058#define E1000_TSYNCRXCTL_TYPE_ALL 0x08 1059#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 1060#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */ 1061 1062#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 1063#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 1064#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 1065#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 1066#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 1067#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 1068 1069#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 1070#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 1071#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 1072#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 1073#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 1074#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 1075#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 1076#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 1077#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 1078#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 1079#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 1080 1081#define E1000_TIMINCA_16NS_SHIFT 24 1082/* TUPLE Filtering Configuration */ 1083#define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */ 1084#define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */ 1085#define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */ 1086/* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */ 1087#define E1000_TTQF_PROTOCOL_TCP 0x0 1088/* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 1089#define E1000_TTQF_PROTOCOL_UDP 0x1 1090/* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 1091#define E1000_TTQF_PROTOCOL_SCTP 0x2 1092#define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */ 1093#define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */ 1094#define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */ 1095#define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */ 1096#define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ 1097#define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */ 1098#define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */ 1099#define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */ 1100 |
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| 1040/* PCI Express Control */ 1041#define E1000_GCR_RXD_NO_SNOOP 0x00000001 1042#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 1043#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 1044#define E1000_GCR_TXD_NO_SNOOP 0x00000008 1045#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 1046#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 1047#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 --- 174 unchanged lines hidden (view full) --- 1222#define NVM_INIT_CONTROL3_PORT_A 0x0024 1223#define NVM_CFG 0x0012 1224#define NVM_FLASH_VERSION 0x0032 1225#define NVM_ALT_MAC_ADDR_PTR 0x0037 1226#define NVM_CHECKSUM_REG 0x003F 1227 1228#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 1229#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ | 1101/* PCI Express Control */ 1102#define E1000_GCR_RXD_NO_SNOOP 0x00000001 1103#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 1104#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 1105#define E1000_GCR_TXD_NO_SNOOP 0x00000008 1106#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 1107#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 1108#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 --- 174 unchanged lines hidden (view full) --- 1283#define NVM_INIT_CONTROL3_PORT_A 0x0024 1284#define NVM_CFG 0x0012 1285#define NVM_FLASH_VERSION 0x0032 1286#define NVM_ALT_MAC_ADDR_PTR 0x0037 1287#define NVM_CHECKSUM_REG 0x003F 1288 1289#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 1290#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ |
| 1291#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 1292#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ |
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| 1230 | 1293 |
| 1294#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0) 1295 |
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| 1231/* Mask bits for fields in Word 0x0f of the NVM */ 1232#define NVM_WORD0F_PAUSE_MASK 0x3000 1233#define NVM_WORD0F_PAUSE 0x1000 1234#define NVM_WORD0F_ASM_DIR 0x2000 1235#define NVM_WORD0F_ANE 0x0800 1236#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 1237#define NVM_WORD0F_LPLU 0x0001 1238 --- 102 unchanged lines hidden (view full) --- 1341#define IGP03E1000_E_PHY_ID 0x02A80390 1342#define IFE_E_PHY_ID 0x02A80330 1343#define IFE_PLUS_E_PHY_ID 0x02A80320 1344#define IFE_C_E_PHY_ID 0x02A80310 1345#define BME1000_E_PHY_ID 0x01410CB0 1346#define BME1000_E_PHY_ID_R2 0x01410CB1 1347#define I82577_E_PHY_ID 0x01540050 1348#define I82578_E_PHY_ID 0x004DD040 | 1296/* Mask bits for fields in Word 0x0f of the NVM */ 1297#define NVM_WORD0F_PAUSE_MASK 0x3000 1298#define NVM_WORD0F_PAUSE 0x1000 1299#define NVM_WORD0F_ASM_DIR 0x2000 1300#define NVM_WORD0F_ANE 0x0800 1301#define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 1302#define NVM_WORD0F_LPLU 0x0001 1303 --- 102 unchanged lines hidden (view full) --- 1406#define IGP03E1000_E_PHY_ID 0x02A80390 1407#define IFE_E_PHY_ID 0x02A80330 1408#define IFE_PLUS_E_PHY_ID 0x02A80320 1409#define IFE_C_E_PHY_ID 0x02A80310 1410#define BME1000_E_PHY_ID 0x01410CB0 1411#define BME1000_E_PHY_ID_R2 0x01410CB1 1412#define I82577_E_PHY_ID 0x01540050 1413#define I82578_E_PHY_ID 0x004DD040 |
| 1414#define I82580_I_PHY_ID 0x015403A0 |
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| 1349#define IGP04E1000_E_PHY_ID 0x02A80391 1350#define M88_VENDOR 0x0141 1351 1352/* M88E1000 Specific Registers */ 1353#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 1354#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 1355#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 1356#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ --- 213 unchanged lines hidden (view full) --- 1570#define E1000_LSECRXCTRL_CHECK 0x1 1571#define E1000_LSECRXCTRL_STRICT 0x2 1572#define E1000_LSECRXCTRL_DROP 0x3 1573#define E1000_LSECRXCTRL_PLSH 0x00000040 1574#define E1000_LSECRXCTRL_RP 0x00000080 1575#define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33 1576 1577 | 1415#define IGP04E1000_E_PHY_ID 0x02A80391 1416#define M88_VENDOR 0x0141 1417 1418/* M88E1000 Specific Registers */ 1419#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 1420#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 1421#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 1422#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ --- 213 unchanged lines hidden (view full) --- 1636#define E1000_LSECRXCTRL_CHECK 0x1 1637#define E1000_LSECRXCTRL_STRICT 0x2 1638#define E1000_LSECRXCTRL_DROP 0x3 1639#define E1000_LSECRXCTRL_PLSH 0x00000040 1640#define E1000_LSECRXCTRL_RP 0x00000080 1641#define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33 1642 1643 |
| 1644/* DMA Coalescing register fields */ 1645#define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coalescing 1646 * Watchdog Timer */ 1647#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coalescing Receive 1648 * Threshold */ 1649#define E1000_DMACR_DMACTHR_SHIFT 16 1650#define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe 1651 * transactions */ 1652#define E1000_DMACR_DMAC_LX_SHIFT 28 1653#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ |
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| 1578 | 1654 |
| 1655#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coalescing Transmit 1656 * Threshold */ 1657 1658#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 1659 1660#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Receive Traffic Rate 1661 * Threshold */ 1662#define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rcv packet rate in 1663 * current window */ 1664 1665#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rcv Traffic 1666 * Current Cnt */ 1667 1668#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* Flow ctrl Rcv Threshold 1669 * High val */ 1670#define E1000_FCRTC_RTH_COAL_SHIFT 4 1671#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision based 1672 on DMA coal */ 1673 |
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| 1579#endif /* _E1000_DEFINES_H_ */ | 1674#endif /* _E1000_DEFINES_H_ */ |