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e1000_82575.c (235527) e1000_82575.c (238262)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2011, Intel Corporation
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/9/sys/dev/e1000/e1000_82575.c 235527 2012-05-16 22:22:52Z jfv $*/
33/*$FreeBSD: stable/9/sys/dev/e1000/e1000_82575.c 238262 2012-07-08 20:35:56Z jfv $*/
34
35/*
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82576 Gigabit Network Connection
40 * 82576 Quad Port Gigabit Mezzanine Adapter
34
35/*
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82576 Gigabit Network Connection
40 * 82576 Quad Port Gigabit Mezzanine Adapter
41 * 82580 Gigabit Network Connection
42 * I350 Gigabit Network Connection
41 */
42
43#include "e1000_api.h"
43 */
44
45#include "e1000_api.h"
46#include "e1000_i210.h"
44
45static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
46static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
47static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
48static void e1000_release_phy_82575(struct e1000_hw *hw);
49static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
50static void e1000_release_nvm_82575(struct e1000_hw *hw);
51static s32 e1000_check_for_link_82575(struct e1000_hw *hw);

--- 105 unchanged lines hidden (view full) ---

157static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
158{
159 struct e1000_phy_info *phy = &hw->phy;
160 s32 ret_val = E1000_SUCCESS;
161 u32 ctrl_ext;
162
163 DEBUGFUNC("e1000_init_phy_params_82575");
164
47
48static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
49static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
50static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
51static void e1000_release_phy_82575(struct e1000_hw *hw);
52static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
53static void e1000_release_nvm_82575(struct e1000_hw *hw);
54static s32 e1000_check_for_link_82575(struct e1000_hw *hw);

--- 105 unchanged lines hidden (view full) ---

160static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
161{
162 struct e1000_phy_info *phy = &hw->phy;
163 s32 ret_val = E1000_SUCCESS;
164 u32 ctrl_ext;
165
166 DEBUGFUNC("e1000_init_phy_params_82575");
167
168 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
169 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
170
165 if (hw->phy.media_type != e1000_media_type_copper) {
166 phy->type = e1000_phy_none;
167 goto out;
168 }
169
170 phy->ops.power_up = e1000_power_up_phy_copper;
171 phy->ops.power_down = e1000_power_down_phy_copper_82575;
172

--- 17 unchanged lines hidden (view full) ---

190 }
191
192 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
193 e1000_reset_mdicnfg_82580(hw);
194
195 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
196 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
197 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
171 if (hw->phy.media_type != e1000_media_type_copper) {
172 phy->type = e1000_phy_none;
173 goto out;
174 }
175
176 phy->ops.power_up = e1000_power_up_phy_copper;
177 phy->ops.power_down = e1000_power_down_phy_copper_82575;
178

--- 17 unchanged lines hidden (view full) ---

196 }
197
198 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
199 e1000_reset_mdicnfg_82580(hw);
200
201 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
202 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
203 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
198 } else if (hw->mac.type >= e1000_82580) {
199 phy->ops.read_reg = e1000_read_phy_reg_82580;
200 phy->ops.write_reg = e1000_write_phy_reg_82580;
201 } else {
204 } else {
202 phy->ops.read_reg = e1000_read_phy_reg_igp;
203 phy->ops.write_reg = e1000_write_phy_reg_igp;
205 switch (hw->mac.type) {
206 case e1000_82580:
207 case e1000_i350:
208 phy->ops.read_reg = e1000_read_phy_reg_82580;
209 phy->ops.write_reg = e1000_write_phy_reg_82580;
210 break;
211 case e1000_i210:
212 case e1000_i211:
213 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
214 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
215 break;
216 default:
217 phy->ops.read_reg = e1000_read_phy_reg_igp;
218 phy->ops.write_reg = e1000_write_phy_reg_igp;
219 }
204 }
205
206 /* Set phy->phy_addr and phy->id. */
207 ret_val = e1000_get_phy_id_82575(hw);
208
209 /* Verify phy id and set remaining function pointers */
210 switch (phy->id) {
211 case I347AT4_E_PHY_ID:

--- 28 unchanged lines hidden (view full) ---

240 phy->ops.check_polarity = e1000_check_polarity_82577;
241 phy->ops.force_speed_duplex =
242 e1000_phy_force_speed_duplex_82577;
243 phy->ops.get_cable_length = e1000_get_cable_length_82577;
244 phy->ops.get_info = e1000_get_phy_info_82577;
245 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
246 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
247 break;
220 }
221
222 /* Set phy->phy_addr and phy->id. */
223 ret_val = e1000_get_phy_id_82575(hw);
224
225 /* Verify phy id and set remaining function pointers */
226 switch (phy->id) {
227 case I347AT4_E_PHY_ID:

--- 28 unchanged lines hidden (view full) ---

256 phy->ops.check_polarity = e1000_check_polarity_82577;
257 phy->ops.force_speed_duplex =
258 e1000_phy_force_speed_duplex_82577;
259 phy->ops.get_cable_length = e1000_get_cable_length_82577;
260 phy->ops.get_info = e1000_get_phy_info_82577;
261 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
262 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
263 break;
264 case I210_I_PHY_ID:
265 phy->type = e1000_phy_i210;
266 phy->ops.check_polarity = e1000_check_polarity_m88;
267 phy->ops.get_info = e1000_get_phy_info_m88;
268 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
269 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
270 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
271 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
272 break;
248 default:
249 ret_val = -E1000_ERR_PHY;
250 goto out;
251 }
252
253out:
254 return ret_val;
255}

--- 20 unchanged lines hidden (view full) ---

276
277 /* Just in case size is out of range, cap it to the largest
278 * EEPROM size supported
279 */
280 if (size > 15)
281 size = 15;
282
283 nvm->word_size = 1 << size;
273 default:
274 ret_val = -E1000_ERR_PHY;
275 goto out;
276 }
277
278out:
279 return ret_val;
280}

--- 20 unchanged lines hidden (view full) ---

301
302 /* Just in case size is out of range, cap it to the largest
303 * EEPROM size supported
304 */
305 if (size > 15)
306 size = 15;
307
308 nvm->word_size = 1 << size;
284 nvm->opcode_bits = 8;
285 nvm->delay_usec = 1;
286 switch (nvm->override) {
287 case e1000_nvm_override_spi_large:
288 nvm->page_size = 32;
289 nvm->address_bits = 16;
290 break;
291 case e1000_nvm_override_spi_small:
292 nvm->page_size = 8;
293 nvm->address_bits = 8;
294 break;
295 default:
296 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
297 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
298 break;
299 }
309 if (hw->mac.type < e1000_i210) {
310 nvm->opcode_bits = 8;
311 nvm->delay_usec = 1;
300
312
301 nvm->type = e1000_nvm_eeprom_spi;
313 switch (nvm->override) {
314 case e1000_nvm_override_spi_large:
315 nvm->page_size = 32;
316 nvm->address_bits = 16;
317 break;
318 case e1000_nvm_override_spi_small:
319 nvm->page_size = 8;
320 nvm->address_bits = 8;
321 break;
322 default:
323 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
324 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
325 16 : 8;
326 break;
327 }
328 if (nvm->word_size == (1 << 15))
329 nvm->page_size = 128;
302
330
303 if (nvm->word_size == (1 << 15))
304 nvm->page_size = 128;
305
331 nvm->type = e1000_nvm_eeprom_spi;
332 } else {
333 nvm->type = e1000_nvm_flash_hw;
334 }
306 /* Function Pointers */
307 nvm->ops.acquire = e1000_acquire_nvm_82575;
308 nvm->ops.release = e1000_release_nvm_82575;
309 if (nvm->word_size < (1 << 15))
310 nvm->ops.read = e1000_read_nvm_eerd;
311 else
312 nvm->ops.read = e1000_read_nvm_spi;
313
314 nvm->ops.write = e1000_write_nvm_spi;
315 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
316 nvm->ops.update = e1000_update_nvm_checksum_generic;
317 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
318
335 /* Function Pointers */
336 nvm->ops.acquire = e1000_acquire_nvm_82575;
337 nvm->ops.release = e1000_release_nvm_82575;
338 if (nvm->word_size < (1 << 15))
339 nvm->ops.read = e1000_read_nvm_eerd;
340 else
341 nvm->ops.read = e1000_read_nvm_spi;
342
343 nvm->ops.write = e1000_write_nvm_spi;
344 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
345 nvm->ops.update = e1000_update_nvm_checksum_generic;
346 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
347
319 /* override genric family function pointers for specific descendants */
348 /* override generic family function pointers for specific descendants */
320 switch (hw->mac.type) {
321 case e1000_82580:
322 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
323 nvm->ops.update = e1000_update_nvm_checksum_82580;
324 break;
325 case e1000_i350:
326 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
327 nvm->ops.update = e1000_update_nvm_checksum_i350;

--- 35 unchanged lines hidden (view full) ---

363 }
364
365 /* Set if part includes ASF firmware */
366 mac->asf_firmware_present = TRUE;
367 /* FWSM register */
368 mac->has_fwsm = TRUE;
369 /* ARC supported; valid only if manageability features are enabled. */
370 mac->arc_subsystem_valid =
349 switch (hw->mac.type) {
350 case e1000_82580:
351 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
352 nvm->ops.update = e1000_update_nvm_checksum_82580;
353 break;
354 case e1000_i350:
355 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
356 nvm->ops.update = e1000_update_nvm_checksum_i350;

--- 35 unchanged lines hidden (view full) ---

392 }
393
394 /* Set if part includes ASF firmware */
395 mac->asf_firmware_present = TRUE;
396 /* FWSM register */
397 mac->has_fwsm = TRUE;
398 /* ARC supported; valid only if manageability features are enabled. */
399 mac->arc_subsystem_valid =
371 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
372 ? TRUE : FALSE;
400 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
373
374 /* Function pointers */
375
376 /* bus type/speed/width */
377 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
378 /* reset */
379 if (mac->type >= e1000_82580)
380 mac->ops.reset_hw = e1000_reset_hw_82580;

--- 8 unchanged lines hidden (view full) ---

389 (hw->phy.media_type == e1000_media_type_copper)
390 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
391 /* physical interface shutdown */
392 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
393 /* physical interface power up */
394 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
395 /* check for link */
396 mac->ops.check_for_link = e1000_check_for_link_82575;
401
402 /* Function pointers */
403
404 /* bus type/speed/width */
405 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
406 /* reset */
407 if (mac->type >= e1000_82580)
408 mac->ops.reset_hw = e1000_reset_hw_82580;

--- 8 unchanged lines hidden (view full) ---

417 (hw->phy.media_type == e1000_media_type_copper)
418 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
419 /* physical interface shutdown */
420 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
421 /* physical interface power up */
422 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
423 /* check for link */
424 mac->ops.check_for_link = e1000_check_for_link_82575;
397 /* receive address register setting */
398 mac->ops.rar_set = e1000_rar_set_generic;
399 /* read mac address */
400 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
401 /* configure collision distance */
402 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
403 /* multicast address update */
404 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
405 if (hw->mac.type == e1000_i350) {
406 /* writing VFTA */

--- 16 unchanged lines hidden (view full) ---

423 mac->ops.cleanup_led = e1000_cleanup_led_generic;
424 /* turn on/off LED */
425 mac->ops.led_on = e1000_led_on_generic;
426 mac->ops.led_off = e1000_led_off_generic;
427 /* clear hardware counters */
428 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
429 /* link info */
430 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
425 /* read mac address */
426 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
427 /* configure collision distance */
428 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
429 /* multicast address update */
430 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
431 if (hw->mac.type == e1000_i350) {
432 /* writing VFTA */

--- 16 unchanged lines hidden (view full) ---

449 mac->ops.cleanup_led = e1000_cleanup_led_generic;
450 /* turn on/off LED */
451 mac->ops.led_on = e1000_led_on_generic;
452 mac->ops.led_off = e1000_led_off_generic;
453 /* clear hardware counters */
454 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
455 /* link info */
456 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
457 /* acquire SW_FW sync */
458 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
459 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
460 if (mac->type >= e1000_i210) {
461 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
462 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
463 }
431
432 /* set lan id for port to determine which phy lock to use */
433 hw->mac.ops.set_lan_id(hw);
434
435 return E1000_SUCCESS;
436}
437
438/**

--- 26 unchanged lines hidden (view full) ---

465
466 if (hw->bus.func == E1000_FUNC_1)
467 mask = E1000_SWFW_PHY1_SM;
468 else if (hw->bus.func == E1000_FUNC_2)
469 mask = E1000_SWFW_PHY2_SM;
470 else if (hw->bus.func == E1000_FUNC_3)
471 mask = E1000_SWFW_PHY3_SM;
472
464
465 /* set lan id for port to determine which phy lock to use */
466 hw->mac.ops.set_lan_id(hw);
467
468 return E1000_SUCCESS;
469}
470
471/**

--- 26 unchanged lines hidden (view full) ---

498
499 if (hw->bus.func == E1000_FUNC_1)
500 mask = E1000_SWFW_PHY1_SM;
501 else if (hw->bus.func == E1000_FUNC_2)
502 mask = E1000_SWFW_PHY2_SM;
503 else if (hw->bus.func == E1000_FUNC_3)
504 mask = E1000_SWFW_PHY3_SM;
505
473 return e1000_acquire_swfw_sync_82575(hw, mask);
506 return hw->mac.ops.acquire_swfw_sync(hw, mask);
474}
475
476/**
477 * e1000_release_phy_82575 - Release rights to access PHY
478 * @hw: pointer to the HW structure
479 *
480 * A wrapper to release access rights to the correct PHY.
481 **/

--- 5 unchanged lines hidden (view full) ---

487
488 if (hw->bus.func == E1000_FUNC_1)
489 mask = E1000_SWFW_PHY1_SM;
490 else if (hw->bus.func == E1000_FUNC_2)
491 mask = E1000_SWFW_PHY2_SM;
492 else if (hw->bus.func == E1000_FUNC_3)
493 mask = E1000_SWFW_PHY3_SM;
494
507}
508
509/**
510 * e1000_release_phy_82575 - Release rights to access PHY
511 * @hw: pointer to the HW structure
512 *
513 * A wrapper to release access rights to the correct PHY.
514 **/

--- 5 unchanged lines hidden (view full) ---

520
521 if (hw->bus.func == E1000_FUNC_1)
522 mask = E1000_SWFW_PHY1_SM;
523 else if (hw->bus.func == E1000_FUNC_2)
524 mask = E1000_SWFW_PHY2_SM;
525 else if (hw->bus.func == E1000_FUNC_3)
526 mask = E1000_SWFW_PHY3_SM;
527
495 e1000_release_swfw_sync_82575(hw, mask);
528 hw->mac.ops.release_swfw_sync(hw, mask);
496}
497
498/**
499 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
500 * @hw: pointer to the HW structure
501 * @offset: register offset to be read
502 * @data: pointer to the read data
503 *

--- 287 unchanged lines hidden (view full) ---

791 * either 10 or 10/100 or 10/100/1000 at all duplexes.
792 * This is a function pointer entry point only called by
793 * PHY setup routines.
794 **/
795static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
796{
797 struct e1000_phy_info *phy = &hw->phy;
798 s32 ret_val = E1000_SUCCESS;
529}
530
531/**
532 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
533 * @hw: pointer to the HW structure
534 * @offset: register offset to be read
535 * @data: pointer to the read data
536 *

--- 287 unchanged lines hidden (view full) ---

824 * either 10 or 10/100 or 10/100/1000 at all duplexes.
825 * This is a function pointer entry point only called by
826 * PHY setup routines.
827 **/
828static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
829{
830 struct e1000_phy_info *phy = &hw->phy;
831 s32 ret_val = E1000_SUCCESS;
799 u16 data;
832 u32 data;
800
801 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
802
803 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
804
805 if (active) {
806 data |= E1000_82580_PM_D0_LPLU;
807

--- 31 unchanged lines hidden (view full) ---

839 * is used during Dx states where the power conservation is most important.
840 * During driver activity, SmartSpeed should be enabled so performance is
841 * maintained.
842 **/
843s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
844{
845 struct e1000_phy_info *phy = &hw->phy;
846 s32 ret_val = E1000_SUCCESS;
833
834 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
835
836 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
837
838 if (active) {
839 data |= E1000_82580_PM_D0_LPLU;
840

--- 31 unchanged lines hidden (view full) ---

872 * is used during Dx states where the power conservation is most important.
873 * During driver activity, SmartSpeed should be enabled so performance is
874 * maintained.
875 **/
876s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
877{
878 struct e1000_phy_info *phy = &hw->phy;
879 s32 ret_val = E1000_SUCCESS;
847 u16 data;
880 u32 data;
848
849 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
850
851 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
852
853 if (!active) {
854 data &= ~E1000_82580_PM_D3_LPLU;
855 /*

--- 57 unchanged lines hidden (view full) ---

913 /* Clear access error flag */
914 E1000_WRITE_REG(hw, E1000_EECD, eecd |
915 E1000_EECD_BLOCKED);
916 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
917 }
918 }
919
920
881
882 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
883
884 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
885
886 if (!active) {
887 data &= ~E1000_82580_PM_D3_LPLU;
888 /*

--- 57 unchanged lines hidden (view full) ---

946 /* Clear access error flag */
947 E1000_WRITE_REG(hw, E1000_EECD, eecd |
948 E1000_EECD_BLOCKED);
949 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
950 }
951 }
952
953
921 switch (hw->mac.type) {
922 default:
923 ret_val = e1000_acquire_nvm_generic(hw);
924 }
925
954 ret_val = e1000_acquire_nvm_generic(hw);
926 if (ret_val)
927 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
928
929out:
930 return ret_val;
931}
932
933/**
934 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
935 * @hw: pointer to the HW structure
936 *
937 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
938 * then release the semaphores acquired.
939 **/
940static void e1000_release_nvm_82575(struct e1000_hw *hw)
941{
942 DEBUGFUNC("e1000_release_nvm_82575");
943
955 if (ret_val)
956 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
957
958out:
959 return ret_val;
960}
961
962/**
963 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
964 * @hw: pointer to the HW structure
965 *
966 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
967 * then release the semaphores acquired.
968 **/
969static void e1000_release_nvm_82575(struct e1000_hw *hw)
970{
971 DEBUGFUNC("e1000_release_nvm_82575");
972
944 switch (hw->mac.type) {
945 default:
946 e1000_release_nvm_generic(hw);
947 }
973 e1000_release_nvm_generic(hw);
974
948 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
949}
950
951/**
952 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
953 * @hw: pointer to the HW structure
954 * @mask: specifies which semaphore to acquire
955 *

--- 97 unchanged lines hidden (view full) ---

1053 break;
1054 msec_delay(1);
1055 timeout--;
1056 }
1057 if (!timeout)
1058 DEBUGOUT("MNG configuration cycle has not completed.\n");
1059
1060 /* If EEPROM is not marked present, init the PHY manually */
975 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
976}
977
978/**
979 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
980 * @hw: pointer to the HW structure
981 * @mask: specifies which semaphore to acquire
982 *

--- 97 unchanged lines hidden (view full) ---

1080 break;
1081 msec_delay(1);
1082 timeout--;
1083 }
1084 if (!timeout)
1085 DEBUGOUT("MNG configuration cycle has not completed.\n");
1086
1087 /* If EEPROM is not marked present, init the PHY manually */
1061 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
1088 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1062 (hw->phy.type == e1000_phy_igp_3))
1063 e1000_phy_init_script_igp3(hw);
1064
1065 return ret_val;
1066}
1067
1068/**
1069 * e1000_get_link_up_info_82575 - Get link speed/duplex info

--- 40 unchanged lines hidden (view full) ---

1110 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1111 &duplex);
1112 /*
1113 * Use this flag to determine if link needs to be checked or
1114 * not. If we have link clear the flag so that we do not
1115 * continue to check for link.
1116 */
1117 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1089 (hw->phy.type == e1000_phy_igp_3))
1090 e1000_phy_init_script_igp3(hw);
1091
1092 return ret_val;
1093}
1094
1095/**
1096 * e1000_get_link_up_info_82575 - Get link speed/duplex info

--- 40 unchanged lines hidden (view full) ---

1137 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1138 &duplex);
1139 /*
1140 * Use this flag to determine if link needs to be checked or
1141 * not. If we have link clear the flag so that we do not
1142 * continue to check for link.
1143 */
1144 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1145
1118 } else {
1119 ret_val = e1000_check_for_copper_link_generic(hw);
1120 }
1121
1122 return ret_val;
1123}
1124
1125/**

--- 37 unchanged lines hidden (view full) ---

1163static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1164 u16 *speed, u16 *duplex)
1165{
1166 struct e1000_mac_info *mac = &hw->mac;
1167 u32 pcs;
1168
1169 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1170
1146 } else {
1147 ret_val = e1000_check_for_copper_link_generic(hw);
1148 }
1149
1150 return ret_val;
1151}
1152
1153/**

--- 37 unchanged lines hidden (view full) ---

1191static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1192 u16 *speed, u16 *duplex)
1193{
1194 struct e1000_mac_info *mac = &hw->mac;
1195 u32 pcs;
1196
1197 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1198
1171 /* Set up defaults for the return values of this function */
1172 mac->serdes_has_link = FALSE;
1173 *speed = 0;
1174 *duplex = 0;
1175
1176 /*
1177 * Read the PCS Status register for link state. For non-copper mode,
1178 * the status register is not accurate. The PCS status register is
1179 * used instead.
1180 */
1181 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1182
1183 /*
1199 /*
1200 * Read the PCS Status register for link state. For non-copper mode,
1201 * the status register is not accurate. The PCS status register is
1202 * used instead.
1203 */
1204 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1205
1206 /*
1184 * The link up bit determines when link is up on autoneg. The sync ok
1185 * gets set once both sides sync up and agree upon link. Stable link
1186 * can be determined by checking for both link up and link sync ok
1207 * The link up bit determines when link is up on autoneg.
1187 */
1208 */
1188 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1209 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1189 mac->serdes_has_link = TRUE;
1190
1191 /* Detect and store PCS speed */
1192 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1193 *speed = SPEED_1000;
1194 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1195 *speed = SPEED_100;
1196 else
1197 *speed = SPEED_10;
1198
1199 /* Detect and store PCS duplex */
1200 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1201 *duplex = FULL_DUPLEX;
1202 else
1203 *duplex = HALF_DUPLEX;
1210 mac->serdes_has_link = TRUE;
1211
1212 /* Detect and store PCS speed */
1213 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1214 *speed = SPEED_1000;
1215 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1216 *speed = SPEED_100;
1217 else
1218 *speed = SPEED_10;
1219
1220 /* Detect and store PCS duplex */
1221 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1222 *duplex = FULL_DUPLEX;
1223 else
1224 *duplex = HALF_DUPLEX;
1225 } else {
1226 mac->serdes_has_link = FALSE;
1227 *speed = 0;
1228 *duplex = 0;
1204 }
1205
1206 return E1000_SUCCESS;
1207}
1208
1209/**
1210 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1211 * @hw: pointer to the HW structure

--- 76 unchanged lines hidden (view full) ---

1288 * When auto config read does not complete, do not
1289 * return with an error. This can happen in situations
1290 * where there is no eeprom and prevents getting link.
1291 */
1292 DEBUGOUT("Auto Read Done did not complete\n");
1293 }
1294
1295 /* If EEPROM is not present, run manual init scripts */
1229 }
1230
1231 return E1000_SUCCESS;
1232}
1233
1234/**
1235 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1236 * @hw: pointer to the HW structure

--- 76 unchanged lines hidden (view full) ---

1313 * When auto config read does not complete, do not
1314 * return with an error. This can happen in situations
1315 * where there is no eeprom and prevents getting link.
1316 */
1317 DEBUGOUT("Auto Read Done did not complete\n");
1318 }
1319
1320 /* If EEPROM is not present, run manual init scripts */
1296 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1321 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1297 e1000_reset_init_script_82575(hw);
1298
1299 /* Clear any pending interrupt events. */
1300 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1301 E1000_READ_REG(hw, E1000_ICR);
1302
1303 /* Install any alternate MAC address into RAR0 */
1304 ret_val = e1000_check_alt_mac_addr_generic(hw);

--- 86 unchanged lines hidden (view full) ---

1391
1392 ret_val = hw->phy.ops.reset(hw);
1393 if (ret_val) {
1394 DEBUGOUT("Error resetting the PHY.\n");
1395 goto out;
1396 }
1397 }
1398 switch (hw->phy.type) {
1322 e1000_reset_init_script_82575(hw);
1323
1324 /* Clear any pending interrupt events. */
1325 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1326 E1000_READ_REG(hw, E1000_ICR);
1327
1328 /* Install any alternate MAC address into RAR0 */
1329 ret_val = e1000_check_alt_mac_addr_generic(hw);

--- 86 unchanged lines hidden (view full) ---

1416
1417 ret_val = hw->phy.ops.reset(hw);
1418 if (ret_val) {
1419 DEBUGOUT("Error resetting the PHY.\n");
1420 goto out;
1421 }
1422 }
1423 switch (hw->phy.type) {
1424 case e1000_phy_i210:
1399 case e1000_phy_m88:
1400 if (hw->phy.id == I347AT4_E_PHY_ID ||
1401 hw->phy.id == M88E1112_E_PHY_ID ||
1402 hw->phy.id == M88E1340M_E_PHY_ID)
1403 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1404 else
1405 ret_val = e1000_copper_link_setup_m88(hw);
1406 break;

--- 193 unchanged lines hidden (view full) ---

1600 init_ctrl_wd_3_offset =
1601 NVM_82580_LAN_FUNC_OFFSET(lan_id) +
1602 NVM_INIT_CONTROL3_PORT_A;
1603 init_ctrl_wd_3_bit_offset =
1604 NVM_WORD24_82580_LNK_MODE_OFFSET;
1605 }
1606 /* Read Init Control Word #3*/
1607 hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3);
1425 case e1000_phy_m88:
1426 if (hw->phy.id == I347AT4_E_PHY_ID ||
1427 hw->phy.id == M88E1112_E_PHY_ID ||
1428 hw->phy.id == M88E1340M_E_PHY_ID)
1429 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1430 else
1431 ret_val = e1000_copper_link_setup_m88(hw);
1432 break;

--- 193 unchanged lines hidden (view full) ---

1626 init_ctrl_wd_3_offset =
1627 NVM_82580_LAN_FUNC_OFFSET(lan_id) +
1628 NVM_INIT_CONTROL3_PORT_A;
1629 init_ctrl_wd_3_bit_offset =
1630 NVM_WORD24_82580_LNK_MODE_OFFSET;
1631 }
1632 /* Read Init Control Word #3*/
1633 hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3);
1634
1635 /*
1636 * Align link mode bits to
1637 * their CTRL_EXT location.
1638 */
1608 current_link_mode = init_ctrl_wd_3;
1639 current_link_mode = init_ctrl_wd_3;
1640 current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET -
1641 init_ctrl_wd_3_bit_offset);
1642 current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK;
1643
1609 /*
1610 * Switch to CSR for all but internal PHY.
1611 */
1644 /*
1645 * Switch to CSR for all but internal PHY.
1646 */
1612 if ((init_ctrl_wd_3 << (E1000_CTRL_EXT_LINK_MODE_OFFSET -
1613 init_ctrl_wd_3_bit_offset)) !=
1614 E1000_CTRL_EXT_LINK_MODE_GMII) {
1615 current_link_mode = ctrl_ext;
1616 init_ctrl_wd_3_bit_offset =
1617 E1000_CTRL_EXT_LINK_MODE_OFFSET;
1618 }
1647 if (current_link_mode != E1000_CTRL_EXT_LINK_MODE_GMII)
1648 /* Take link mode from CSR */
1649 current_link_mode = ctrl_ext &
1650 E1000_CTRL_EXT_LINK_MODE_MASK;
1619 } else {
1620 /* Take link mode from CSR */
1651 } else {
1652 /* Take link mode from CSR */
1621 current_link_mode = ctrl_ext;
1622 init_ctrl_wd_3_bit_offset = E1000_CTRL_EXT_LINK_MODE_OFFSET;
1653 current_link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1623 }
1624
1654 }
1655
1625 /*
1626 * Align link mode bits to
1627 * their CTRL_EXT location.
1628 */
1629 current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET -
1630 init_ctrl_wd_3_bit_offset);
1631 current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK;
1632
1633 switch (current_link_mode) {
1634
1635 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1636 hw->phy.media_type = e1000_media_type_internal_serdes;
1637 current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX;
1638 break;
1639 case E1000_CTRL_EXT_LINK_MODE_GMII:
1640 hw->phy.media_type = e1000_media_type_copper;

--- 685 unchanged lines hidden (view full) ---

2326 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2327 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2328 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2329 E1000_WRITE_FLUSH(hw);
2330
2331 msec_delay(10);
2332
2333 /* Determine whether or not a global dev reset is requested */
1656 switch (current_link_mode) {
1657
1658 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1659 hw->phy.media_type = e1000_media_type_internal_serdes;
1660 current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX;
1661 break;
1662 case E1000_CTRL_EXT_LINK_MODE_GMII:
1663 hw->phy.media_type = e1000_media_type_copper;

--- 685 unchanged lines hidden (view full) ---

2349 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2350 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2351 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2352 E1000_WRITE_FLUSH(hw);
2353
2354 msec_delay(10);
2355
2356 /* Determine whether or not a global dev reset is requested */
2334 if (global_device_reset && e1000_acquire_swfw_sync_82575(hw,
2357 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2335 swmbsw_mask))
2336 global_device_reset = FALSE;
2337
2338 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2339 E1000_STAT_DEV_RST_SET))
2340 ctrl |= E1000_CTRL_DEV_RST;
2341 else
2342 ctrl |= E1000_CTRL_RST;

--- 11 unchanged lines hidden (view full) ---

2354 * When auto config read does not complete, do not
2355 * return with an error. This can happen in situations
2356 * where there is no eeprom and prevents getting link.
2357 */
2358 DEBUGOUT("Auto Read Done did not complete\n");
2359 }
2360
2361 /* If EEPROM is not present, run manual init scripts */
2358 swmbsw_mask))
2359 global_device_reset = FALSE;
2360
2361 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2362 E1000_STAT_DEV_RST_SET))
2363 ctrl |= E1000_CTRL_DEV_RST;
2364 else
2365 ctrl |= E1000_CTRL_RST;

--- 11 unchanged lines hidden (view full) ---

2377 * When auto config read does not complete, do not
2378 * return with an error. This can happen in situations
2379 * where there is no eeprom and prevents getting link.
2380 */
2381 DEBUGOUT("Auto Read Done did not complete\n");
2382 }
2383
2384 /* If EEPROM is not present, run manual init scripts */
2362 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
2385 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
2363 e1000_reset_init_script_82575(hw);
2364
2365 /* clear global device reset status bit */
2366 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2367
2368 /* Clear any pending interrupt events. */
2369 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2370 E1000_READ_REG(hw, E1000_ICR);
2371
2372 ret_val = e1000_reset_mdicnfg_82580(hw);
2373 if (ret_val)
2374 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2375
2376 /* Install any alternate MAC address into RAR0 */
2377 ret_val = e1000_check_alt_mac_addr_generic(hw);
2378
2379 /* Release semaphore */
2380 if (global_device_reset)
2386 e1000_reset_init_script_82575(hw);
2387
2388 /* clear global device reset status bit */
2389 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2390
2391 /* Clear any pending interrupt events. */
2392 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2393 E1000_READ_REG(hw, E1000_ICR);
2394
2395 ret_val = e1000_reset_mdicnfg_82580(hw);
2396 if (ret_val)
2397 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2398
2399 /* Install any alternate MAC address into RAR0 */
2400 ret_val = e1000_check_alt_mac_addr_generic(hw);
2401
2402 /* Release semaphore */
2403 if (global_device_reset)
2381 e1000_release_swfw_sync_82575(hw, swmbsw_mask);
2404 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2382
2383 return ret_val;
2384}
2385
2386/**
2387 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2388 * @data: data received by reading RXPBS register
2389 *

--- 143 unchanged lines hidden (view full) ---

2533 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2534
2535 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2536 if (ret_val) {
2537 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2538 goto out;
2539 }
2540
2405
2406 return ret_val;
2407}
2408
2409/**
2410 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2411 * @data: data received by reading RXPBS register
2412 *

--- 143 unchanged lines hidden (view full) ---

2556 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2557
2558 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2559 if (ret_val) {
2560 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2561 goto out;
2562 }
2563
2541 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2564 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2542 /* set compatibility bit to validate checksums appropriately */
2543 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2544 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2545 &nvm_data);
2546 if (ret_val) {
2547 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2548 goto out;
2549 }

--- 182 unchanged lines hidden (view full) ---

2732
2733 return ret_val;
2734}
2735
2736/**
2737 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
2738 * @hw: pointer to hardware structure
2739 * @byte_offset: byte offset to read
2565 /* set compatibility bit to validate checksums appropriately */
2566 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2567 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2568 &nvm_data);
2569 if (ret_val) {
2570 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2571 goto out;
2572 }

--- 182 unchanged lines hidden (view full) ---

2755
2756 return ret_val;
2757}
2758
2759/**
2760 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
2761 * @hw: pointer to hardware structure
2762 * @byte_offset: byte offset to read
2763 * @dev_addr: device address
2740 * @data: value read
2741 *
2742 * Performs byte read operation over I2C interface at
2743 * a specified device address.
2744 **/
2745s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2746 u8 dev_addr, u8 *data)
2747{
2748 s32 status = E1000_SUCCESS;
2749 u32 max_retry = 10;
2750 u32 retry = 1;
2751 u16 swfw_mask = 0;
2752
2764 * @data: value read
2765 *
2766 * Performs byte read operation over I2C interface at
2767 * a specified device address.
2768 **/
2769s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2770 u8 dev_addr, u8 *data)
2771{
2772 s32 status = E1000_SUCCESS;
2773 u32 max_retry = 10;
2774 u32 retry = 1;
2775 u16 swfw_mask = 0;
2776
2753 bool nack = 1;
2777 bool nack = TRUE;
2754
2755 DEBUGFUNC("e1000_read_i2c_byte_generic");
2756
2757 swfw_mask = E1000_SWFW_PHY0_SM;
2758
2759 do {
2778
2779 DEBUGFUNC("e1000_read_i2c_byte_generic");
2780
2781 swfw_mask = E1000_SWFW_PHY0_SM;
2782
2783 do {
2760 if (e1000_acquire_swfw_sync_82575(hw, swfw_mask)
2784 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
2761 != E1000_SUCCESS) {
2762 status = E1000_ERR_SWFW_SYNC;
2763 goto read_byte_out;
2764 }
2765
2766 e1000_i2c_start(hw);
2767
2768 /* Device Address and write indication */

--- 31 unchanged lines hidden (view full) ---

2800 status = e1000_clock_out_i2c_bit(hw, nack);
2801 if (status != E1000_SUCCESS)
2802 goto fail;
2803
2804 e1000_i2c_stop(hw);
2805 break;
2806
2807fail:
2785 != E1000_SUCCESS) {
2786 status = E1000_ERR_SWFW_SYNC;
2787 goto read_byte_out;
2788 }
2789
2790 e1000_i2c_start(hw);
2791
2792 /* Device Address and write indication */

--- 31 unchanged lines hidden (view full) ---

2824 status = e1000_clock_out_i2c_bit(hw, nack);
2825 if (status != E1000_SUCCESS)
2826 goto fail;
2827
2828 e1000_i2c_stop(hw);
2829 break;
2830
2831fail:
2808 e1000_release_swfw_sync_82575(hw, swfw_mask);
2832 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2809 msec_delay(100);
2810 e1000_i2c_bus_clear(hw);
2811 retry++;
2812 if (retry < max_retry)
2813 DEBUGOUT("I2C byte read error - Retrying.\n");
2814 else
2815 DEBUGOUT("I2C byte read error.\n");
2816
2817 } while (retry < max_retry);
2818
2833 msec_delay(100);
2834 e1000_i2c_bus_clear(hw);
2835 retry++;
2836 if (retry < max_retry)
2837 DEBUGOUT("I2C byte read error - Retrying.\n");
2838 else
2839 DEBUGOUT("I2C byte read error.\n");
2840
2841 } while (retry < max_retry);
2842
2819 e1000_release_swfw_sync_82575(hw, swfw_mask);
2843 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2820
2821read_byte_out:
2822
2823 return status;
2824}
2825
2826/**
2827 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
2828 * @hw: pointer to hardware structure
2829 * @byte_offset: byte offset to write
2844
2845read_byte_out:
2846
2847 return status;
2848}
2849
2850/**
2851 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
2852 * @hw: pointer to hardware structure
2853 * @byte_offset: byte offset to write
2854 * @dev_addr: device address
2830 * @data: value to write
2831 *
2832 * Performs byte write operation over I2C interface at
2833 * a specified device address.
2834 **/
2835s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2836 u8 dev_addr, u8 data)
2837{
2838 s32 status = E1000_SUCCESS;
2839 u32 max_retry = 1;
2840 u32 retry = 0;
2841 u16 swfw_mask = 0;
2842
2843 DEBUGFUNC("e1000_write_i2c_byte_generic");
2844
2845 swfw_mask = E1000_SWFW_PHY0_SM;
2846
2855 * @data: value to write
2856 *
2857 * Performs byte write operation over I2C interface at
2858 * a specified device address.
2859 **/
2860s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2861 u8 dev_addr, u8 data)
2862{
2863 s32 status = E1000_SUCCESS;
2864 u32 max_retry = 1;
2865 u32 retry = 0;
2866 u16 swfw_mask = 0;
2867
2868 DEBUGFUNC("e1000_write_i2c_byte_generic");
2869
2870 swfw_mask = E1000_SWFW_PHY0_SM;
2871
2847 if (e1000_acquire_swfw_sync_82575(hw, swfw_mask) != E1000_SUCCESS) {
2872 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
2848 status = E1000_ERR_SWFW_SYNC;
2849 goto write_byte_out;
2850 }
2851
2852 do {
2853 e1000_i2c_start(hw);
2854
2855 status = e1000_clock_out_i2c_byte(hw, dev_addr);

--- 27 unchanged lines hidden (view full) ---

2883 e1000_i2c_bus_clear(hw);
2884 retry++;
2885 if (retry < max_retry)
2886 DEBUGOUT("I2C byte write error - Retrying.\n");
2887 else
2888 DEBUGOUT("I2C byte write error.\n");
2889 } while (retry < max_retry);
2890
2873 status = E1000_ERR_SWFW_SYNC;
2874 goto write_byte_out;
2875 }
2876
2877 do {
2878 e1000_i2c_start(hw);
2879
2880 status = e1000_clock_out_i2c_byte(hw, dev_addr);

--- 27 unchanged lines hidden (view full) ---

2908 e1000_i2c_bus_clear(hw);
2909 retry++;
2910 if (retry < max_retry)
2911 DEBUGOUT("I2C byte write error - Retrying.\n");
2912 else
2913 DEBUGOUT("I2C byte write error.\n");
2914 } while (retry < max_retry);
2915
2891 e1000_release_swfw_sync_82575(hw, swfw_mask);
2916 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2892
2893write_byte_out:
2894
2895 return status;
2896}
2897
2898/**
2899 * e1000_i2c_start - Sets I2C start condition

--- 115 unchanged lines hidden (view full) ---

3015 * Clocks in/out one bit via I2C data/clock
3016 **/
3017static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3018{
3019 s32 status = E1000_SUCCESS;
3020 u32 i = 0;
3021 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3022 u32 timeout = 10;
2917
2918write_byte_out:
2919
2920 return status;
2921}
2922
2923/**
2924 * e1000_i2c_start - Sets I2C start condition

--- 115 unchanged lines hidden (view full) ---

3040 * Clocks in/out one bit via I2C data/clock
3041 **/
3042static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3043{
3044 s32 status = E1000_SUCCESS;
3045 u32 i = 0;
3046 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3047 u32 timeout = 10;
3023 bool ack = 1;
3048 bool ack = TRUE;
3024
3025 DEBUGFUNC("e1000_get_i2c_ack");
3026
3027 e1000_raise_i2c_clk(hw, &i2cctl);
3028
3029 /* Minimum high period of clock is 4us */
3030 usec_delay(E1000_I2C_T_HIGH);
3031
3032 /* Wait until SCL returns high */
3033 for (i = 0; i < timeout; i++) {
3034 usec_delay(1);
3035 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3036 if (i2cctl & E1000_I2C_CLK_IN)
3037 break;
3038 }
3039 if (!(i2cctl & E1000_I2C_CLK_IN))
3040 return E1000_ERR_I2C;
3041
3042 ack = e1000_get_i2c_data(&i2cctl);
3049
3050 DEBUGFUNC("e1000_get_i2c_ack");
3051
3052 e1000_raise_i2c_clk(hw, &i2cctl);
3053
3054 /* Minimum high period of clock is 4us */
3055 usec_delay(E1000_I2C_T_HIGH);
3056
3057 /* Wait until SCL returns high */
3058 for (i = 0; i < timeout; i++) {
3059 usec_delay(1);
3060 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3061 if (i2cctl & E1000_I2C_CLK_IN)
3062 break;
3063 }
3064 if (!(i2cctl & E1000_I2C_CLK_IN))
3065 return E1000_ERR_I2C;
3066
3067 ack = e1000_get_i2c_data(&i2cctl);
3043 if (ack == 1) {
3068 if (ack) {
3044 DEBUGOUT("I2C ack was not received.\n");
3045 status = E1000_ERR_I2C;
3046 }
3047
3048 e1000_lower_i2c_clk(hw, &i2cctl);
3049
3050 /* Minimum low period of clock is 4.7 us */
3051 usec_delay(E1000_I2C_T_LOW);

--- 201 unchanged lines hidden --- 		3069 DEBUGOUT("I2C ack was not received.\n");
3070 status = E1000_ERR_I2C;
3071 }
3072
3073 e1000_lower_i2c_clk(hw, &i2cctl);
3074
3075 /* Minimum low period of clock is 4.7 us */
3076 usec_delay(E1000_I2C_T_LOW);

--- 201 unchanged lines hidden ---