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e1000_82575.c (213234) e1000_82575.c (218530)
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 213234 2010-09-28 00:13:15Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 218530 2011-02-11 01:00:26Z jfv $*/
34
35/*
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82575GB Gigabit Network Connection
40 * 82576 Gigabit Network Connection
41 * 82576 Quad Port Gigabit Mezzanine Adapter

--- 13 unchanged lines hidden (view full) ---

55static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
56 u16 *duplex);
57static s32 e1000_init_hw_82575(struct e1000_hw *hw);
58static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
60 u16 *data);
61static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
62static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
34
35/*
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82575GB Gigabit Network Connection
40 * 82576 Gigabit Network Connection
41 * 82576 Quad Port Gigabit Mezzanine Adapter

--- 13 unchanged lines hidden (view full) ---

55static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
56 u16 *duplex);
57static s32 e1000_init_hw_82575(struct e1000_hw *hw);
58static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
60 u16 *data);
61static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
62static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
63static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
63static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
64 u32 offset, u16 *data);
64 u32 offset, u16 *data);
65static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
65static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
66 u32 offset, u16 data);
66 u32 offset, u16 data);
67static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
68 bool active);
69static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
70 bool active);
67static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
68 bool active);
69static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
70static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
71static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
72static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
73 u32 offset, u16 data);
74static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);

--- 6 unchanged lines hidden (view full) ---

81static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
82static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
83static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
84static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
85static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
86static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
87static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
88static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
71static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
72 bool active);
73static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
74static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
75static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
76static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
77 u32 offset, u16 data);
78static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);

--- 6 unchanged lines hidden (view full) ---

85static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
86static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
87static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
88static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
89static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
90static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
91static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
92static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
93static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
94static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
95static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
96 u16 offset);
97static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
98 u16 offset);
99static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
100static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
89
90static const u16 e1000_82580_rxpbs_table[] =
91 { 36, 72, 144, 1, 2, 4, 8, 16,
92 35, 70, 140 };
93#define E1000_82580_RXPBS_TABLE_SIZE \
94 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
95
96

--- 13 unchanged lines hidden (view full) ---

110
111 switch (hw->mac.type) {
112 case e1000_82575:
113 case e1000_82576:
114 reg = E1000_READ_REG(hw, E1000_MDIC);
115 ext_mdio = !!(reg & E1000_MDIC_DEST);
116 break;
117 case e1000_82580:
101
102static const u16 e1000_82580_rxpbs_table[] =
103 { 36, 72, 144, 1, 2, 4, 8, 16,
104 35, 70, 140 };
105#define E1000_82580_RXPBS_TABLE_SIZE \
106 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
107
108

--- 13 unchanged lines hidden (view full) ---

122
123 switch (hw->mac.type) {
124 case e1000_82575:
125 case e1000_82576:
126 reg = E1000_READ_REG(hw, E1000_MDIC);
127 ext_mdio = !!(reg & E1000_MDIC_DEST);
128 break;
129 case e1000_82580:
130 case e1000_i350:
118 reg = E1000_READ_REG(hw, E1000_MDICNFG);
119 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
120 break;
121 default:
122 break;
123 }
124 return ext_mdio;
125}

--- 34 unchanged lines hidden (view full) ---

160 ctrl_ext |= E1000_CTRL_I2C_ENA;
161 } else {
162 phy->ops.reset = e1000_phy_hw_reset_generic;
163 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
164 }
165
166 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
167 e1000_reset_mdicnfg_82580(hw);
131 reg = E1000_READ_REG(hw, E1000_MDICNFG);
132 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
133 break;
134 default:
135 break;
136 }
137 return ext_mdio;
138}

--- 34 unchanged lines hidden (view full) ---

173 ctrl_ext |= E1000_CTRL_I2C_ENA;
174 } else {
175 phy->ops.reset = e1000_phy_hw_reset_generic;
176 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
177 }
178
179 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
180 e1000_reset_mdicnfg_82580(hw);
168
181
169 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
170 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
171 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
172 } else if (hw->mac.type >= e1000_82580) {
173 phy->ops.read_reg = e1000_read_phy_reg_82580;
174 phy->ops.write_reg = e1000_write_phy_reg_82580;
175 } else {
176 phy->ops.read_reg = e1000_read_phy_reg_igp;
177 phy->ops.write_reg = e1000_write_phy_reg_igp;
178 }
179
180 /* Set phy->phy_addr and phy->id. */
181 ret_val = e1000_get_phy_id_82575(hw);
182
183 /* Verify phy id and set remaining function pointers */
184 switch (phy->id) {
182 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
183 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
184 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
185 } else if (hw->mac.type >= e1000_82580) {
186 phy->ops.read_reg = e1000_read_phy_reg_82580;
187 phy->ops.write_reg = e1000_write_phy_reg_82580;
188 } else {
189 phy->ops.read_reg = e1000_read_phy_reg_igp;
190 phy->ops.write_reg = e1000_write_phy_reg_igp;
191 }
192
193 /* Set phy->phy_addr and phy->id. */
194 ret_val = e1000_get_phy_id_82575(hw);
195
196 /* Verify phy id and set remaining function pointers */
197 switch (phy->id) {
198 case I347AT4_E_PHY_ID:
199 case M88E1112_E_PHY_ID:
185 case M88E1111_I_PHY_ID:
186 phy->type = e1000_phy_m88;
187 phy->ops.check_polarity = e1000_check_polarity_m88;
188 phy->ops.get_info = e1000_get_phy_info_m88;
200 case M88E1111_I_PHY_ID:
201 phy->type = e1000_phy_m88;
202 phy->ops.check_polarity = e1000_check_polarity_m88;
203 phy->ops.get_info = e1000_get_phy_info_m88;
189 phy->ops.get_cable_length = e1000_get_cable_length_m88;
204 if (phy->id == I347AT4_E_PHY_ID ||
205 phy->id == M88E1112_E_PHY_ID)
206 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
207 else
208 phy->ops.get_cable_length = e1000_get_cable_length_m88;
190 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
191 break;
192 case IGP03E1000_E_PHY_ID:
193 case IGP04E1000_E_PHY_ID:
194 phy->type = e1000_phy_igp_3;
195 phy->ops.check_polarity = e1000_check_polarity_igp;
196 phy->ops.get_info = e1000_get_phy_info_igp;
197 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
198 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
199 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
200 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
201 break;
202 case I82580_I_PHY_ID:
209 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
210 break;
211 case IGP03E1000_E_PHY_ID:
212 case IGP04E1000_E_PHY_ID:
213 phy->type = e1000_phy_igp_3;
214 phy->ops.check_polarity = e1000_check_polarity_igp;
215 phy->ops.get_info = e1000_get_phy_info_igp;
216 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
217 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
218 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
219 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
220 break;
221 case I82580_I_PHY_ID:
222 case I350_I_PHY_ID:
203 phy->type = e1000_phy_82580;
204 phy->ops.check_polarity = e1000_check_polarity_82577;
205 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577;
206 phy->ops.get_cable_length = e1000_get_cable_length_82577;
207 phy->ops.get_info = e1000_get_phy_info_82577;
223 phy->type = e1000_phy_82580;
224 phy->ops.check_polarity = e1000_check_polarity_82577;
225 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577;
226 phy->ops.get_cable_length = e1000_get_cable_length_82577;
227 phy->ops.get_info = e1000_get_phy_info_82577;
228 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
229 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
208 break;
209 default:
210 ret_val = -E1000_ERR_PHY;
211 goto out;
212 }
213
214out:
215 return ret_val;

--- 6 unchanged lines hidden (view full) ---

222static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
223{
224 struct e1000_nvm_info *nvm = &hw->nvm;
225 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
226 u16 size;
227
228 DEBUGFUNC("e1000_init_nvm_params_82575");
229
230 break;
231 default:
232 ret_val = -E1000_ERR_PHY;
233 goto out;
234 }
235
236out:
237 return ret_val;

--- 6 unchanged lines hidden (view full) ---

244static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
245{
246 struct e1000_nvm_info *nvm = &hw->nvm;
247 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
248 u16 size;
249
250 DEBUGFUNC("e1000_init_nvm_params_82575");
251
252 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
253 E1000_EECD_SIZE_EX_SHIFT);
254 /*
255 * Added to a constant, "size" becomes the left-shift value
256 * for setting word_size.
257 */
258 size += NVM_WORD_SIZE_BASE_SHIFT;
259
260 nvm->word_size = 1 << size;
261
230 nvm->opcode_bits = 8;
231 nvm->delay_usec = 1;
232 switch (nvm->override) {
233 case e1000_nvm_override_spi_large:
234 nvm->page_size = 32;
235 nvm->address_bits = 16;
236 break;
237 case e1000_nvm_override_spi_small:
238 nvm->page_size = 8;
239 nvm->address_bits = 8;
240 break;
241 default:
242 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
243 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
244 break;
245 }
246
262 nvm->opcode_bits = 8;
263 nvm->delay_usec = 1;
264 switch (nvm->override) {
265 case e1000_nvm_override_spi_large:
266 nvm->page_size = 32;
267 nvm->address_bits = 16;
268 break;
269 case e1000_nvm_override_spi_small:
270 nvm->page_size = 8;
271 nvm->address_bits = 8;
272 break;
273 default:
274 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
275 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
276 break;
277 }
278
247 nvm->type = e1000_nvm_eeprom_spi;
279 nvm->type = e1000_nvm_eeprom_spi;
248
280
249 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
250 E1000_EECD_SIZE_EX_SHIFT);
281 if (nvm->word_size == (1 << 15)) {
282 nvm->page_size = 128;
283 }
251
284
252 /*
253 * Added to a constant, "size" becomes the left-shift value
254 * for setting word_size.
255 */
256 size += NVM_WORD_SIZE_BASE_SHIFT;
257
285
258 /* EEPROM access above 16k is unsupported */
259 if (size > 14)
260 size = 14;
261 nvm->word_size = 1 << size;
262
263 /* Function Pointers */
286 /* Function Pointers */
264 nvm->ops.acquire = e1000_acquire_nvm_82575;
265 nvm->ops.read = e1000_read_nvm_eerd;
266 nvm->ops.release = e1000_release_nvm_82575;
267 nvm->ops.update = e1000_update_nvm_checksum_generic;
287 nvm->ops.acquire = e1000_acquire_nvm_82575;
288 if (nvm->word_size < (1 << 15)) {
289 nvm->ops.read = e1000_read_nvm_eerd;
290 } else {
291 nvm->ops.read = e1000_read_nvm_spi;
292 }
293 nvm->ops.release = e1000_release_nvm_82575;
268 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
294 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
269 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
270 nvm->ops.write = e1000_write_nvm_spi;
295 switch (hw->mac.type) {
296 case e1000_82580:
297 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
298 nvm->ops.update = e1000_update_nvm_checksum_82580;
299 break;
300 case e1000_i350:
301 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
302 nvm->ops.update = e1000_update_nvm_checksum_i350;
303 break;
304 default:
305 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
306 nvm->ops.update = e1000_update_nvm_checksum_generic;
307 }
308 nvm->ops.write = e1000_write_nvm_spi;
271
272 return E1000_SUCCESS;
273}
274
275/**
276 * e1000_init_mac_params_82575 - Init MAC func ptrs.
277 * @hw: pointer to the HW structure
278 **/

--- 34 unchanged lines hidden (view full) ---

313 /* Set uta register count */
314 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
315 /* Set rar entry count */
316 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
317 if (mac->type == e1000_82576)
318 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
319 if (mac->type == e1000_82580)
320 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
309
310 return E1000_SUCCESS;
311}
312
313/**
314 * e1000_init_mac_params_82575 - Init MAC func ptrs.
315 * @hw: pointer to the HW structure
316 **/

--- 34 unchanged lines hidden (view full) ---

351 /* Set uta register count */
352 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
353 /* Set rar entry count */
354 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
355 if (mac->type == e1000_82576)
356 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
357 if (mac->type == e1000_82580)
358 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
359 if (mac->type == e1000_i350) {
360 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
361 /* Enable EEE default settings for i350 */
362 dev_spec->eee_disable = FALSE;
363 }
364
321 /* Set if part includes ASF firmware */
322 mac->asf_firmware_present = TRUE;
323 /* FWSM register */
324 mac->has_fwsm = TRUE;
325 /* ARC supported; valid only if manageability features are enabled. */
326 mac->arc_subsystem_valid =
327 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
328 ? TRUE : FALSE;

--- 216 unchanged lines hidden (view full) ---

545 switch (hw->mac.type) {
546 case e1000_82575:
547 case e1000_82576:
548 mdic = E1000_READ_REG(hw, E1000_MDIC);
549 mdic &= E1000_MDIC_PHY_MASK;
550 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
551 break;
552 case e1000_82580:
365 /* Set if part includes ASF firmware */
366 mac->asf_firmware_present = TRUE;
367 /* FWSM register */
368 mac->has_fwsm = TRUE;
369 /* ARC supported; valid only if manageability features are enabled. */
370 mac->arc_subsystem_valid =
371 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
372 ? TRUE : FALSE;

--- 216 unchanged lines hidden (view full) ---

589 switch (hw->mac.type) {
590 case e1000_82575:
591 case e1000_82576:
592 mdic = E1000_READ_REG(hw, E1000_MDIC);
593 mdic &= E1000_MDIC_PHY_MASK;
594 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
595 break;
596 case e1000_82580:
597 case e1000_i350:
553 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
554 mdic &= E1000_MDICNFG_PHY_MASK;
555 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
556 break;
557 default:
558 ret_val = -E1000_ERR_PHY;
559 goto out;
560 break;

--- 164 unchanged lines hidden (view full) ---

725 }
726 }
727
728out:
729 return ret_val;
730}
731
732/**
598 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
599 mdic &= E1000_MDICNFG_PHY_MASK;
600 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
601 break;
602 default:
603 ret_val = -E1000_ERR_PHY;
604 goto out;
605 break;

--- 164 unchanged lines hidden (view full) ---

770 }
771 }
772
773out:
774 return ret_val;
775}
776
777/**
778 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
779 * @hw: pointer to the HW structure
780 * @active: TRUE to enable LPLU, FALSE to disable
781 *
782 * Sets the LPLU D0 state according to the active flag. When
783 * activating LPLU this function also disables smart speed
784 * and vice versa. LPLU will not be activated unless the
785 * device autonegotiation advertisement meets standards of
786 * either 10 or 10/100 or 10/100/1000 at all duplexes.
787 * This is a function pointer entry point only called by
788 * PHY setup routines.
789 **/
790static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
791{
792 struct e1000_phy_info *phy = &hw->phy;
793 s32 ret_val = E1000_SUCCESS;
794 u16 data;
795
796 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
797
798 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
799
800 if (active) {
801 data |= E1000_82580_PM_D0_LPLU;
802
803 /* When LPLU is enabled, we should disable SmartSpeed */
804 data &= ~E1000_82580_PM_SPD;
805 } else {
806 data &= ~E1000_82580_PM_D0_LPLU;
807
808 /*
809 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
810 * during Dx states where the power conservation is most
811 * important. During driver activity we should enable
812 * SmartSpeed, so performance is maintained.
813 */
814 if (phy->smart_speed == e1000_smart_speed_on) {
815 data |= E1000_82580_PM_SPD;
816 } else if (phy->smart_speed == e1000_smart_speed_off) {
817 data &= ~E1000_82580_PM_SPD;
818 }
819 }
820
821 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
822 return ret_val;
823}
824
825/**
826 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
827 * @hw: pointer to the HW structure
828 * @active: boolean used to enable/disable lplu
829 *
830 * Success returns 0, Failure returns 1
831 *
832 * The low power link up (lplu) state is set to the power management level D3
833 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
834 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
835 * is used during Dx states where the power conservation is most important.
836 * During driver activity, SmartSpeed should be enabled so performance is
837 * maintained.
838 **/
839s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
840{
841 struct e1000_phy_info *phy = &hw->phy;
842 s32 ret_val = E1000_SUCCESS;
843 u16 data;
844
845 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
846
847 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
848
849 if (!active) {
850 data &= ~E1000_82580_PM_D3_LPLU;
851 /*
852 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
853 * during Dx states where the power conservation is most
854 * important. During driver activity we should enable
855 * SmartSpeed, so performance is maintained.
856 */
857 if (phy->smart_speed == e1000_smart_speed_on) {
858 data |= E1000_82580_PM_SPD;
859 } else if (phy->smart_speed == e1000_smart_speed_off) {
860 data &= ~E1000_82580_PM_SPD;
861 }
862 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
863 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
864 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
865 data |= E1000_82580_PM_D3_LPLU;
866 /* When LPLU is enabled, we should disable SmartSpeed */
867 data &= ~E1000_82580_PM_SPD;
868 }
869
870 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
871 return ret_val;
872}
873
874/**
733 * e1000_acquire_nvm_82575 - Request for access to EEPROM
734 * @hw: pointer to the HW structure
735 *
736 * Acquire the necessary semaphores for exclusive access to the EEPROM.
737 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
738 * Return successful if access grant bit set, else clear the request for
739 * EEPROM access and return -E1000_ERR_NVM (-1).
740 **/

--- 330 unchanged lines hidden (view full) ---

1071/**
1072 * e1000_reset_hw_82575 - Reset hardware
1073 * @hw: pointer to the HW structure
1074 *
1075 * This resets the hardware into a known state.
1076 **/
1077static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1078{
875 * e1000_acquire_nvm_82575 - Request for access to EEPROM
876 * @hw: pointer to the HW structure
877 *
878 * Acquire the necessary semaphores for exclusive access to the EEPROM.
879 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
880 * Return successful if access grant bit set, else clear the request for
881 * EEPROM access and return -E1000_ERR_NVM (-1).
882 **/

--- 330 unchanged lines hidden (view full) ---

1213/**
1214 * e1000_reset_hw_82575 - Reset hardware
1215 * @hw: pointer to the HW structure
1216 *
1217 * This resets the hardware into a known state.
1218 **/
1219static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1220{
1079 u32 ctrl, icr;
1221 u32 ctrl;
1080 s32 ret_val;
1081
1082 DEBUGFUNC("e1000_reset_hw_82575");
1083
1084 /*
1085 * Prevent the PCI-E bus from sticking if there is no TLP connection
1086 * on the last TLP read/write transaction when MAC is reset.
1087 */

--- 33 unchanged lines hidden (view full) ---

1121 }
1122
1123 /* If EEPROM is not present, run manual init scripts */
1124 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1125 e1000_reset_init_script_82575(hw);
1126
1127 /* Clear any pending interrupt events. */
1128 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1222 s32 ret_val;
1223
1224 DEBUGFUNC("e1000_reset_hw_82575");
1225
1226 /*
1227 * Prevent the PCI-E bus from sticking if there is no TLP connection
1228 * on the last TLP read/write transaction when MAC is reset.
1229 */

--- 33 unchanged lines hidden (view full) ---

1263 }
1264
1265 /* If EEPROM is not present, run manual init scripts */
1266 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1267 e1000_reset_init_script_82575(hw);
1268
1269 /* Clear any pending interrupt events. */
1270 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1129 icr = E1000_READ_REG(hw, E1000_ICR);
1271 E1000_READ_REG(hw, E1000_ICR);
1130
1131 /* Install any alternate MAC address into RAR0 */
1132 ret_val = e1000_check_alt_mac_addr_generic(hw);
1133
1134 return ret_val;
1135}
1136
1137/**

--- 79 unchanged lines hidden (view full) ---

1217 ret_val = hw->phy.ops.reset(hw);
1218 if (ret_val) {
1219 DEBUGOUT("Error resetting the PHY.\n");
1220 goto out;
1221 }
1222 }
1223 switch (hw->phy.type) {
1224 case e1000_phy_m88:
1272
1273 /* Install any alternate MAC address into RAR0 */
1274 ret_val = e1000_check_alt_mac_addr_generic(hw);
1275
1276 return ret_val;
1277}
1278
1279/**

--- 79 unchanged lines hidden (view full) ---

1359 ret_val = hw->phy.ops.reset(hw);
1360 if (ret_val) {
1361 DEBUGOUT("Error resetting the PHY.\n");
1362 goto out;
1363 }
1364 }
1365 switch (hw->phy.type) {
1366 case e1000_phy_m88:
1225 ret_val = e1000_copper_link_setup_m88(hw);
1367 if (hw->phy.id == I347AT4_E_PHY_ID ||
1368 hw->phy.id == M88E1112_E_PHY_ID)
1369 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1370 else
1371 ret_val = e1000_copper_link_setup_m88(hw);
1226 break;
1227 case e1000_phy_igp_3:
1228 ret_val = e1000_copper_link_setup_igp(hw);
1229 break;
1230 case e1000_phy_82580:
1231 ret_val = e1000_copper_link_setup_82577(hw);
1232 break;
1233 default:

--- 331 unchanged lines hidden (view full) ---

1565
1566 /* This register should not be read in copper configurations */
1567 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1568 e1000_sgmii_active_82575(hw))
1569 E1000_READ_REG(hw, E1000_SCVPC);
1570}
1571
1572/**
1372 break;
1373 case e1000_phy_igp_3:
1374 ret_val = e1000_copper_link_setup_igp(hw);
1375 break;
1376 case e1000_phy_82580:
1377 ret_val = e1000_copper_link_setup_82577(hw);
1378 break;
1379 default:

--- 331 unchanged lines hidden (view full) ---

1711
1712 /* This register should not be read in copper configurations */
1713 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1714 e1000_sgmii_active_82575(hw))
1715 E1000_READ_REG(hw, E1000_SCVPC);
1716}
1717
1718/**
1573 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1719 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
1574 * @hw: pointer to the HW structure
1575 *
1576 * After rx enable if managability is enabled then there is likely some
1577 * bad data at the start of the fifo and possibly in the DMA fifo. This
1578 * function clears the fifos and flushes any packets that came in as rx was
1579 * being enabled.
1580 **/
1581void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
1582{
1583 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1584 int i, ms_wait;
1585
1586 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
1587 if (hw->mac.type != e1000_82575 ||
1588 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1589 return;
1590
1720 * @hw: pointer to the HW structure
1721 *
1722 * After rx enable if managability is enabled then there is likely some
1723 * bad data at the start of the fifo and possibly in the DMA fifo. This
1724 * function clears the fifos and flushes any packets that came in as rx was
1725 * being enabled.
1726 **/
1727void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
1728{
1729 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1730 int i, ms_wait;
1731
1732 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
1733 if (hw->mac.type != e1000_82575 ||
1734 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1735 return;
1736
1591 /* Disable all RX queues */
1737 /* Disable all Rx queues */
1592 for (i = 0; i < 4; i++) {
1593 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
1594 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
1595 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1596 }
1597 /* Poll all queues to verify they have shut down */
1598 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1599 msec_delay(1);

--- 21 unchanged lines hidden (view full) ---

1621 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1622 temp_rctl |= E1000_RCTL_LPE;
1623
1624 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
1625 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1626 E1000_WRITE_FLUSH(hw);
1627 msec_delay(2);
1628
1738 for (i = 0; i < 4; i++) {
1739 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
1740 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
1741 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1742 }
1743 /* Poll all queues to verify they have shut down */
1744 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1745 msec_delay(1);

--- 21 unchanged lines hidden (view full) ---

1767 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1768 temp_rctl |= E1000_RCTL_LPE;
1769
1770 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
1771 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1772 E1000_WRITE_FLUSH(hw);
1773 msec_delay(2);
1774
1629 /* Enable RX queues that were previously enabled and restore our
1775 /* Enable Rx queues that were previously enabled and restore our
1630 * previous state
1631 */
1632 for (i = 0; i < 4; i++)
1633 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
1634 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1635 E1000_WRITE_FLUSH(hw);
1636
1637 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);

--- 66 unchanged lines hidden (view full) ---

1704 * enables/disables L2 switch anti-spoofing functionality.
1705 **/
1706void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1707{
1708 u32 dtxswc;
1709
1710 switch (hw->mac.type) {
1711 case e1000_82576:
1776 * previous state
1777 */
1778 for (i = 0; i < 4; i++)
1779 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
1780 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1781 E1000_WRITE_FLUSH(hw);
1782
1783 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);

--- 66 unchanged lines hidden (view full) ---

1850 * enables/disables L2 switch anti-spoofing functionality.
1851 **/
1852void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1853{
1854 u32 dtxswc;
1855
1856 switch (hw->mac.type) {
1857 case e1000_82576:
1858 case e1000_i350:
1712 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
1713 if (enable) {
1714 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1715 E1000_DTXSWC_VLAN_SPOOF_MASK);
1716 /* The PF can spoof - it has to in order to
1717 * support emulation mode NICs */
1718 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1719 } else {

--- 22 unchanged lines hidden (view full) ---

1742 case e1000_82576:
1743 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
1744 if (enable)
1745 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1746 else
1747 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1748 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
1749 break;
1859 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
1860 if (enable) {
1861 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1862 E1000_DTXSWC_VLAN_SPOOF_MASK);
1863 /* The PF can spoof - it has to in order to
1864 * support emulation mode NICs */
1865 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1866 } else {

--- 22 unchanged lines hidden (view full) ---

1889 case e1000_82576:
1890 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
1891 if (enable)
1892 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1893 else
1894 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1895 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
1896 break;
1897 case e1000_i350:
1898 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
1899 if (enable)
1900 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1901 else
1902 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1903 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
1904 break;
1750 default:
1751 /* Currently no other hardware supports loopback */
1752 break;
1753 }
1754
1755
1756}
1757

--- 76 unchanged lines hidden (view full) ---

1834 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
1835 * the values found in the EEPROM. This addresses an issue in which these
1836 * bits are not restored from EEPROM after reset.
1837 **/
1838static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
1839{
1840 s32 ret_val = E1000_SUCCESS;
1841 u32 mdicnfg;
1905 default:
1906 /* Currently no other hardware supports loopback */
1907 break;
1908 }
1909
1910
1911}
1912

--- 76 unchanged lines hidden (view full) ---

1989 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
1990 * the values found in the EEPROM. This addresses an issue in which these
1991 * bits are not restored from EEPROM after reset.
1992 **/
1993static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
1994{
1995 s32 ret_val = E1000_SUCCESS;
1996 u32 mdicnfg;
1842 u16 nvm_data;
1997 u16 nvm_data = 0;
1843
1844 DEBUGFUNC("e1000_reset_mdicnfg_82580");
1845
1846 if (hw->mac.type != e1000_82580)
1847 goto out;
1848 if (!e1000_sgmii_active_82575(hw))
1849 goto out;
1850

--- 22 unchanged lines hidden (view full) ---

1873 * This resets function or entire device (all ports, etc.)
1874 * to a known state.
1875 **/
1876static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
1877{
1878 s32 ret_val = E1000_SUCCESS;
1879 /* BH SW mailbox bit in SW_FW_SYNC */
1880 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1998
1999 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2000
2001 if (hw->mac.type != e1000_82580)
2002 goto out;
2003 if (!e1000_sgmii_active_82575(hw))
2004 goto out;
2005

--- 22 unchanged lines hidden (view full) ---

2028 * This resets function or entire device (all ports, etc.)
2029 * to a known state.
2030 **/
2031static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2032{
2033 s32 ret_val = E1000_SUCCESS;
2034 /* BH SW mailbox bit in SW_FW_SYNC */
2035 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1881 u32 ctrl, icr;
2036 u32 ctrl;
1882 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1883
1884 DEBUGFUNC("e1000_reset_hw_82580");
1885
1886 hw->dev_spec._82575.global_device_reset = FALSE;
1887
1888 /* Get current control state. */
1889 ctrl = E1000_READ_REG(hw, E1000_CTRL);

--- 45 unchanged lines hidden (view full) ---

1935 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1936 e1000_reset_init_script_82575(hw);
1937
1938 /* clear global device reset status bit */
1939 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
1940
1941 /* Clear any pending interrupt events. */
1942 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2037 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2038
2039 DEBUGFUNC("e1000_reset_hw_82580");
2040
2041 hw->dev_spec._82575.global_device_reset = FALSE;
2042
2043 /* Get current control state. */
2044 ctrl = E1000_READ_REG(hw, E1000_CTRL);

--- 45 unchanged lines hidden (view full) ---

2090 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
2091 e1000_reset_init_script_82575(hw);
2092
2093 /* clear global device reset status bit */
2094 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2095
2096 /* Clear any pending interrupt events. */
2097 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1943 icr = E1000_READ_REG(hw, E1000_ICR);
2098 E1000_READ_REG(hw, E1000_ICR);
1944
1945 ret_val = e1000_reset_mdicnfg_82580(hw);
1946 if (ret_val)
1947 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
1948
1949 /* Install any alternate MAC address into RAR0 */
1950 ret_val = e1000_check_alt_mac_addr_generic(hw);
1951
1952 /* Release semaphore */
1953 if (global_device_reset)
1954 e1000_release_swfw_sync_82575(hw, swmbsw_mask);
1955
1956 return ret_val;
1957}
1958
1959/**
2099
2100 ret_val = e1000_reset_mdicnfg_82580(hw);
2101 if (ret_val)
2102 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2103
2104 /* Install any alternate MAC address into RAR0 */
2105 ret_val = e1000_check_alt_mac_addr_generic(hw);
2106
2107 /* Release semaphore */
2108 if (global_device_reset)
2109 e1000_release_swfw_sync_82575(hw, swmbsw_mask);
2110
2111 return ret_val;
2112}
2113
2114/**
1960 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2115 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
1961 * @data: data received by reading RXPBS register
1962 *
1963 * The 82580 uses a table based approach for packet buffer allocation sizes.
1964 * This function converts the retrieved value into the correct table value
1965 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1966 * 0x0 36 72 144 1 2 4 8 16
1967 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1968 */
1969u16 e1000_rxpbs_adjust_82580(u32 data)
1970{
1971 u16 ret_val = 0;
1972
1973 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1974 ret_val = e1000_82580_rxpbs_table[data];
1975
1976 return ret_val;
1977}
2116 * @data: data received by reading RXPBS register
2117 *
2118 * The 82580 uses a table based approach for packet buffer allocation sizes.
2119 * This function converts the retrieved value into the correct table value
2120 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2121 * 0x0 36 72 144 1 2 4 8 16
2122 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2123 */
2124u16 e1000_rxpbs_adjust_82580(u32 data)
2125{
2126 u16 ret_val = 0;
2127
2128 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2129 ret_val = e1000_82580_rxpbs_table[data];
2130
2131 return ret_val;
2132}
2133
2134/**
2135 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2136 * checksum
2137 * @hw: pointer to the HW structure
2138 * @offset: offset in words of the checksum protected region
2139 *
2140 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2141 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2142 **/
2143s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2144{
2145 s32 ret_val = E1000_SUCCESS;
2146 u16 checksum = 0;
2147 u16 i, nvm_data;
2148
2149 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2150
2151 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2152 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2153 if (ret_val) {
2154 DEBUGOUT("NVM Read Error\n");
2155 goto out;
2156 }
2157 checksum += nvm_data;
2158 }
2159
2160 if (checksum != (u16) NVM_SUM) {
2161 DEBUGOUT("NVM Checksum Invalid\n");
2162 ret_val = -E1000_ERR_NVM;
2163 goto out;
2164 }
2165
2166out:
2167 return ret_val;
2168}
2169
2170/**
2171 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2172 * checksum
2173 * @hw: pointer to the HW structure
2174 * @offset: offset in words of the checksum protected region
2175 *
2176 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2177 * up to the checksum. Then calculates the EEPROM checksum and writes the
2178 * value to the EEPROM.
2179 **/
2180s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2181{
2182 s32 ret_val;
2183 u16 checksum = 0;
2184 u16 i, nvm_data;
2185
2186 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2187
2188 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2189 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2190 if (ret_val) {
2191 DEBUGOUT("NVM Read Error while updating checksum.\n");
2192 goto out;
2193 }
2194 checksum += nvm_data;
2195 }
2196 checksum = (u16) NVM_SUM - checksum;
2197 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2198 &checksum);
2199 if (ret_val)
2200 DEBUGOUT("NVM Write Error while updating checksum.\n");
2201
2202out:
2203 return ret_val;
2204}
2205
2206/**
2207 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2208 * @hw: pointer to the HW structure
2209 *
2210 * Calculates the EEPROM section checksum by reading/adding each word of
2211 * the EEPROM and then verifies that the sum of the EEPROM is
2212 * equal to 0xBABA.
2213 **/
2214static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2215{
2216 s32 ret_val = E1000_SUCCESS;
2217 u16 eeprom_regions_count = 1;
2218 u16 j, nvm_data;
2219 u16 nvm_offset;
2220
2221 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2222
2223 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2224 if (ret_val) {
2225 DEBUGOUT("NVM Read Error\n");
2226 goto out;
2227 }
2228
2229 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2230 /* if chekcsums compatibility bit is set validate checksums
2231 * for all 4 ports. */
2232 eeprom_regions_count = 4;
2233 }
2234
2235 for (j = 0; j < eeprom_regions_count; j++) {
2236 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2237 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2238 nvm_offset);
2239 if (ret_val != E1000_SUCCESS)
2240 goto out;
2241 }
2242
2243out:
2244 return ret_val;
2245}
2246
2247/**
2248 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2249 * @hw: pointer to the HW structure
2250 *
2251 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2252 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2253 * checksum and writes the value to the EEPROM.
2254 **/
2255static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2256{
2257 s32 ret_val;
2258 u16 j, nvm_data;
2259 u16 nvm_offset;
2260
2261 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2262
2263 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2264 if (ret_val) {
2265 DEBUGOUT("NVM Read Error while updating checksum"
2266 " compatibility bit.\n");
2267 goto out;
2268 }
2269
2270 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2271 /* set compatibility bit to validate checksums appropriately */
2272 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2273 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2274 &nvm_data);
2275 if (ret_val) {
2276 DEBUGOUT("NVM Write Error while updating checksum"
2277 " compatibility bit.\n");
2278 goto out;
2279 }
2280 }
2281
2282 for (j = 0; j < 4; j++) {
2283 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2284 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2285 if (ret_val) {
2286 goto out;
2287 }
2288 }
2289
2290out:
2291 return ret_val;
2292}
2293
2294/**
2295 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2296 * @hw: pointer to the HW structure
2297 *
2298 * Calculates the EEPROM section checksum by reading/adding each word of
2299 * the EEPROM and then verifies that the sum of the EEPROM is
2300 * equal to 0xBABA.
2301 **/
2302static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2303{
2304 s32 ret_val = E1000_SUCCESS;
2305 u16 j;
2306 u16 nvm_offset;
2307
2308 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2309
2310 for (j = 0; j < 4; j++) {
2311 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2312 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2313 nvm_offset);
2314 if (ret_val != E1000_SUCCESS)
2315 goto out;
2316 }
2317
2318out:
2319 return ret_val;
2320}
2321
2322/**
2323 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2324 * @hw: pointer to the HW structure
2325 *
2326 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2327 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2328 * checksum and writes the value to the EEPROM.
2329 **/
2330static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2331{
2332 s32 ret_val = E1000_SUCCESS;
2333 u16 j;
2334 u16 nvm_offset;
2335
2336 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2337
2338 for (j = 0; j < 4; j++) {
2339 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2340 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2341 if (ret_val != E1000_SUCCESS)
2342 goto out;
2343 }
2344
2345out:
2346 return ret_val;
2347}
2348
2349/**
2350 * e1000_set_eee_i350 - Enable/disable EEE support
2351 * @hw: pointer to the HW structure
2352 *
2353 * Enable/disable EEE based on setting in dev_spec structure.
2354 *
2355 **/
2356s32 e1000_set_eee_i350(struct e1000_hw *hw)
2357{
2358 s32 ret_val = E1000_SUCCESS;
2359 u32 ipcnfg, eeer, ctrl_ext;
2360
2361 DEBUGFUNC("e1000_set_eee_i350");
2362
2363 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2364 if ((hw->mac.type != e1000_i350) ||
2365 (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK))
2366 goto out;
2367 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2368 eeer = E1000_READ_REG(hw, E1000_EEER);
2369
2370 /* enable or disable per user setting */
2371 if (!(hw->dev_spec._82575.eee_disable)) {
2372 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN |
2373 E1000_IPCNFG_EEE_100M_AN);
2374 eeer |= (E1000_EEER_TX_LPI_EN |
2375 E1000_EEER_RX_LPI_EN |
2376 E1000_EEER_LPI_FC);
2377
2378 } else {
2379 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2380 E1000_IPCNFG_EEE_100M_AN);
2381 eeer &= ~(E1000_EEER_TX_LPI_EN |
2382 E1000_EEER_RX_LPI_EN |
2383 E1000_EEER_LPI_FC);
2384 }
2385 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2386 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2387 E1000_READ_REG(hw, E1000_IPCNFG);
2388 E1000_READ_REG(hw, E1000_EEER);
2389out:
2390
2391 return ret_val;
2392}