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e1000_82575.c (178523) e1000_82575.c (181027)
1/******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/igb/e1000_82575.c 178523 2008-04-25 21:19:41Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 181027 2008-07-30 21:56:53Z jfv $*/
34
35/* e1000_82575
36 * e1000_82576
37 */
38
39#include "e1000_api.h"
40
41static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);

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53static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
54static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
55 u16 *data);
56static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
57static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
58 bool active);
59static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
60static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw);
34
35/* e1000_82575
36 * e1000_82576
37 */
38
39#include "e1000_api.h"
40
41static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);

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53static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
54static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
55 u16 *data);
56static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
57static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
58 bool active);
59static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
60static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw);
61static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
61static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
62 u32 offset, u16 data);
63static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
64static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
65static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw);
66static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
67 u16 *speed, u16 *duplex);
68static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
69static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
70static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
71static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
72static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
73static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
74
62static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
63 u32 offset, u16 data);
64static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
65static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
66static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw);
67static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
68 u16 *speed, u16 *duplex);
69static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
70static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
71static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
72static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
73static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
74static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
75
76static void e1000_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count);
77static void e1000_update_mc_addr_list_82575(struct e1000_hw *hw,
78 u8 *mc_addr_list, u32 mc_addr_count,
79 u32 rar_used_count, u32 rar_count);
80void e1000_remove_device_82575(struct e1000_hw *hw);
81void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw);
75
76struct e1000_dev_spec_82575 {
77 bool sgmii_active;
78};
79
80/**
81 * e1000_init_phy_params_82575 - Init PHY func ptrs.
82 * @hw: pointer to the HW structure

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125 case M88E1111_I_PHY_ID:
126 phy->type = e1000_phy_m88;
127 phy->ops.check_polarity = e1000_check_polarity_m88;
128 phy->ops.get_info = e1000_get_phy_info_m88;
129 phy->ops.get_cable_length = e1000_get_cable_length_m88;
130 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
131 break;
132 case IGP03E1000_E_PHY_ID:
82
83struct e1000_dev_spec_82575 {
84 bool sgmii_active;
85};
86
87/**
88 * e1000_init_phy_params_82575 - Init PHY func ptrs.
89 * @hw: pointer to the HW structure

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132 case M88E1111_I_PHY_ID:
133 phy->type = e1000_phy_m88;
134 phy->ops.check_polarity = e1000_check_polarity_m88;
135 phy->ops.get_info = e1000_get_phy_info_m88;
136 phy->ops.get_cable_length = e1000_get_cable_length_m88;
137 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
138 break;
139 case IGP03E1000_E_PHY_ID:
140 case IGP04E1000_E_PHY_ID:
133 phy->type = e1000_phy_igp_3;
134 phy->ops.check_polarity = e1000_check_polarity_igp;
135 phy->ops.get_info = e1000_get_phy_info_igp;
136 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
137 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
138 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
139 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
140 break;

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194 size = 14;
195 nvm->word_size = 1 << size;
196
197 /* Function Pointers */
198 nvm->ops.acquire = e1000_acquire_nvm_82575;
199 nvm->ops.read = e1000_read_nvm_eerd;
200 nvm->ops.release = e1000_release_nvm_82575;
201 nvm->ops.update = e1000_update_nvm_checksum_generic;
141 phy->type = e1000_phy_igp_3;
142 phy->ops.check_polarity = e1000_check_polarity_igp;
143 phy->ops.get_info = e1000_get_phy_info_igp;
144 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
145 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
146 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
147 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
148 break;

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202 size = 14;
203 nvm->word_size = 1 << size;
204
205 /* Function Pointers */
206 nvm->ops.acquire = e1000_acquire_nvm_82575;
207 nvm->ops.read = e1000_read_nvm_eerd;
208 nvm->ops.release = e1000_release_nvm_82575;
209 nvm->ops.update = e1000_update_nvm_checksum_generic;
202 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
210 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
203 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
204 nvm->ops.write = e1000_write_nvm_spi;
205
206 return E1000_SUCCESS;
207}
208
209/**
210 * e1000_init_mac_params_82575 - Init MAC func ptrs.

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253 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
254 }
255 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
256
257 /* Set mta register count */
258 mac->mta_reg_count = 128;
259 /* Set rar entry count */
260 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
211 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
212 nvm->ops.write = e1000_write_nvm_spi;
213
214 return E1000_SUCCESS;
215}
216
217/**
218 * e1000_init_mac_params_82575 - Init MAC func ptrs.

--- 42 unchanged lines hidden (view full) ---

261 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
262 }
263 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
264
265 /* Set mta register count */
266 mac->mta_reg_count = 128;
267 /* Set rar entry count */
268 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
269 if (mac->type == e1000_82576)
270 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
261 /* Set if part includes ASF firmware */
262 mac->asf_firmware_present = TRUE;
263 /* Set if manageability features are enabled. */
264 mac->arc_subsystem_valid =
265 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
266 ? TRUE : FALSE;
267
268 /* Function pointers */

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275 mac->ops.init_hw = e1000_init_hw_82575;
276 /* link setup */
277 mac->ops.setup_link = e1000_setup_link_generic;
278 /* physical interface link setup */
279 mac->ops.setup_physical_interface =
280 (hw->phy.media_type == e1000_media_type_copper)
281 ? e1000_setup_copper_link_82575
282 : e1000_setup_fiber_serdes_link_82575;
271 /* Set if part includes ASF firmware */
272 mac->asf_firmware_present = TRUE;
273 /* Set if manageability features are enabled. */
274 mac->arc_subsystem_valid =
275 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
276 ? TRUE : FALSE;
277
278 /* Function pointers */

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285 mac->ops.init_hw = e1000_init_hw_82575;
286 /* link setup */
287 mac->ops.setup_link = e1000_setup_link_generic;
288 /* physical interface link setup */
289 mac->ops.setup_physical_interface =
290 (hw->phy.media_type == e1000_media_type_copper)
291 ? e1000_setup_copper_link_82575
292 : e1000_setup_fiber_serdes_link_82575;
293 /* physical interface shutdown */
294 mac->ops.shutdown_serdes = e1000_shutdown_fiber_serdes_link_82575;
283 /* check for link */
284 mac->ops.check_for_link = e1000_check_for_link_82575;
285 /* receive address register setting */
286 mac->ops.rar_set = e1000_rar_set_generic;
287 /* read mac address */
288 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
289 /* multicast address update */
295 /* check for link */
296 mac->ops.check_for_link = e1000_check_for_link_82575;
297 /* receive address register setting */
298 mac->ops.rar_set = e1000_rar_set_generic;
299 /* read mac address */
300 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
301 /* multicast address update */
290 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
302 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_82575;
291 /* writing VFTA */
292 mac->ops.write_vfta = e1000_write_vfta_generic;
293 /* clearing VFTA */
294 mac->ops.clear_vfta = e1000_clear_vfta_generic;
295 /* setting MTA */
296 mac->ops.mta_set = e1000_mta_set_generic;
297 /* blink LED */
298 mac->ops.blink_led = e1000_blink_led_generic;
299 /* setup LED */
300 mac->ops.setup_led = e1000_setup_led_generic;
301 /* cleanup LED */
302 mac->ops.cleanup_led = e1000_cleanup_led_generic;
303 /* turn on/off LED */
304 mac->ops.led_on = e1000_led_on_generic;
305 mac->ops.led_off = e1000_led_off_generic;
306 /* remove device */
303 /* writing VFTA */
304 mac->ops.write_vfta = e1000_write_vfta_generic;
305 /* clearing VFTA */
306 mac->ops.clear_vfta = e1000_clear_vfta_generic;
307 /* setting MTA */
308 mac->ops.mta_set = e1000_mta_set_generic;
309 /* blink LED */
310 mac->ops.blink_led = e1000_blink_led_generic;
311 /* setup LED */
312 mac->ops.setup_led = e1000_setup_led_generic;
313 /* cleanup LED */
314 mac->ops.cleanup_led = e1000_cleanup_led_generic;
315 /* turn on/off LED */
316 mac->ops.led_on = e1000_led_on_generic;
317 mac->ops.led_off = e1000_led_off_generic;
318 /* remove device */
307 mac->ops.remove_device = e1000_remove_device_generic;
319 mac->ops.remove_device = e1000_remove_device_82575;
308 /* clear hardware counters */
309 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
310 /* link info */
311 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
312
313out:
314 return ret_val;
315}

--- 612 unchanged lines hidden (view full) ---

928 *duplex = HALF_DUPLEX;
929 }
930 }
931
932 return E1000_SUCCESS;
933}
934
935/**
320 /* clear hardware counters */
321 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
322 /* link info */
323 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
324
325out:
326 return ret_val;
327}

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940 *duplex = HALF_DUPLEX;
941 }
942 }
943
944 return E1000_SUCCESS;
945}
946
947/**
948 * e1000_init_rx_addrs_82575 - Initialize receive address's
949 * @hw: pointer to the HW structure
950 * @rar_count: receive address registers
951 *
952 * Setups the receive address registers by setting the base receive address
953 * register to the devices MAC address and clearing all the other receive
954 * address registers to 0.
955 **/
956static void e1000_init_rx_addrs_82575(struct e1000_hw *hw, u16 rar_count)
957{
958 u32 i;
959 u8 addr[6] = {0,0,0,0,0,0};
960 /*
961 * This function is essentially the same as that of
962 * e1000_init_rx_addrs_generic. However it also takes care
963 * of the special case where the register offset of the
964 * second set of RARs begins elsewhere. This is implicitly taken care by
965 * function e1000_rar_set_generic.
966 */
967
968 DEBUGFUNC("e1000_init_rx_addrs_82575");
969
970 /* Setup the receive address */
971 DEBUGOUT("Programming MAC Address into RAR[0]\n");
972 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
973
974 /* Zero out the other (rar_entry_count - 1) receive addresses */
975 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
976 for (i = 1; i < rar_count; i++) {
977 hw->mac.ops.rar_set(hw, addr, i);
978 }
979}
980
981/**
982 * e1000_update_mc_addr_list_82575 - Update Multicast addresses
983 * @hw: pointer to the HW structure
984 * @mc_addr_list: array of multicast addresses to program
985 * @mc_addr_count: number of multicast addresses to program
986 * @rar_used_count: the first RAR register free to program
987 * @rar_count: total number of supported Receive Address Registers
988 *
989 * Updates the Receive Address Registers and Multicast Table Array.
990 * The caller must have a packed mc_addr_list of multicast addresses.
991 * The parameter rar_count will usually be hw->mac.rar_entry_count
992 * unless there are workarounds that change this.
993 **/
994static void e1000_update_mc_addr_list_82575(struct e1000_hw *hw,
995 u8 *mc_addr_list, u32 mc_addr_count,
996 u32 rar_used_count, u32 rar_count)
997{
998 u32 hash_value;
999 u32 i;
1000 u8 addr[6] = {0,0,0,0,0,0};
1001 /*
1002 * This function is essentially the same as that of
1003 * e1000_update_mc_addr_list_generic. However it also takes care
1004 * of the special case where the register offset of the
1005 * second set of RARs begins elsewhere. This is implicitly taken care by
1006 * function e1000_rar_set_generic.
1007 */
1008
1009 DEBUGFUNC("e1000_update_mc_addr_list_82575");
1010
1011 /*
1012 * Load the first set of multicast addresses into the exact
1013 * filters (RAR). If there are not enough to fill the RAR
1014 * array, clear the filters.
1015 */
1016 for (i = rar_used_count; i < rar_count; i++) {
1017 if (mc_addr_count) {
1018 e1000_rar_set_generic(hw, mc_addr_list, i);
1019 mc_addr_count--;
1020 mc_addr_list += ETH_ADDR_LEN;
1021 } else {
1022 e1000_rar_set_generic(hw, addr, i);
1023 }
1024 }
1025
1026 /* Clear the old settings from the MTA */
1027 DEBUGOUT("Clearing MTA\n");
1028 for (i = 0; i < hw->mac.mta_reg_count; i++) {
1029 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1030 E1000_WRITE_FLUSH(hw);
1031 }
1032
1033 /* Load any remaining multicast addresses into the hash table. */
1034 for (; mc_addr_count > 0; mc_addr_count--) {
1035 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
1036 DEBUGOUT1("Hash value = 0x%03X\n", hash_value);
1037 hw->mac.ops.mta_set(hw, hash_value);
1038 mc_addr_list += ETH_ADDR_LEN;
1039 }
1040}
1041
1042/**
1043 * e1000_shutdown_fiber_serdes_link_82575 - Remove link during power down
1044 * @hw: pointer to the HW structure
1045 *
1046 * In the case of fiber serdes shut down optics and PCS on driver unload
1047 * when management pass thru is not enabled.
1048 **/
1049void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw)
1050{
1051 u32 reg;
1052
1053 if (hw->mac.type != e1000_82576 ||
1054 (hw->phy.media_type != e1000_media_type_fiber &&
1055 hw->phy.media_type != e1000_media_type_internal_serdes))
1056 return;
1057
1058 /* if the management interface is not enabled, then power down */
1059 if (!e1000_enable_mng_pass_thru(hw)) {
1060 /* Disable PCS to turn off link */
1061 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1062 reg &= ~E1000_PCS_CFG_PCS_EN;
1063 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1064
1065 /* shutdown the laser */
1066 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1067 reg |= E1000_CTRL_EXT_SDP7_DATA;
1068 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1069
1070 /* flush the write to verfiy completion */
1071 E1000_WRITE_FLUSH(hw);
1072 msec_delay(1);
1073 }
1074
1075 return;
1076}
1077
1078/**
936 * e1000_reset_hw_82575 - Reset hardware
937 * @hw: pointer to the HW structure
938 *
939 * This resets the hardware into a known state. This is a
940 * function pointer entry point called by the api module.
941 **/
942static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
943{

--- 69 unchanged lines hidden (view full) ---

1013 /* This is not fatal and we should not stop init due to this */
1014 }
1015
1016 /* Disabling VLAN filtering */
1017 DEBUGOUT("Initializing the IEEE VLAN\n");
1018 mac->ops.clear_vfta(hw);
1019
1020 /* Setup the receive address */
1079 * e1000_reset_hw_82575 - Reset hardware
1080 * @hw: pointer to the HW structure
1081 *
1082 * This resets the hardware into a known state. This is a
1083 * function pointer entry point called by the api module.
1084 **/
1085static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1086{

--- 69 unchanged lines hidden (view full) ---

1156 /* This is not fatal and we should not stop init due to this */
1157 }
1158
1159 /* Disabling VLAN filtering */
1160 DEBUGOUT("Initializing the IEEE VLAN\n");
1161 mac->ops.clear_vfta(hw);
1162
1163 /* Setup the receive address */
1021 e1000_init_rx_addrs_generic(hw, rar_count);
1164 e1000_init_rx_addrs_82575(hw, rar_count);
1022 /* Zero out the Multicast HASH table */
1023 DEBUGOUT("Zeroing the MTA\n");
1024 for (i = 0; i < mac->mta_reg_count; i++)
1025 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1026
1027 /* Setup link and flow control */
1028 ret_val = mac->ops.setup_link(hw);
1029

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1152 reg = E1000_READ_REG(hw, E1000_CTRL);
1153 reg |= E1000_CTRL_SLU |
1154 E1000_CTRL_SPD_1000 |
1155 E1000_CTRL_FRCSPD |
1156 E1000_CTRL_SWDPIN0 |
1157 E1000_CTRL_SWDPIN1;
1158 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1159
1165 /* Zero out the Multicast HASH table */
1166 DEBUGOUT("Zeroing the MTA\n");
1167 for (i = 0; i < mac->mta_reg_count; i++)
1168 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1169
1170 /* Setup link and flow control */
1171 ret_val = mac->ops.setup_link(hw);
1172

--- 122 unchanged lines hidden (view full) ---

1295 reg = E1000_READ_REG(hw, E1000_CTRL);
1296 reg |= E1000_CTRL_SLU |
1297 E1000_CTRL_SPD_1000 |
1298 E1000_CTRL_FRCSPD |
1299 E1000_CTRL_SWDPIN0 |
1300 E1000_CTRL_SWDPIN1;
1301 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1302
1303 /* Power on phy for 82576 fiber adapters */
1304 if (hw->mac.type == e1000_82576) {
1305 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1306 reg &= ~E1000_CTRL_EXT_SDP7_DATA;
1307 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1308 }
1309
1160 /* Set switch control to serdes energy detect */
1161 reg = E1000_READ_REG(hw, E1000_CONNSW);
1162 reg |= E1000_CONNSW_ENRGSRC;
1163 E1000_WRITE_REG(hw, E1000_CONNSW, reg);
1164
1165 /*
1166 * New SerDes mode allows for forcing speed or autonegotiating speed
1167 * at 1gb. Autoneg should be default set by most drivers. This is the

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1184 /* Set PCS register for forced speed */
1185 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1186 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1187 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1188 E1000_PCS_LCTL_FSD | /* Force Speed */
1189 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1190 DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1191 }
1310 /* Set switch control to serdes energy detect */
1311 reg = E1000_READ_REG(hw, E1000_CONNSW);
1312 reg |= E1000_CONNSW_ENRGSRC;
1313 E1000_WRITE_REG(hw, E1000_CONNSW, reg);
1314
1315 /*
1316 * New SerDes mode allows for forcing speed or autonegotiating speed
1317 * at 1gb. Autoneg should be default set by most drivers. This is the

--- 16 unchanged lines hidden (view full) ---

1334 /* Set PCS register for forced speed */
1335 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1336 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1337 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1338 E1000_PCS_LCTL_FSD | /* Force Speed */
1339 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1340 DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1341 }
1342
1343 if (hw->mac.type == e1000_82576) {
1344 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1345 e1000_force_mac_fc_generic(hw);
1346 }
1347
1192 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1193
1194 return E1000_SUCCESS;
1195}
1196
1197/**
1348 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1349
1350 return E1000_SUCCESS;
1351}
1352
1353/**
1354 * e1000_valid_led_default_82575 - Verify a valid default LED config
1355 * @hw: pointer to the HW structure
1356 * @data: pointer to the NVM (EEPROM)
1357 *
1358 * Read the EEPROM for the current default LED configuration. If the
1359 * LED configuration is not valid, set to a valid LED configuration.
1360 **/
1361static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1362{
1363 s32 ret_val;
1364
1365 DEBUGFUNC("e1000_valid_led_default_82575");
1366
1367 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1368 if (ret_val) {
1369 DEBUGOUT("NVM Read Error\n");
1370 goto out;
1371 }
1372
1373 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1374 switch(hw->phy.media_type) {
1375 case e1000_media_type_fiber:
1376 case e1000_media_type_internal_serdes:
1377 *data = ID_LED_DEFAULT_82575_SERDES;
1378 break;
1379 case e1000_media_type_copper:
1380 default:
1381 *data = ID_LED_DEFAULT;
1382 break;
1383 }
1384 }
1385out:
1386 return ret_val;
1387}
1388
1389/**
1198 * e1000_configure_pcs_link_82575 - Configure PCS link
1199 * @hw: pointer to the HW structure
1200 *
1201 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1202 * only used on copper connections where the serialized gigabit media
1203 * independent interface (sgmii) is being used. Configures the link
1204 * for auto-negotiation or forces speed/duplex.
1205 **/

--- 64 unchanged lines hidden (view full) ---

1270 **/
1271static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1272{
1273 struct e1000_dev_spec_82575 *dev_spec;
1274 bool ret_val;
1275
1276 DEBUGFUNC("e1000_sgmii_active_82575");
1277
1390 * e1000_configure_pcs_link_82575 - Configure PCS link
1391 * @hw: pointer to the HW structure
1392 *
1393 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1394 * only used on copper connections where the serialized gigabit media
1395 * independent interface (sgmii) is being used. Configures the link
1396 * for auto-negotiation or forces speed/duplex.
1397 **/

--- 64 unchanged lines hidden (view full) ---

1462 **/
1463static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1464{
1465 struct e1000_dev_spec_82575 *dev_spec;
1466 bool ret_val;
1467
1468 DEBUGFUNC("e1000_sgmii_active_82575");
1469
1278 if (hw->mac.type != e1000_82575) {
1470 if (hw->mac.type != e1000_82575 && hw->mac.type != e1000_82576) {
1279 ret_val = FALSE;
1280 goto out;
1281 }
1282
1283 dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
1284
1285 ret_val = dev_spec->sgmii_active;
1286
1287out:
1288 return ret_val;
1289}
1290
1291/**
1471 ret_val = FALSE;
1472 goto out;
1473 }
1474
1475 dev_spec = (struct e1000_dev_spec_82575 *)hw->dev_spec;
1476
1477 ret_val = dev_spec->sgmii_active;
1478
1479out:
1480 return ret_val;
1481}
1482
1483/**
1484 * e1000_translate_register_82576 - Translate the proper register offset
1485 * @reg: e1000 register to be read
1486 *
1487 * Registers in 82576 are located in different offsets than other adapters
1488 * even though they function in the same manner. This function takes in
1489 * the name of the register to read and returns the correct offset for
1490 * 82576 silicon.
1491 **/
1492u32 e1000_translate_register_82576(u32 reg)
1493{
1494 /*
1495 * Some of the 82576 registers are located at different
1496 * offsets than they are in older adapters.
1497 * Despite the difference in location, the registers
1498 * function in the same manner.
1499 */
1500 switch (reg) {
1501 case E1000_TDBAL(0):
1502 reg = 0x0E000;
1503 break;
1504 case E1000_TDBAH(0):
1505 reg = 0x0E004;
1506 break;
1507 case E1000_TDLEN(0):
1508 reg = 0x0E008;
1509 break;
1510 case E1000_TDH(0):
1511 reg = 0x0E010;
1512 break;
1513 case E1000_TDT(0):
1514 reg = 0x0E018;
1515 break;
1516 case E1000_TXDCTL(0):
1517 reg = 0x0E028;
1518 break;
1519 case E1000_RDBAL(0):
1520 reg = 0x0C000;
1521 break;
1522 case E1000_RDBAH(0):
1523 reg = 0x0C004;
1524 break;
1525 case E1000_RDLEN(0):
1526 reg = 0x0C008;
1527 break;
1528 case E1000_RDH(0):
1529 reg = 0x0C010;
1530 break;
1531 case E1000_RDT(0):
1532 reg = 0x0C018;
1533 break;
1534 case E1000_RXDCTL(0):
1535 reg = 0x0C028;
1536 break;
1537 case E1000_SRRCTL(0):
1538 reg = 0x0C00C;
1539 break;
1540 default:
1541 break;
1542 }
1543
1544 return reg;
1545}
1546
1547/**
1292 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1293 * @hw: pointer to the HW structure
1294 *
1295 * Inits recommended HW defaults after a reset when there is no EEPROM
1296 * detected. This is only for the 82575.
1297 **/
1298static s32 e1000_reset_init_script_82575(struct e1000_hw* hw)
1299{

--- 59 unchanged lines hidden (view full) ---

1359 /* If the management interface is not enabled, then power down */
1360 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1361 e1000_power_down_phy_copper(hw);
1362
1363 return;
1364}
1365
1366/**
1548 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1549 * @hw: pointer to the HW structure
1550 *
1551 * Inits recommended HW defaults after a reset when there is no EEPROM
1552 * detected. This is only for the 82575.
1553 **/
1554static s32 e1000_reset_init_script_82575(struct e1000_hw* hw)
1555{

--- 59 unchanged lines hidden (view full) ---

1615 /* If the management interface is not enabled, then power down */
1616 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1617 e1000_power_down_phy_copper(hw);
1618
1619 return;
1620}
1621
1622/**
1623 * e1000_remove_device_82575 - Free device specific structure
1624 * @hw: pointer to the HW structure
1625 *
1626 * If a device specific structure was allocated, this function will
1627 * free it after shutting down the serdes interface if available.
1628 **/
1629void e1000_remove_device_82575(struct e1000_hw *hw)
1630{
1631 u16 eeprom_data = 0;
1632
1633 /*
1634 * If APM is enabled in the EEPROM then leave the port on for fiber
1635 * serdes adapters.
1636 */
1637 if (hw->bus.func == 0)
1638 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1639
1640 if (!(eeprom_data & E1000_NVM_APME_82575))
1641 e1000_shutdown_fiber_serdes_link_82575(hw);
1642
1643 e1000_remove_device_generic(hw);
1644}
1645
1646/**
1367 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1368 * @hw: pointer to the HW structure
1369 *
1370 * Clears the hardware counters by reading the counter registers.
1371 **/
1372static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1373{
1374 volatile u32 temp;

--- 48 unchanged lines hidden (view full) ---

1423 temp = E1000_READ_REG(hw, E1000_HGOTCL);
1424 temp = E1000_READ_REG(hw, E1000_HGOTCH);
1425 temp = E1000_READ_REG(hw, E1000_LENERRS);
1426
1427 /* This register should not be read in copper configurations */
1428 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1429 temp = E1000_READ_REG(hw, E1000_SCVPC);
1430}
1647 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1648 * @hw: pointer to the HW structure
1649 *
1650 * Clears the hardware counters by reading the counter registers.
1651 **/
1652static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1653{
1654 volatile u32 temp;

--- 48 unchanged lines hidden (view full) ---

1703 temp = E1000_READ_REG(hw, E1000_HGOTCL);
1704 temp = E1000_READ_REG(hw, E1000_HGOTCH);
1705 temp = E1000_READ_REG(hw, E1000_LENERRS);
1706
1707 /* This register should not be read in copper configurations */
1708 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1709 temp = E1000_READ_REG(hw, E1000_SCVPC);
1710}
1711/**
1712 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1713 * @hw: pointer to the HW structure
1714 *
1715 * After rx enable if managability is enabled then there is likely some
1716 * bad data at the start of the fifo and possibly in the DMA fifo. This
1717 * function clears the fifos and flushes any packets that came in as rx was
1718 * being enabled.
1719 **/
1720void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
1721{
1722 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1723 int i, ms_wait;
1724
1725 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
1726 if (hw->mac.type != e1000_82575 ||
1727 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1728 return;
1729
1730 /* Disable all RX queues */
1731 for (i = 0; i < 4; i++) {
1732 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
1733 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
1734 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1735 }
1736 /* Poll all queues to verify they have shut down */
1737 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1738 msec_delay(1);
1739 rx_enabled = 0;
1740 for (i = 0; i < 4; i++)
1741 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
1742 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1743 break;
1744 }
1745
1746 if (ms_wait == 10)
1747 DEBUGOUT("Queue disable timed out after 10ms\n");
1748
1749 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1750 * incoming packets are rejected. Set enable and wait 2ms so that
1751 * any packet that was coming in as RCTL.EN was set is flushed
1752 */
1753 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
1754 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1755
1756 rlpml = E1000_READ_REG(hw, E1000_RLPML);
1757 E1000_WRITE_REG(hw, E1000_RLPML, 0);
1758
1759 rctl = E1000_READ_REG(hw, E1000_RCTL);
1760 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1761 temp_rctl |= E1000_RCTL_LPE;
1762
1763 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
1764 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1765 E1000_WRITE_FLUSH(hw);
1766 msec_delay(2);
1767
1768 /* Enable RX queues that were previously enabled and restore our
1769 * previous state
1770 */
1771 for (i = 0; i < 4; i++)
1772 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
1773 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1774 E1000_WRITE_FLUSH(hw);
1775
1776 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
1777 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
1778
1779 /* Flush receive errors generated by workaround */
1780 E1000_READ_REG(hw, E1000_ROC);
1781 E1000_READ_REG(hw, E1000_RNBC);
1782 E1000_READ_REG(hw, E1000_MPC);
1783}