Deleted Added
sdiff udiff text old ( 139749 ) new ( 145132 )
full compact
mga_drm.h (139749) mga_drm.h (145132)
1/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
2 * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com */
3/*-
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a

--- 17 unchanged lines hidden (view full) ---

26 *
27 * Authors:
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 *
31 * Rewritten by:
32 * Gareth Hughes <gareth@valinux.com>
33 *
1/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
2 * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com */
3/*-
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a

--- 17 unchanged lines hidden (view full) ---

26 *
27 * Authors:
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 *
31 * Rewritten by:
32 * Gareth Hughes <gareth@valinux.com>
33 *
34 * $FreeBSD: head/sys/dev/drm/mga_drm.h 139749 2005-01-06 01:43:34Z imp $
34 * $FreeBSD: head/sys/dev/drm/mga_drm.h 145132 2005-04-16 03:44:47Z anholt $
35 */
36
37#ifndef __MGA_DRM_H__
38#define __MGA_DRM_H__
39
40/* WARNING: If you change any of these defines, make sure to change the
41 * defines in the Xserver file (mga_sarea.h)
42 */
43
44#ifndef __MGA_SAREA_DEFINES__
45#define __MGA_SAREA_DEFINES__
46
47/* WARP pipe flags
48 */
35 */
36
37#ifndef __MGA_DRM_H__
38#define __MGA_DRM_H__
39
40/* WARNING: If you change any of these defines, make sure to change the
41 * defines in the Xserver file (mga_sarea.h)
42 */
43
44#ifndef __MGA_SAREA_DEFINES__
45#define __MGA_SAREA_DEFINES__
46
47/* WARP pipe flags
48 */
49#define MGA_F 0x1 /* fog */
50#define MGA_A 0x2 /* alpha */
51#define MGA_S 0x4 /* specular */
52#define MGA_T2 0x8 /* multitexture */
49#define MGA_F 0x1 /* fog */
50#define MGA_A 0x2 /* alpha */
51#define MGA_S 0x4 /* specular */
52#define MGA_T2 0x8 /* multitexture */
53
54#define MGA_WARP_TGZ 0
55#define MGA_WARP_TGZF (MGA_F)
56#define MGA_WARP_TGZA (MGA_A)
57#define MGA_WARP_TGZAF (MGA_F|MGA_A)
58#define MGA_WARP_TGZS (MGA_S)
59#define MGA_WARP_TGZSF (MGA_S|MGA_F)
60#define MGA_WARP_TGZSA (MGA_S|MGA_A)
61#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A)
62#define MGA_WARP_T2GZ (MGA_T2)
63#define MGA_WARP_T2GZF (MGA_T2|MGA_F)
64#define MGA_WARP_T2GZA (MGA_T2|MGA_A)
65#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F)
66#define MGA_WARP_T2GZS (MGA_T2|MGA_S)
67#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F)
68#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A)
69#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A)
70
53
54#define MGA_WARP_TGZ 0
55#define MGA_WARP_TGZF (MGA_F)
56#define MGA_WARP_TGZA (MGA_A)
57#define MGA_WARP_TGZAF (MGA_F|MGA_A)
58#define MGA_WARP_TGZS (MGA_S)
59#define MGA_WARP_TGZSF (MGA_S|MGA_F)
60#define MGA_WARP_TGZSA (MGA_S|MGA_A)
61#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A)
62#define MGA_WARP_T2GZ (MGA_T2)
63#define MGA_WARP_T2GZF (MGA_T2|MGA_F)
64#define MGA_WARP_T2GZA (MGA_T2|MGA_A)
65#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F)
66#define MGA_WARP_T2GZS (MGA_T2|MGA_S)
67#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F)
68#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A)
69#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A)
70
71#define MGA_MAX_G200_PIPES 8 /* no multitex */
71#define MGA_MAX_G200_PIPES 8 /* no multitex */
72#define MGA_MAX_G400_PIPES 16
73#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
72#define MGA_MAX_G400_PIPES 16
73#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
74#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */
74#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */
75
76#define MGA_CARD_TYPE_G200 1
77#define MGA_CARD_TYPE_G400 2
78
75
76#define MGA_CARD_TYPE_G200 1
77#define MGA_CARD_TYPE_G400 2
78
79
80#define MGA_FRONT 0x1
81#define MGA_BACK 0x2
82#define MGA_DEPTH 0x4
83
84/* What needs to be changed for the current vertex dma buffer?
85 */
86#define MGA_UPLOAD_CONTEXT 0x1
87#define MGA_UPLOAD_TEX0 0x2
88#define MGA_UPLOAD_TEX1 0x4
89#define MGA_UPLOAD_PIPE 0x8
79#define MGA_FRONT 0x1
80#define MGA_BACK 0x2
81#define MGA_DEPTH 0x4
82
83/* What needs to be changed for the current vertex dma buffer?
84 */
85#define MGA_UPLOAD_CONTEXT 0x1
86#define MGA_UPLOAD_TEX0 0x2
87#define MGA_UPLOAD_TEX1 0x4
88#define MGA_UPLOAD_PIPE 0x8
90#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */
91#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */
89#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */
90#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */
92#define MGA_UPLOAD_2D 0x40
91#define MGA_UPLOAD_2D 0x40
93#define MGA_WAIT_AGE 0x80 /* handled client-side */
94#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */
92#define MGA_WAIT_AGE 0x80 /* handled client-side */
93#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */
95#if 0
94#if 0
96#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock
97 quiescent */
95#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock
96 quiescent */
98#endif
99
100/* 32 buffers of 64k each, total 2 meg.
101 */
102#define MGA_BUFFER_SIZE (1 << 16)
103#define MGA_NUM_BUFFERS 128
104
105/* Keep these small for testing.

--- 10 unchanged lines hidden (view full) ---

116#define MGA_CARD_HEAP 0
117#define MGA_AGP_HEAP 1
118#define MGA_NR_TEX_HEAPS 2
119#define MGA_NR_TEX_REGIONS 16
120#define MGA_LOG_MIN_TEX_REGION_SIZE 16
121
122#define DRM_MGA_IDLE_RETRY 2048
123
97#endif
98
99/* 32 buffers of 64k each, total 2 meg.
100 */
101#define MGA_BUFFER_SIZE (1 << 16)
102#define MGA_NUM_BUFFERS 128
103
104/* Keep these small for testing.

--- 10 unchanged lines hidden (view full) ---

115#define MGA_CARD_HEAP 0
116#define MGA_AGP_HEAP 1
117#define MGA_NR_TEX_HEAPS 2
118#define MGA_NR_TEX_REGIONS 16
119#define MGA_LOG_MIN_TEX_REGION_SIZE 16
120
121#define DRM_MGA_IDLE_RETRY 2048
122
124#endif /* __MGA_SAREA_DEFINES__ */
123#endif /* __MGA_SAREA_DEFINES__ */
125
124
126
127/* Setup registers for 3D context
128 */
129typedef struct {
130 unsigned int dstorg;
131 unsigned int maccess;
132 unsigned int plnwt;
133 unsigned int dwgctl;
134 unsigned int alphactrl;

--- 26 unchanged lines hidden (view full) ---

161 unsigned int texorg2;
162 unsigned int texorg3;
163 unsigned int texorg4;
164} drm_mga_texture_regs_t;
165
166/* General aging mechanism
167 */
168typedef struct {
125/* Setup registers for 3D context
126 */
127typedef struct {
128 unsigned int dstorg;
129 unsigned int maccess;
130 unsigned int plnwt;
131 unsigned int dwgctl;
132 unsigned int alphactrl;

--- 26 unchanged lines hidden (view full) ---

159 unsigned int texorg2;
160 unsigned int texorg3;
161 unsigned int texorg4;
162} drm_mga_texture_regs_t;
163
164/* General aging mechanism
165 */
166typedef struct {
169 unsigned int head; /* Position of head pointer */
170 unsigned int wrap; /* Primary DMA wrap count */
167 unsigned int head; /* Position of head pointer */
168 unsigned int wrap; /* Primary DMA wrap count */
171} drm_mga_age_t;
172
173typedef struct _drm_mga_sarea {
174 /* The channel for communication of state information to the kernel
175 * on firing a vertex dma buffer.
176 */
169} drm_mga_age_t;
170
171typedef struct _drm_mga_sarea {
172 /* The channel for communication of state information to the kernel
173 * on firing a vertex dma buffer.
174 */
177 drm_mga_context_regs_t context_state;
178 drm_mga_server_regs_t server_state;
179 drm_mga_texture_regs_t tex_state[2];
180 unsigned int warp_pipe;
181 unsigned int dirty;
182 unsigned int vertsize;
175 drm_mga_context_regs_t context_state;
176 drm_mga_server_regs_t server_state;
177 drm_mga_texture_regs_t tex_state[2];
178 unsigned int warp_pipe;
179 unsigned int dirty;
180 unsigned int vertsize;
183
184 /* The current cliprects, or a subset thereof.
185 */
181
182 /* The current cliprects, or a subset thereof.
183 */
186 drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
187 unsigned int nbox;
184 drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS];
185 unsigned int nbox;
188
189 /* Information about the most recently used 3d drawable. The
190 * client fills in the req_* fields, the server fills in the
191 * exported_ fields and puts the cliprects into boxes, above.
192 *
193 * The client clears the exported_drawable field before
194 * clobbering the boxes data.
195 */
186
187 /* Information about the most recently used 3d drawable. The
188 * client fills in the req_* fields, the server fills in the
189 * exported_ fields and puts the cliprects into boxes, above.
190 *
191 * The client clears the exported_drawable field before
192 * clobbering the boxes data.
193 */
196 unsigned int req_drawable; /* the X drawable id */
197 unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */
194 unsigned int req_drawable; /* the X drawable id */
195 unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */
198
196
199 unsigned int exported_drawable;
197 unsigned int exported_drawable;
200 unsigned int exported_index;
198 unsigned int exported_index;
201 unsigned int exported_stamp;
202 unsigned int exported_buffers;
203 unsigned int exported_nfront;
204 unsigned int exported_nback;
199 unsigned int exported_stamp;
200 unsigned int exported_buffers;
201 unsigned int exported_nfront;
202 unsigned int exported_nback;
205 int exported_back_x, exported_front_x, exported_w;
206 int exported_back_y, exported_front_y, exported_h;
203 int exported_back_x, exported_front_x, exported_w;
204 int exported_back_y, exported_front_y, exported_h;
207 drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
205 drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS];
208
209 /* Counters for aging textures and for client-side throttling.
210 */
211 unsigned int status[4];
212 unsigned int last_wrap;
213
214 drm_mga_age_t last_frame;
206
207 /* Counters for aging textures and for client-side throttling.
208 */
209 unsigned int status[4];
210 unsigned int last_wrap;
211
212 drm_mga_age_t last_frame;
215 unsigned int last_enqueue; /* last time a buffer was enqueued */
213 unsigned int last_enqueue; /* last time a buffer was enqueued */
216 unsigned int last_dispatch; /* age of the most recently dispatched buffer */
214 unsigned int last_dispatch; /* age of the most recently dispatched buffer */
217 unsigned int last_quiescent; /* */
215 unsigned int last_quiescent; /* */
218
219 /* LRU lists for texture memory in agp space and on the card.
220 */
216
217 /* LRU lists for texture memory in agp space and on the card.
218 */
221 drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1];
219 drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
222 unsigned int texAge[MGA_NR_TEX_HEAPS];
223
224 /* Mechanism to validate card state.
225 */
220 unsigned int texAge[MGA_NR_TEX_HEAPS];
221
222 /* Mechanism to validate card state.
223 */
226 int ctxOwner;
224 int ctxOwner;
227} drm_mga_sarea_t;
228
225} drm_mga_sarea_t;
226
229
230/* WARNING: If you change any of these defines, make sure to change the
231 * defines in the Xserver file (xf86drmMga.h)
232 */
233
234/* MGA specific ioctls
235 * The device specific ioctl range is 0x40 to 0x79.
236 */
237#define DRM_MGA_INIT 0x00

--- 14 unchanged lines hidden (view full) ---

252#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
253#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
254#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
255#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
256#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
257#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
258
259typedef struct _drm_mga_warp_index {
227/* WARNING: If you change any of these defines, make sure to change the
228 * defines in the Xserver file (xf86drmMga.h)
229 */
230
231/* MGA specific ioctls
232 * The device specific ioctl range is 0x40 to 0x79.
233 */
234#define DRM_MGA_INIT 0x00

--- 14 unchanged lines hidden (view full) ---

249#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
250#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
251#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
252#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
253#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
254#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
255
256typedef struct _drm_mga_warp_index {
260 int installed;
261 unsigned long phys_addr;
262 int size;
257 int installed;
258 unsigned long phys_addr;
259 int size;
263} drm_mga_warp_index_t;
264
265typedef struct drm_mga_init {
260} drm_mga_warp_index_t;
261
262typedef struct drm_mga_init {
266 enum {
267 MGA_INIT_DMA = 0x01,
268 MGA_CLEANUP_DMA = 0x02
263 enum {
264 MGA_INIT_DMA = 0x01,
265 MGA_CLEANUP_DMA = 0x02
269 } func;
270
266 } func;
267
271 unsigned long sarea_priv_offset;
268 unsigned long sarea_priv_offset;
272
273 int chipset;
269
270 int chipset;
274 int sgram;
271 int sgram;
275
276 unsigned int maccess;
277
272
273 unsigned int maccess;
274
278 unsigned int fb_cpp;
275 unsigned int fb_cpp;
279 unsigned int front_offset, front_pitch;
276 unsigned int front_offset, front_pitch;
280 unsigned int back_offset, back_pitch;
277 unsigned int back_offset, back_pitch;
281
278
282 unsigned int depth_cpp;
283 unsigned int depth_offset, depth_pitch;
279 unsigned int depth_cpp;
280 unsigned int depth_offset, depth_pitch;
284
281
285 unsigned int texture_offset[MGA_NR_TEX_HEAPS];
286 unsigned int texture_size[MGA_NR_TEX_HEAPS];
282 unsigned int texture_offset[MGA_NR_TEX_HEAPS];
283 unsigned int texture_size[MGA_NR_TEX_HEAPS];
287
288 unsigned long fb_offset;
289 unsigned long mmio_offset;
290 unsigned long status_offset;
291 unsigned long warp_offset;
292 unsigned long primary_offset;
293 unsigned long buffers_offset;
294} drm_mga_init_t;
295
296typedef struct drm_mga_fullscreen {
297 enum {
284
285 unsigned long fb_offset;
286 unsigned long mmio_offset;
287 unsigned long status_offset;
288 unsigned long warp_offset;
289 unsigned long primary_offset;
290 unsigned long buffers_offset;
291} drm_mga_init_t;
292
293typedef struct drm_mga_fullscreen {
294 enum {
298 MGA_INIT_FULLSCREEN = 0x01,
295 MGA_INIT_FULLSCREEN = 0x01,
299 MGA_CLEANUP_FULLSCREEN = 0x02
300 } func;
301} drm_mga_fullscreen_t;
302
303typedef struct drm_mga_clear {
304 unsigned int flags;
305 unsigned int clear_color;
306 unsigned int clear_depth;
307 unsigned int color_mask;
308 unsigned int depth_mask;
309} drm_mga_clear_t;
310
311typedef struct drm_mga_vertex {
296 MGA_CLEANUP_FULLSCREEN = 0x02
297 } func;
298} drm_mga_fullscreen_t;
299
300typedef struct drm_mga_clear {
301 unsigned int flags;
302 unsigned int clear_color;
303 unsigned int clear_depth;
304 unsigned int color_mask;
305 unsigned int depth_mask;
306} drm_mga_clear_t;
307
308typedef struct drm_mga_vertex {
312 int idx; /* buffer to queue */
313 int used; /* bytes in use */
314 int discard; /* client finished with buffer? */
309 int idx; /* buffer to queue */
310 int used; /* bytes in use */
311 int discard; /* client finished with buffer? */
315} drm_mga_vertex_t;
316
317typedef struct drm_mga_indices {
312} drm_mga_vertex_t;
313
314typedef struct drm_mga_indices {
318 int idx; /* buffer to queue */
315 int idx; /* buffer to queue */
319 unsigned int start;
320 unsigned int end;
316 unsigned int start;
317 unsigned int end;
321 int discard; /* client finished with buffer? */
318 int discard; /* client finished with buffer? */
322} drm_mga_indices_t;
323
324typedef struct drm_mga_iload {
325 int idx;
326 unsigned int dstorg;
327 unsigned int length;
328} drm_mga_iload_t;
329
330typedef struct _drm_mga_blit {
331 unsigned int planemask;
332 unsigned int srcorg;
333 unsigned int dstorg;
334 int src_pitch, dst_pitch;
335 int delta_sx, delta_sy;
336 int delta_dx, delta_dy;
319} drm_mga_indices_t;
320
321typedef struct drm_mga_iload {
322 int idx;
323 unsigned int dstorg;
324 unsigned int length;
325} drm_mga_iload_t;
326
327typedef struct _drm_mga_blit {
328 unsigned int planemask;
329 unsigned int srcorg;
330 unsigned int dstorg;
331 int src_pitch, dst_pitch;
332 int delta_sx, delta_sy;
333 int delta_dx, delta_dy;
337 int height, ydir; /* flip image vertically */
334 int height, ydir; /* flip image vertically */
338 int source_pitch, dest_pitch;
339} drm_mga_blit_t;
340
341/* 3.1: An ioctl to get parameters that aren't available to the 3d
335 int source_pitch, dest_pitch;
336} drm_mga_blit_t;
337
338/* 3.1: An ioctl to get parameters that aren't available to the 3d
342 * client any other way.
339 * client any other way.
343 */
344#define MGA_PARAM_IRQ_NR 1
345
346typedef struct drm_mga_getparam {
347 int param;
340 */
341#define MGA_PARAM_IRQ_NR 1
342
343typedef struct drm_mga_getparam {
344 int param;
348 void *value;
345 void __user *value;
349} drm_mga_getparam_t;
350
351#endif
346} drm_mga_getparam_t;
347
348#endif