1/**************************************************************************
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8

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23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
28***************************************************************************/
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/cxgb/cxgb_main.c 172105 2007-09-09 20:26:02Z kmacy $");
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/bus.h>
37#include <sys/module.h>
38#include <sys/pciio.h>
39#include <sys/conf.h>

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382}
383
384static int
385cxgb_controller_attach(device_t dev)
386{
387 device_t child;
388 const struct adapter_info *ai;
389 struct adapter *sc;
390 int i, reg, error = 0;
391 uint32_t vers;
392 int port_qsets = 1;
393#ifdef MSI_SUPPORTED
394 int msi_needed;
395#endif
396 sc = device_get_softc(dev);
397 sc->dev = dev;
398 sc->msi_count = 0;
399
400 /* find the PCIe link width and set max read request to 4KB*/
401 if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
402 uint16_t lnk, pectl;
403 lnk = pci_read_config(dev, reg + 0x12, 2);
404 sc->link_width = (lnk >> 4) & 0x3f;
405
406 pectl = pci_read_config(dev, reg + 0x8, 2);
407 pectl = (pectl & ~0x7000) | (5 << 12);
408 pci_write_config(dev, reg + 0x8, pectl, 2);
409 }
410
411 ai = cxgb_get_adapter_info(dev);
412 if (sc->link_width != 0 && sc->link_width <= 4 &&
413 (ai->nports0 + ai->nports1) <= 2) {
414 device_printf(sc->dev,
415 "PCIe x%d Link, expect reduced performance\n",
416 sc->link_width);
417 }
418
419 touch_bars(dev);
420 pci_enable_busmaster(dev);
421 /*
422 * Allocate the registers and make them available to the driver.
423 * The registers that we care about for NIC mode are in BAR 0
424 */
425 sc->regs_rid = PCIR_BAR(0);
426 if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,

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1326
1327 }
1328 }
1329}
1330
1331static void
1332update_tpeeprom(struct adapter *adap)
1333{
1334 const struct firmware *tpeeprom;
1335 char buf[64];
1336 uint32_t version;
1337 unsigned int major, minor;
1338 int ret, len;
1339 char rev;
1340
1341 t3_seeprom_read(adap, TP_SRAM_OFFSET, &version);
1342

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1382 firmware_put(tpeeprom, FIRMWARE_UNLOAD);
1383
1384 return;
1385}
1386
1387static int
1388update_tpsram(struct adapter *adap)
1389{
1390 const struct firmware *tpsram;
1391 char buf[64];
1392 int ret;
1393 char rev;
1394
1395 rev = t3rev2char(adap);
1396 if (!rev)
1397 return 0;
1398

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1822}
1823
1824static int
1825cxgb_start_tx(struct ifnet *ifp, uint32_t txmax)
1826{
1827 struct sge_qset *qs;
1828 struct sge_txq *txq;
1829 struct port_info *p = ifp->if_softc;
1830 struct mbuf *m0, *m = NULL;
1831 int err, in_use_init, free;
1832
1833 if (!p->link_config.link_ok)
1834 return (ENXIO);
1835
1836 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1837 return (ENOBUFS);
1838

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1851 free = 0;
1852 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1853 if (m == NULL)
1854 break;
1855 /*
1856 * Convert chain to M_IOVEC
1857 */
1858 KASSERT((m->m_flags & M_IOVEC) == 0, ("IOVEC set too early"));
1859 m0 = m;
1860#ifdef INVARIANTS
1861 /*
1862 * Clean up after net stack sloppiness
1863 * before calling m_sanity
1864 */
1865 m0 = m->m_next;
1866 while (m0) {
1867 m0->m_flags &= ~M_PKTHDR;
1868 m0 = m0->m_next;
1869 }
1870 m_sanity(m0, 0);
1871 m0 = m;
1872#endif
1873 if (collapse_mbufs && m->m_pkthdr.len > MCLBYTES &&
1874 m_collapse(m, TX_MAX_SEGS, &m0) == EFBIG) {
1875 if ((m0 = m_defrag(m, M_NOWAIT)) != NULL) {
1876 m = m0;
1877 m_collapse(m, TX_MAX_SEGS, &m0);
1878 } else
1879 break;
1880 }
1881 m = m0;
1882 if ((err = t3_encap(p, &m, &free)) != 0)
1883 break;
1884 BPF_MTAP(ifp, m);
1885 if (free)
1886 m_freem(m);
1887 }
1888 txq->flags &= ~TXQ_TRANSMITTING;
1889 mtx_unlock(&txq->lock);

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