33
34***************************************************************************/
35#ifndef T3_CPL_H
36#define T3_CPL_H
37
38#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
39# include <asm/byteorder.h>
40#endif
41
42enum CPL_opcode {
43 CPL_PASS_OPEN_REQ = 0x1,
44 CPL_PASS_ACCEPT_RPL = 0x2,
45 CPL_ACT_OPEN_REQ = 0x3,
46 CPL_SET_TCB = 0x4,
47 CPL_SET_TCB_FIELD = 0x5,
48 CPL_GET_TCB = 0x6,
49 CPL_PCMD = 0x7,
50 CPL_CLOSE_CON_REQ = 0x8,
51 CPL_CLOSE_LISTSRV_REQ = 0x9,
52 CPL_ABORT_REQ = 0xA,
53 CPL_ABORT_RPL = 0xB,
54 CPL_TX_DATA = 0xC,
55 CPL_RX_DATA_ACK = 0xD,
56 CPL_TX_PKT = 0xE,
57 CPL_RTE_DELETE_REQ = 0xF,
58 CPL_RTE_WRITE_REQ = 0x10,
59 CPL_RTE_READ_REQ = 0x11,
60 CPL_L2T_WRITE_REQ = 0x12,
61 CPL_L2T_READ_REQ = 0x13,
62 CPL_SMT_WRITE_REQ = 0x14,
63 CPL_SMT_READ_REQ = 0x15,
64 CPL_TX_PKT_LSO = 0x16,
65 CPL_PCMD_READ = 0x17,
66 CPL_BARRIER = 0x18,
67 CPL_TID_RELEASE = 0x1A,
68
69 CPL_CLOSE_LISTSRV_RPL = 0x20,
70 CPL_ERROR = 0x21,
71 CPL_GET_TCB_RPL = 0x22,
72 CPL_L2T_WRITE_RPL = 0x23,
73 CPL_PCMD_READ_RPL = 0x24,
74 CPL_PCMD_RPL = 0x25,
75 CPL_PEER_CLOSE = 0x26,
76 CPL_RTE_DELETE_RPL = 0x27,
77 CPL_RTE_WRITE_RPL = 0x28,
78 CPL_RX_DDP_COMPLETE = 0x29,
79 CPL_RX_PHYS_ADDR = 0x2A,
80 CPL_RX_PKT = 0x2B,
81 CPL_RX_URG_NOTIFY = 0x2C,
82 CPL_SET_TCB_RPL = 0x2D,
83 CPL_SMT_WRITE_RPL = 0x2E,
84 CPL_TX_DATA_ACK = 0x2F,
85
86 CPL_ABORT_REQ_RSS = 0x30,
87 CPL_ABORT_RPL_RSS = 0x31,
88 CPL_CLOSE_CON_RPL = 0x32,
89 CPL_ISCSI_HDR = 0x33,
90 CPL_L2T_READ_RPL = 0x34,
91 CPL_RDMA_CQE = 0x35,
92 CPL_RDMA_CQE_READ_RSP = 0x36,
93 CPL_RDMA_CQE_ERR = 0x37,
94 CPL_RTE_READ_RPL = 0x38,
95 CPL_RX_DATA = 0x39,
96
97 CPL_ACT_OPEN_RPL = 0x40,
98 CPL_PASS_OPEN_RPL = 0x41,
99 CPL_RX_DATA_DDP = 0x42,
100 CPL_SMT_READ_RPL = 0x43,
101
102 CPL_ACT_ESTABLISH = 0x50,
103 CPL_PASS_ESTABLISH = 0x51,
104
105 CPL_PASS_ACCEPT_REQ = 0x70,
106
107 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */
108
109 CPL_TX_DMA_ACK = 0xA0,
110 CPL_RDMA_READ_REQ = 0xA1,
111 CPL_RDMA_TERMINATE = 0xA2,
112 CPL_TRACE_PKT = 0xA3,
113 CPL_RDMA_EC_STATUS = 0xA5,
114
115 NUM_CPL_CMDS /* must be last and previous entries must be sorted */
116};
117
118enum CPL_error {
119 CPL_ERR_NONE = 0,
120 CPL_ERR_TCAM_PARITY = 1,
121 CPL_ERR_TCAM_FULL = 3,
122 CPL_ERR_CONN_RESET = 20,
123 CPL_ERR_CONN_EXIST = 22,
124 CPL_ERR_ARP_MISS = 23,
125 CPL_ERR_BAD_SYN = 24,
126 CPL_ERR_CONN_TIMEDOUT = 30,
127 CPL_ERR_XMIT_TIMEDOUT = 31,
128 CPL_ERR_PERSIST_TIMEDOUT = 32,
129 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
130 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
131 CPL_ERR_RTX_NEG_ADVICE = 35,
132 CPL_ERR_PERSIST_NEG_ADVICE = 36,
133 CPL_ERR_ABORT_FAILED = 42,
134 CPL_ERR_GENERAL = 99
135};
136
137enum {
138 CPL_CONN_POLICY_AUTO = 0,
139 CPL_CONN_POLICY_ASK = 1,
140 CPL_CONN_POLICY_DENY = 3
141};
142
143enum {
144 ULP_MODE_NONE = 0,
145 ULP_MODE_TCP_DDP = 1,
146 ULP_MODE_ISCSI = 2,
147 ULP_MODE_RDMA = 4,
148 ULP_MODE_TCPDDP = 5
149};
150
151enum {
152 ULP_CRC_HEADER = 1 << 0,
153 ULP_CRC_DATA = 1 << 1
154};
155
156enum {
157 CPL_PASS_OPEN_ACCEPT,
158 CPL_PASS_OPEN_REJECT
159};
160
161enum {
162 CPL_ABORT_SEND_RST = 0,
163 CPL_ABORT_NO_RST,
164 CPL_ABORT_POST_CLOSE_REQ = 2
165};
166
167enum { /* TX_PKT_LSO ethernet types */
168 CPL_ETH_II,
169 CPL_ETH_II_VLAN,
170 CPL_ETH_802_3,
171 CPL_ETH_802_3_VLAN
172};
173
174enum { /* TCP congestion control algorithms */
175 CONG_ALG_RENO,
176 CONG_ALG_TAHOE,
177 CONG_ALG_NEWRENO,
178 CONG_ALG_HIGHSPEED
179};
180
181enum { /* RSS hash type */
182 RSS_HASH_NONE = 0,
183 RSS_HASH_2_TUPLE = 1 << 0,
184 RSS_HASH_4_TUPLE = 1 << 1
185};
186
187union opcode_tid {
188 __be32 opcode_tid;
189 __u8 opcode;
190};
191
192#define S_OPCODE 24
193#define V_OPCODE(x) ((x) << S_OPCODE)
194#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
195#define G_TID(x) ((x) & 0xFFFFFF)
196
197#define S_HASHTYPE 22
198#define M_HASHTYPE 0x3
199#define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
200
201#define S_QNUM 0
202#define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF)
203
204/* tid is assumed to be 24-bits */
205#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
206
207#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
208
209/* extract the TID from a CPL command */
210#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
211
212struct tcp_options {
213 __be16 mss;
214 __u8 wsf;
215#if defined(__LITTLE_ENDIAN_BITFIELD)
216 __u8 :5;
217 __u8 ecn:1;
218 __u8 sack:1;
219 __u8 tstamp:1;
220#else
221 __u8 tstamp:1;
222 __u8 sack:1;
223 __u8 ecn:1;
224 __u8 :5;
225#endif
226};
227
228struct rss_header {
229 __u8 opcode;
230#if defined(__LITTLE_ENDIAN_BITFIELD)
231 __u8 cpu_idx:6;
232 __u8 hash_type:2;
233#else
234 __u8 hash_type:2;
235 __u8 cpu_idx:6;
236#endif
237 __be16 cq_idx;
238 __be32 rss_hash_val;
239};
240
241#ifndef CHELSIO_FW
242struct work_request_hdr {
243 __be32 wr_hi;
244 __be32 wr_lo;
245};
246
247/* wr_hi fields */
248#define S_WR_SGE_CREDITS 0
249#define M_WR_SGE_CREDITS 0xFF
250#define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS)
251#define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS)
252
253#define S_WR_SGLSFLT 8
254#define M_WR_SGLSFLT 0xFF
255#define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT)
256#define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT)
257
258#define S_WR_BCNTLFLT 16
259#define M_WR_BCNTLFLT 0xF
260#define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
261#define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
262
263/* Applicable to BYPASS WRs only: the uP will added a CPL_BARRIER before
264 * and after the BYPASS WR if the ATOMIC bit is set.
265 */
266#define S_WR_ATOMIC 16
267#define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC)
268#define F_WR_ATOMIC V_WR_ATOMIC(1U)
269
270/* Applicable to BYPASS WRs only: the uP will flush buffered non abort
271 * related WRs.
272 */
273#define S_WR_FLUSH 17
274#define V_WR_FLUSH(x) ((x) << S_WR_FLUSH)
275#define F_WR_FLUSH V_WR_FLUSH(1U)
276
277#define S_WR_DATATYPE 20
278#define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
279#define F_WR_DATATYPE V_WR_DATATYPE(1U)
280
281#define S_WR_COMPL 21
282#define V_WR_COMPL(x) ((x) << S_WR_COMPL)
283#define F_WR_COMPL V_WR_COMPL(1U)
284
285#define S_WR_EOP 22
286#define V_WR_EOP(x) ((x) << S_WR_EOP)
287#define F_WR_EOP V_WR_EOP(1U)
288
289#define S_WR_SOP 23
290#define V_WR_SOP(x) ((x) << S_WR_SOP)
291#define F_WR_SOP V_WR_SOP(1U)
292
293#define S_WR_OP 24
294#define M_WR_OP 0xFF
295#define V_WR_OP(x) ((x) << S_WR_OP)
296#define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
297
298/* wr_lo fields */
299#define S_WR_LEN 0
300#define M_WR_LEN 0xFF
301#define V_WR_LEN(x) ((x) << S_WR_LEN)
302#define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN)
303
304#define S_WR_TID 8
305#define M_WR_TID 0xFFFFF
306#define V_WR_TID(x) ((x) << S_WR_TID)
307#define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID)
308
309#define S_WR_CR_FLUSH 30
310#define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH)
311#define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U)
312
313#define S_WR_GEN 31
314#define V_WR_GEN(x) ((x) << S_WR_GEN)
315#define F_WR_GEN V_WR_GEN(1U)
316
317# define WR_HDR struct work_request_hdr wr
318# define RSS_HDR
319#else
320# define WR_HDR
321# define RSS_HDR struct rss_header rss_hdr;
322#endif
323
324/* option 0 lower-half fields */
325#define S_CPL_STATUS 0
326#define M_CPL_STATUS 0xFF
327#define V_CPL_STATUS(x) ((x) << S_CPL_STATUS)
328#define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS)
329
330#define S_INJECT_TIMER 6
331#define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
332#define F_INJECT_TIMER V_INJECT_TIMER(1U)
333
334#define S_NO_OFFLOAD 7
335#define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD)
336#define F_NO_OFFLOAD V_NO_OFFLOAD(1U)
337
338#define S_ULP_MODE 8
339#define M_ULP_MODE 0xF
340#define V_ULP_MODE(x) ((x) << S_ULP_MODE)
341#define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
342
343#define S_RCV_BUFSIZ 12
344#define M_RCV_BUFSIZ 0x3FFF
345#define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
346#define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
347
348#define S_TOS 26
349#define M_TOS 0x3F
350#define V_TOS(x) ((x) << S_TOS)
351#define G_TOS(x) (((x) >> S_TOS) & M_TOS)
352
353/* option 0 upper-half fields */
354#define S_DELACK 0
355#define V_DELACK(x) ((x) << S_DELACK)
356#define F_DELACK V_DELACK(1U)
357
358#define S_NO_CONG 1
359#define V_NO_CONG(x) ((x) << S_NO_CONG)
360#define F_NO_CONG V_NO_CONG(1U)
361
362#define S_SRC_MAC_SEL 2
363#define M_SRC_MAC_SEL 0x3
364#define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL)
365#define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL)
366
367#define S_L2T_IDX 4
368#define M_L2T_IDX 0x7FF
369#define V_L2T_IDX(x) ((x) << S_L2T_IDX)
370#define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
371
372#define S_TX_CHANNEL 15
373#define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL)
374#define F_TX_CHANNEL V_TX_CHANNEL(1U)
375
376#define S_TCAM_BYPASS 16
377#define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS)
378#define F_TCAM_BYPASS V_TCAM_BYPASS(1U)
379
380#define S_NAGLE 17
381#define V_NAGLE(x) ((x) << S_NAGLE)
382#define F_NAGLE V_NAGLE(1U)
383
384#define S_WND_SCALE 18
385#define M_WND_SCALE 0xF
386#define V_WND_SCALE(x) ((x) << S_WND_SCALE)
387#define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
388
389#define S_KEEP_ALIVE 22
390#define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE)
391#define F_KEEP_ALIVE V_KEEP_ALIVE(1U)
392
393#define S_MAX_RETRANS 23
394#define M_MAX_RETRANS 0xF
395#define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS)
396#define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS)
397
398#define S_MAX_RETRANS_OVERRIDE 27
399#define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE)
400#define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U)
401
402#define S_MSS_IDX 28
403#define M_MSS_IDX 0xF
404#define V_MSS_IDX(x) ((x) << S_MSS_IDX)
405#define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
406
407/* option 1 fields */
408#define S_RSS_ENABLE 0
409#define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE)
410#define F_RSS_ENABLE V_RSS_ENABLE(1U)
411
412#define S_RSS_MASK_LEN 1
413#define M_RSS_MASK_LEN 0x7
414#define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
415#define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
416
417#define S_CPU_IDX 4
418#define M_CPU_IDX 0x3F
419#define V_CPU_IDX(x) ((x) << S_CPU_IDX)
420#define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
421
422#define S_MAC_MATCH_VALID 18
423#define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
424#define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U)
425
426#define S_CONN_POLICY 19
427#define M_CONN_POLICY 0x3
428#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
429#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
430
431#define S_SYN_DEFENSE 21
432#define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
433#define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
434
435#define S_VLAN_PRI 22
436#define M_VLAN_PRI 0x3
437#define V_VLAN_PRI(x) ((x) << S_VLAN_PRI)
438#define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI)
439
440#define S_VLAN_PRI_VALID 24
441#define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID)
442#define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U)
443
444#define S_PKT_TYPE 25
445#define M_PKT_TYPE 0x3
446#define V_PKT_TYPE(x) ((x) << S_PKT_TYPE)
447#define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE)
448
449#define S_MAC_MATCH 27
450#define M_MAC_MATCH 0x1F
451#define V_MAC_MATCH(x) ((x) << S_MAC_MATCH)
452#define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH)
453
454/* option 2 fields */
455#define S_CPU_INDEX 0
456#define M_CPU_INDEX 0x7F
457#define V_CPU_INDEX(x) ((x) << S_CPU_INDEX)
458#define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX)
459
460#define S_CPU_INDEX_VALID 7
461#define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID)
462#define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U)
463
464#define S_RX_COALESCE 8
465#define M_RX_COALESCE 0x3
466#define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
467#define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
468
469#define S_RX_COALESCE_VALID 10
470#define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
471#define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U)
472
473#define S_CONG_CONTROL_FLAVOR 11
474#define M_CONG_CONTROL_FLAVOR 0x3
475#define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR)
476#define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR)
477
478#define S_PACING_FLAVOR 13
479#define M_PACING_FLAVOR 0x3
480#define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR)
481#define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR)
482
483#define S_FLAVORS_VALID 15
484#define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID)
485#define F_FLAVORS_VALID V_FLAVORS_VALID(1U)
486
487#define S_RX_FC_DISABLE 16
488#define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
489#define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U)
490
491#define S_RX_FC_VALID 17
492#define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
493#define F_RX_FC_VALID V_RX_FC_VALID(1U)
494
495struct cpl_pass_open_req {
496 WR_HDR;
497 union opcode_tid ot;
498 __be16 local_port;
499 __be16 peer_port;
500 __be32 local_ip;
501 __be32 peer_ip;
502 __be32 opt0h;
503 __be32 opt0l;
504 __be32 peer_netmask;
505 __be32 opt1;
506};
507
508struct cpl_pass_open_rpl {
509 RSS_HDR
510 union opcode_tid ot;
511 __be16 local_port;
512 __be16 peer_port;
513 __be32 local_ip;
514 __be32 peer_ip;
515 __u8 resvd[7];
516 __u8 status;
517};
518
519struct cpl_pass_establish {
520 RSS_HDR
521 union opcode_tid ot;
522 __be16 local_port;
523 __be16 peer_port;
524 __be32 local_ip;
525 __be32 peer_ip;
526 __be32 tos_tid;
527 __be16 l2t_idx;
528 __be16 tcp_opt;
529 __be32 snd_isn;
530 __be32 rcv_isn;
531};
532
533/* cpl_pass_establish.tos_tid fields */
534#define S_PASS_OPEN_TID 0
535#define M_PASS_OPEN_TID 0xFFFFFF
536#define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
537#define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
538
539#define S_PASS_OPEN_TOS 24
540#define M_PASS_OPEN_TOS 0xFF
541#define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
542#define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
543
544/* cpl_pass_establish.l2t_idx fields */
545#define S_L2T_IDX16 5
546#define M_L2T_IDX16 0x7FF
547#define V_L2T_IDX16(x) ((x) << S_L2T_IDX16)
548#define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16)
549
550/* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */
551#define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
552#define G_TCPOPT_SACK(x) (((x) >> 6) & 1)
553#define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
554#define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
555#define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
556
557struct cpl_pass_accept_req {
558 RSS_HDR
559 union opcode_tid ot;
560 __be16 local_port;
561 __be16 peer_port;
562 __be32 local_ip;
563 __be32 peer_ip;
564 __be32 tos_tid;
565 struct tcp_options tcp_options;
566 __u8 dst_mac[6];
567 __be16 vlan_tag;
568 __u8 src_mac[6];
569#if defined(__LITTLE_ENDIAN_BITFIELD)
570 __u8 :3;
571 __u8 addr_idx:3;
572 __u8 port_idx:1;
573 __u8 exact_match:1;
574#else
575 __u8 exact_match:1;
576 __u8 port_idx:1;
577 __u8 addr_idx:3;
578 __u8 :3;
579#endif
580 __u8 rsvd;
581 __be32 rcv_isn;
582 __be32 rsvd2;
583};
584
585struct cpl_pass_accept_rpl {
586 WR_HDR;
587 union opcode_tid ot;
588 __be32 opt2;
589 __be32 rsvd;
590 __be32 peer_ip;
591 __be32 opt0h;
592 __be32 opt0l_status;
593};
594
595struct cpl_act_open_req {
596 WR_HDR;
597 union opcode_tid ot;
598 __be16 local_port;
599 __be16 peer_port;
600 __be32 local_ip;
601 __be32 peer_ip;
602 __be32 opt0h;
603 __be32 opt0l;
604 __be32 params;
605 __be32 opt2;
606};
607
608/* cpl_act_open_req.params fields */
609#define S_AOPEN_VLAN_PRI 9
610#define M_AOPEN_VLAN_PRI 0x3
611#define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI)
612#define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI)
613
614#define S_AOPEN_VLAN_PRI_VALID 11
615#define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID)
616#define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U)
617
618#define S_AOPEN_PKT_TYPE 12
619#define M_AOPEN_PKT_TYPE 0x3
620#define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE)
621#define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE)
622
623#define S_AOPEN_MAC_MATCH 14
624#define M_AOPEN_MAC_MATCH 0x1F
625#define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH)
626#define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH)
627
628#define S_AOPEN_MAC_MATCH_VALID 19
629#define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID)
630#define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U)
631
632#define S_AOPEN_IFF_VLAN 20
633#define M_AOPEN_IFF_VLAN 0xFFF
634#define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN)
635#define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN)
636
637struct cpl_act_open_rpl {
638 RSS_HDR
639 union opcode_tid ot;
640 __be16 local_port;
641 __be16 peer_port;
642 __be32 local_ip;
643 __be32 peer_ip;
644 __be32 atid;
645 __u8 rsvd[3];
646 __u8 status;
647};
648
649struct cpl_act_establish {
650 RSS_HDR
651 union opcode_tid ot;
652 __be16 local_port;
653 __be16 peer_port;
654 __be32 local_ip;
655 __be32 peer_ip;
656 __be32 tos_tid;
657 __be16 l2t_idx;
658 __be16 tcp_opt;
659 __be32 snd_isn;
660 __be32 rcv_isn;
661};
662
663struct cpl_get_tcb {
664 WR_HDR;
665 union opcode_tid ot;
666 __be16 cpuno;
667 __be16 rsvd;
668};
669
670struct cpl_get_tcb_rpl {
671 RSS_HDR
672 union opcode_tid ot;
673 __u8 rsvd;
674 __u8 status;
675 __be16 len;
676};
677
678struct cpl_set_tcb {
679 WR_HDR;
680 union opcode_tid ot;
681 __u8 reply;
682 __u8 cpu_idx;
683 __be16 len;
684};
685
686/* cpl_set_tcb.reply fields */
687#define S_NO_REPLY 7
688#define V_NO_REPLY(x) ((x) << S_NO_REPLY)
689#define F_NO_REPLY V_NO_REPLY(1U)
690
691struct cpl_set_tcb_field {
692 WR_HDR;
693 union opcode_tid ot;
694 __u8 reply;
695 __u8 cpu_idx;
696 __be16 word;
697 __be64 mask;
698 __be64 val;
699};
700
701struct cpl_set_tcb_rpl {
702 RSS_HDR
703 union opcode_tid ot;
704 __u8 rsvd[3];
705 __u8 status;
706};
707
708struct cpl_pcmd {
709 WR_HDR;
710 union opcode_tid ot;
711 __u8 rsvd[3];
712#if defined(__LITTLE_ENDIAN_BITFIELD)
713 __u8 src:1;
714 __u8 bundle:1;
715 __u8 channel:1;
716 __u8 :5;
717#else
718 __u8 :5;
719 __u8 channel:1;
720 __u8 bundle:1;
721 __u8 src:1;
722#endif
723 __be32 pcmd_parm[2];
724};
725
726struct cpl_pcmd_reply {
727 RSS_HDR
728 union opcode_tid ot;
729 __u8 status;
730 __u8 rsvd;
731 __be16 len;
732};
733
734struct cpl_close_con_req {
735 WR_HDR;
736 union opcode_tid ot;
737 __be32 rsvd;
738};
739
740struct cpl_close_con_rpl {
741 RSS_HDR
742 union opcode_tid ot;
743 __u8 rsvd[3];
744 __u8 status;
745 __be32 snd_nxt;
746 __be32 rcv_nxt;
747};
748
749struct cpl_close_listserv_req {
750 WR_HDR;
751 union opcode_tid ot;
752 __u8 rsvd0;
753 __u8 cpu_idx;
754 __be16 rsvd1;
755};
756
757struct cpl_close_listserv_rpl {
758 RSS_HDR
759 union opcode_tid ot;
760 __u8 rsvd[3];
761 __u8 status;
762};
763
764struct cpl_abort_req_rss {
765 RSS_HDR
766 union opcode_tid ot;
767 __be32 rsvd0;
768 __u8 rsvd1;
769 __u8 status;
770 __u8 rsvd2[6];
771};
772
773struct cpl_abort_req {
774 WR_HDR;
775 union opcode_tid ot;
776 __be32 rsvd0;
777 __u8 rsvd1;
778 __u8 cmd;
779 __u8 rsvd2[6];
780};
781
782struct cpl_abort_rpl_rss {
783 RSS_HDR
784 union opcode_tid ot;
785 __be32 rsvd0;
786 __u8 rsvd1;
787 __u8 status;
788 __u8 rsvd2[6];
789};
790
791struct cpl_abort_rpl {
792 WR_HDR;
793 union opcode_tid ot;
794 __be32 rsvd0;
795 __u8 rsvd1;
796 __u8 cmd;
797 __u8 rsvd2[6];
798};
799
800struct cpl_peer_close {
801 RSS_HDR
802 union opcode_tid ot;
803 __be32 rcv_nxt;
804};
805
806struct tx_data_wr {
807 __be32 wr_hi;
808 __be32 wr_lo;
809 __be32 len;
810 __be32 flags;
811 __be32 sndseq;
812 __be32 param;
813};
814
815/* tx_data_wr.param fields */
816#define S_TX_PORT 0
817#define M_TX_PORT 0x7
818#define V_TX_PORT(x) ((x) << S_TX_PORT)
819#define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
820
821#define S_TX_MSS 4
822#define M_TX_MSS 0xF
823#define V_TX_MSS(x) ((x) << S_TX_MSS)
824#define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
825
826#define S_TX_QOS 8
827#define M_TX_QOS 0xFF
828#define V_TX_QOS(x) ((x) << S_TX_QOS)
829#define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
830
831#define S_TX_SNDBUF 16
832#define M_TX_SNDBUF 0xFFFF
833#define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
834#define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
835
836struct cpl_tx_data {
837 union opcode_tid ot;
838 __be32 len;
839 __be32 rsvd;
840 __be16 urg;
841 __be16 flags;
842};
843
844/* cpl_tx_data.flags fields */
845#define S_TX_ULP_SUBMODE 6
846#define M_TX_ULP_SUBMODE 0xF
847#define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
848#define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
849
850#define S_TX_ULP_MODE 10
851#define M_TX_ULP_MODE 0xF
852#define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
853#define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
854
855#define S_TX_SHOVE 14
856#define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
857#define F_TX_SHOVE V_TX_SHOVE(1U)
858
859#define S_TX_MORE 15
860#define V_TX_MORE(x) ((x) << S_TX_MORE)
861#define F_TX_MORE V_TX_MORE(1U)
862
863/* additional tx_data_wr.flags fields */
864#define S_TX_CPU_IDX 0
865#define M_TX_CPU_IDX 0x3F
866#define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
867#define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
868
869#define S_TX_URG 16
870#define V_TX_URG(x) ((x) << S_TX_URG)
871#define F_TX_URG V_TX_URG(1U)
872
873#define S_TX_CLOSE 17
874#define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
875#define F_TX_CLOSE V_TX_CLOSE(1U)
876
877#define S_TX_INIT 18
878#define V_TX_INIT(x) ((x) << S_TX_INIT)
879#define F_TX_INIT V_TX_INIT(1U)
880
881#define S_TX_IMM_ACK 19
882#define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
883#define F_TX_IMM_ACK V_TX_IMM_ACK(1U)
884
885#define S_TX_IMM_DMA 20
886#define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
887#define F_TX_IMM_DMA V_TX_IMM_DMA(1U)
888
889struct cpl_tx_data_ack {
890 RSS_HDR
891 union opcode_tid ot;
892 __be32 ack_seq;
893};
894
895struct cpl_wr_ack {
896 RSS_HDR
897 union opcode_tid ot;
898 __be16 credits;
899 __be16 rsvd;
900 __be32 snd_nxt;
901 __be32 snd_una;
902};
903
904struct cpl_rdma_ec_status {
905 RSS_HDR
906 union opcode_tid ot;
907 __u8 rsvd[3];
908 __u8 status;
909};
910
911struct mngt_pktsched_wr {
912 __be32 wr_hi;
913 __be32 wr_lo;
914 __u8 mngt_opcode;
915 __u8 rsvd[7];
916 __u8 sched;
917 __u8 idx;
918 __u8 min;
919 __u8 max;
920 __u8 binding;
921 __u8 rsvd1[3];
922};
923
924struct cpl_iscsi_hdr {
925 RSS_HDR
926 union opcode_tid ot;
927 __be16 pdu_len_ddp;
928 __be16 len;
929 __be32 seq;
930 __be16 urg;
931 __u8 rsvd;
932 __u8 status;
933};
934
935/* cpl_iscsi_hdr.pdu_len_ddp fields */
936#define S_ISCSI_PDU_LEN 0
937#define M_ISCSI_PDU_LEN 0x7FFF
938#define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
939#define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
940
941#define S_ISCSI_DDP 15
942#define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
943#define F_ISCSI_DDP V_ISCSI_DDP(1U)
944
945struct cpl_rx_data {
946 RSS_HDR
947 union opcode_tid ot;
948 __be16 rsvd;
949 __be16 len;
950 __be32 seq;
951 __be16 urg;
952#if defined(__LITTLE_ENDIAN_BITFIELD)
953 __u8 dack_mode:2;
954 __u8 psh:1;
955 __u8 heartbeat:1;
956 __u8 :4;
957#else
958 __u8 :4;
959 __u8 heartbeat:1;
960 __u8 psh:1;
961 __u8 dack_mode:2;
962#endif
963 __u8 status;
964};
965
966struct cpl_rx_data_ack {
967 WR_HDR;
968 union opcode_tid ot;
969 __be32 credit_dack;
970};
971
972/* cpl_rx_data_ack.ack_seq fields */
973#define S_RX_CREDITS 0
974#define M_RX_CREDITS 0x7FFFFFF
975#define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
976#define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
977
978#define S_RX_MODULATE 27
979#define V_RX_MODULATE(x) ((x) << S_RX_MODULATE)
980#define F_RX_MODULATE V_RX_MODULATE(1U)
981
982#define S_RX_FORCE_ACK 28
983#define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
984#define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U)
985
986#define S_RX_DACK_MODE 29
987#define M_RX_DACK_MODE 0x3
988#define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
989#define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
990
991#define S_RX_DACK_CHANGE 31
992#define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
993#define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
994
995struct cpl_rx_urg_notify {
996 RSS_HDR
997 union opcode_tid ot;
998 __be32 seq;
999};
1000
1001struct cpl_rx_ddp_complete {
1002 RSS_HDR
1003 union opcode_tid ot;
1004 __be32 ddp_report;
1005};
1006
1007struct cpl_rx_data_ddp {
1008 RSS_HDR
1009 union opcode_tid ot;
1010 __be16 urg;
1011 __be16 len;
1012 __be32 seq;
1013 union {
1014 __be32 nxt_seq;
1015 __be32 ddp_report;
1016 } __U;
1017 __be32 ulp_crc;
1018 __be32 ddpvld_status;
1019};
1020
1021/* cpl_rx_data_ddp.ddpvld_status fields */
1022#define S_DDP_STATUS 0
1023#define M_DDP_STATUS 0xFF
1024#define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
1025#define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS)
1026
1027#define S_DDP_VALID 15
1028#define M_DDP_VALID 0x1FFFF
1029#define V_DDP_VALID(x) ((x) << S_DDP_VALID)
1030#define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
1031
1032#define S_DDP_PPOD_MISMATCH 15
1033#define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1034#define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U)
1035
1036#define S_DDP_PDU 16
1037#define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1038#define F_DDP_PDU V_DDP_PDU(1U)
1039
1040#define S_DDP_LLIMIT_ERR 17
1041#define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1042#define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U)
1043
1044#define S_DDP_PPOD_PARITY_ERR 18
1045#define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1046#define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U)
1047
1048#define S_DDP_PADDING_ERR 19
1049#define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1050#define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U)
1051
1052#define S_DDP_HDRCRC_ERR 20
1053#define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1054#define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U)
1055
1056#define S_DDP_DATACRC_ERR 21
1057#define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1058#define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U)
1059
1060#define S_DDP_INVALID_TAG 22
1061#define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1062#define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U)
1063
1064#define S_DDP_ULIMIT_ERR 23
1065#define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1066#define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U)
1067
1068#define S_DDP_OFFSET_ERR 24
1069#define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1070#define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U)
1071
1072#define S_DDP_COLOR_ERR 25
1073#define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1074#define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U)
1075
1076#define S_DDP_TID_MISMATCH 26
1077#define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1078#define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U)
1079
1080#define S_DDP_INVALID_PPOD 27
1081#define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1082#define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U)
1083
1084#define S_DDP_ULP_MODE 28
1085#define M_DDP_ULP_MODE 0xF
1086#define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1087#define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1088
1089/* cpl_rx_data_ddp.ddp_report fields */
1090#define S_DDP_OFFSET 0
1091#define M_DDP_OFFSET 0x3FFFFF
1092#define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1093#define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1094
1095#define S_DDP_URG 24
1096#define V_DDP_URG(x) ((x) << S_DDP_URG)
1097#define F_DDP_URG V_DDP_URG(1U)
1098
1099#define S_DDP_PSH 25
1100#define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1101#define F_DDP_PSH V_DDP_PSH(1U)
1102
1103#define S_DDP_BUF_COMPLETE 26
1104#define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1105#define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U)
1106
1107#define S_DDP_BUF_TIMED_OUT 27
1108#define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1109#define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U)
1110
1111#define S_DDP_BUF_IDX 28
1112#define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1113#define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1114
1115struct cpl_tx_pkt {
1116 WR_HDR;
1117 __be32 cntrl;
1118 __be32 len;
1119};
1120
1121struct cpl_tx_pkt_lso {
1122 WR_HDR;
1123 __be32 cntrl;
1124 __be32 len;
1125
1126 __be32 rsvd;
1127 __be32 lso_info;
1128};
1129
1130/* cpl_tx_pkt*.cntrl fields */
1131#define S_TXPKT_VLAN 0
1132#define M_TXPKT_VLAN 0xFFFF
1133#define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN)
1134#define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1135
1136#define S_TXPKT_INTF 16
1137#define M_TXPKT_INTF 0xF
1138#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1139#define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1140
1141#define S_TXPKT_IPCSUM_DIS 20
1142#define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS)
1143#define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U)
1144
1145#define S_TXPKT_L4CSUM_DIS 21
1146#define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS)
1147#define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U)
1148
1149#define S_TXPKT_VLAN_VLD 22
1150#define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD)
1151#define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U)
1152
1153#define S_TXPKT_LOOPBACK 23
1154#define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1155#define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1156
1157#define S_TXPKT_OPCODE 24
1158#define M_TXPKT_OPCODE 0xFF
1159#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1160#define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1161
1162/* cpl_tx_pkt_lso.lso_info fields */
1163#define S_LSO_MSS 0
1164#define M_LSO_MSS 0x3FFF
1165#define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1166#define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1167
1168#define S_LSO_ETH_TYPE 14
1169#define M_LSO_ETH_TYPE 0x3
1170#define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE)
1171#define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE)
1172
1173#define S_LSO_TCPHDR_WORDS 16
1174#define M_LSO_TCPHDR_WORDS 0xF
1175#define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS)
1176#define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS)
1177
1178#define S_LSO_IPHDR_WORDS 20
1179#define M_LSO_IPHDR_WORDS 0xF
1180#define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS)
1181#define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS)
1182
1183#define S_LSO_IPV6 24
1184#define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1185#define F_LSO_IPV6 V_LSO_IPV6(1U)
1186
1187struct cpl_trace_pkt {
1188#ifdef CHELSIO_FW
1189 __u8 rss_opcode;
1190#if defined(__LITTLE_ENDIAN_BITFIELD)
1191 __u8 err:1;
1192 __u8 :7;
1193#else
1194 __u8 :7;
1195 __u8 err:1;
1196#endif
1197 __u8 rsvd0;
1198#if defined(__LITTLE_ENDIAN_BITFIELD)
1199 __u8 qid:4;
1200 __u8 :4;
1201#else
1202 __u8 :4;
1203 __u8 qid:4;
1204#endif
1205 __be32 tstamp;
1206#endif /* CHELSIO_FW */
1207
1208 __u8 opcode;
1209#if defined(__LITTLE_ENDIAN_BITFIELD)
1210 __u8 iff:4;
1211 __u8 :4;
1212#else
1213 __u8 :4;
1214 __u8 iff:4;
1215#endif
1216 __u8 rsvd[4];
1217 __be16 len;
1218};
1219
1220struct cpl_rx_pkt {
1221 RSS_HDR
1222 __u8 opcode;
1223#if defined(__LITTLE_ENDIAN_BITFIELD)
1224 __u8 iff:4;
1225 __u8 csum_valid:1;
1226 __u8 ipmi_pkt:1;
1227 __u8 vlan_valid:1;
1228 __u8 fragment:1;
1229#else
1230 __u8 fragment:1;
1231 __u8 vlan_valid:1;
1232 __u8 ipmi_pkt:1;
1233 __u8 csum_valid:1;
1234 __u8 iff:4;
1235#endif
1236 __be16 csum;
1237 __be16 vlan;
1238 __be16 len;
1239};
1240
1241struct cpl_l2t_write_req {
1242 WR_HDR;
1243 union opcode_tid ot;
1244 __be32 params;
1245 __u8 rsvd[2];
1246 __u8 dst_mac[6];
1247};
1248
1249/* cpl_l2t_write_req.params fields */
1250#define S_L2T_W_IDX 0
1251#define M_L2T_W_IDX 0x7FF
1252#define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
1253#define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)
1254
1255#define S_L2T_W_VLAN 11
1256#define M_L2T_W_VLAN 0xFFF
1257#define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN)
1258#define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN)
1259
1260#define S_L2T_W_IFF 23
1261#define M_L2T_W_IFF 0xF
1262#define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF)
1263#define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF)
1264
1265#define S_L2T_W_PRIO 27
1266#define M_L2T_W_PRIO 0x7
1267#define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO)
1268#define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO)
1269
1270struct cpl_l2t_write_rpl {
1271 RSS_HDR
1272 union opcode_tid ot;
1273 __u8 status;
1274 __u8 rsvd[3];
1275};
1276
1277struct cpl_l2t_read_req {
1278 WR_HDR;
1279 union opcode_tid ot;
1280 __be16 rsvd;
1281 __be16 l2t_idx;
1282};
1283
1284struct cpl_l2t_read_rpl {
1285 RSS_HDR
1286 union opcode_tid ot;
1287 __be32 params;
1288 __u8 rsvd[2];
1289 __u8 dst_mac[6];
1290};
1291
1292/* cpl_l2t_read_rpl.params fields */
1293#define S_L2T_R_PRIO 0
1294#define M_L2T_R_PRIO 0x7
1295#define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO)
1296#define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO)
1297
1298#define S_L2T_R_VLAN 8
1299#define M_L2T_R_VLAN 0xFFF
1300#define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN)
1301#define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN)
1302
1303#define S_L2T_R_IFF 20
1304#define M_L2T_R_IFF 0xF
1305#define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF)
1306#define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF)
1307
1308#define S_L2T_STATUS 24
1309#define M_L2T_STATUS 0xFF
1310#define V_L2T_STATUS(x) ((x) << S_L2T_STATUS)
1311#define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS)
1312
1313struct cpl_smt_write_req {
1314 WR_HDR;
1315 union opcode_tid ot;
1316 __u8 rsvd0;
1317#if defined(__LITTLE_ENDIAN_BITFIELD)
1318 __u8 mtu_idx:4;
1319 __u8 iff:4;
1320#else
1321 __u8 iff:4;
1322 __u8 mtu_idx:4;
1323#endif
1324 __be16 rsvd2;
1325 __be16 rsvd3;
1326 __u8 src_mac1[6];
1327 __be16 rsvd4;
1328 __u8 src_mac0[6];
1329};
1330
1331struct cpl_smt_write_rpl {
1332 RSS_HDR
1333 union opcode_tid ot;
1334 __u8 status;
1335 __u8 rsvd[3];
1336};
1337
1338struct cpl_smt_read_req {
1339 WR_HDR;
1340 union opcode_tid ot;
1341 __u8 rsvd0;
1342#if defined(__LITTLE_ENDIAN_BITFIELD)
1343 __u8 :4;
1344 __u8 iff:4;
1345#else
1346 __u8 iff:4;
1347 __u8 :4;
1348#endif
1349 __be16 rsvd2;
1350};
1351
1352struct cpl_smt_read_rpl {
1353 RSS_HDR
1354 union opcode_tid ot;
1355 __u8 status;
1356#if defined(__LITTLE_ENDIAN_BITFIELD)
1357 __u8 mtu_idx:4;
1358 __u8 :4;
1359#else
1360 __u8 :4;
1361 __u8 mtu_idx:4;
1362#endif
1363 __be16 rsvd2;
1364 __be16 rsvd3;
1365 __u8 src_mac1[6];
1366 __be16 rsvd4;
1367 __u8 src_mac0[6];
1368};
1369
1370struct cpl_rte_delete_req {
1371 WR_HDR;
1372 union opcode_tid ot;
1373 __be32 params;
1374};
1375
1376/* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */
1377#define S_RTE_REQ_LUT_IX 8
1378#define M_RTE_REQ_LUT_IX 0x7FF
1379#define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1380#define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1381
1382#define S_RTE_REQ_LUT_BASE 19
1383#define M_RTE_REQ_LUT_BASE 0x7FF
1384#define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1385#define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1386
1387#define S_RTE_READ_REQ_SELECT 31
1388#define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1389#define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U)
1390
1391struct cpl_rte_delete_rpl {
1392 RSS_HDR
1393 union opcode_tid ot;
1394 __u8 status;
1395 __u8 rsvd[3];
1396};
1397
1398struct cpl_rte_write_req {
1399 WR_HDR;
1400 union opcode_tid ot;
1401#if defined(__LITTLE_ENDIAN_BITFIELD)
1402 __u8 :6;
1403 __u8 write_tcam:1;
1404 __u8 write_l2t_lut:1;
1405#else
1406 __u8 write_l2t_lut:1;
1407 __u8 write_tcam:1;
1408 __u8 :6;
1409#endif
1410 __u8 rsvd[3];
1411 __be32 lut_params;
1412 __be16 rsvd2;
1413 __be16 l2t_idx;
1414 __be32 netmask;
1415 __be32 faddr;
1416};
1417
1418/* cpl_rte_write_req.lut_params fields */
1419#define S_RTE_WRITE_REQ_LUT_IX 10
1420#define M_RTE_WRITE_REQ_LUT_IX 0x7FF
1421#define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX)
1422#define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX)
1423
1424#define S_RTE_WRITE_REQ_LUT_BASE 21
1425#define M_RTE_WRITE_REQ_LUT_BASE 0x7FF
1426#define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE)
1427#define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE)
1428
1429struct cpl_rte_write_rpl {
1430 RSS_HDR
1431 union opcode_tid ot;
1432 __u8 status;
1433 __u8 rsvd[3];
1434};
1435
1436struct cpl_rte_read_req {
1437 WR_HDR;
1438 union opcode_tid ot;
1439 __be32 params;
1440};
1441
1442struct cpl_rte_read_rpl {
1443 RSS_HDR
1444 union opcode_tid ot;
1445 __u8 status;
1446 __u8 rsvd0;
1447 __be16 l2t_idx;
1448#if defined(__LITTLE_ENDIAN_BITFIELD)
1449 __u8 :7;
1450 __u8 select:1;
1451#else
1452 __u8 select:1;
1453 __u8 :7;
1454#endif
1455 __u8 rsvd2[3];
1456 __be32 addr;
1457};
1458
1459struct cpl_tid_release {
1460 WR_HDR;
1461 union opcode_tid ot;
1462 __be32 rsvd;
1463};
1464
1465struct cpl_barrier {
1466 WR_HDR;
1467 __u8 opcode;
1468 __u8 rsvd[7];
1469};
1470
1471struct cpl_rdma_read_req {
1472 __u8 opcode;
1473 __u8 rsvd[15];
1474};
1475
1476struct cpl_rdma_terminate {
1477#ifdef CHELSIO_FW
1478 __u8 opcode;
1479 __u8 rsvd[2];
1480#if defined(__LITTLE_ENDIAN_BITFIELD)
1481 __u8 rspq:3;
1482 __u8 :5;
1483#else
1484 __u8 :5;
1485 __u8 rspq:3;
1486#endif
1487 __be32 tid_len;
1488#endif
1489 __be32 msn;
1490 __be32 mo;
1491 __u8 data[0];
1492};
1493
1494/* cpl_rdma_terminate.tid_len fields */
1495#define S_FLIT_CNT 0
1496#define M_FLIT_CNT 0xFF
1497#define V_FLIT_CNT(x) ((x) << S_FLIT_CNT)
1498#define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT)
1499
1500#define S_TERM_TID 8
1501#define M_TERM_TID 0xFFFFF
1502#define V_TERM_TID(x) ((x) << S_TERM_TID)
1503#define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
1504
1505/* ULP_TX opcodes */
1506enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 };
1507
1508#define S_ULPTX_CMD 28
1509#define M_ULPTX_CMD 0xF
1510#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
1511
1512#define S_ULPTX_NFLITS 0
1513#define M_ULPTX_NFLITS 0xFF
1514#define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
1515
1516struct ulp_mem_io {
1517 WR_HDR;
1518 __be32 cmd_lock_addr;
1519 __be32 len;
1520};
1521
1522 /* ulp_mem_io.cmd_lock_addr fields */
1523#define S_ULP_MEMIO_ADDR 0
1524#define M_ULP_MEMIO_ADDR 0x7FFFFFF
1525#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
1526
1527#define S_ULP_MEMIO_LOCK 27
1528#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
1529#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
1530
1531 /* ulp_mem_io.len fields */
1532#define S_ULP_MEMIO_DATA_LEN 28
1533#define M_ULP_MEMIO_DATA_LEN 0xF
1534#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
1535
1536struct ulp_txpkt {
1537 __be32 cmd_dest;
1538 __be32 len;
1539};
1540
1541 /* ulp_txpkt.cmd_dest fields */
1542#define S_ULP_TXPKT_DEST 24
1543#define M_ULP_TXPKT_DEST 0xF
1544#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
1545
1546#endif /* T3_CPL_H */
| 29
30***************************************************************************/
31#ifndef T3_CPL_H
32#define T3_CPL_H
33
34#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
35# include <asm/byteorder.h>
36#endif
37
38enum CPL_opcode {
39 CPL_PASS_OPEN_REQ = 0x1,
40 CPL_PASS_ACCEPT_RPL = 0x2,
41 CPL_ACT_OPEN_REQ = 0x3,
42 CPL_SET_TCB = 0x4,
43 CPL_SET_TCB_FIELD = 0x5,
44 CPL_GET_TCB = 0x6,
45 CPL_PCMD = 0x7,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
48 CPL_ABORT_REQ = 0xA,
49 CPL_ABORT_RPL = 0xB,
50 CPL_TX_DATA = 0xC,
51 CPL_RX_DATA_ACK = 0xD,
52 CPL_TX_PKT = 0xE,
53 CPL_RTE_DELETE_REQ = 0xF,
54 CPL_RTE_WRITE_REQ = 0x10,
55 CPL_RTE_READ_REQ = 0x11,
56 CPL_L2T_WRITE_REQ = 0x12,
57 CPL_L2T_READ_REQ = 0x13,
58 CPL_SMT_WRITE_REQ = 0x14,
59 CPL_SMT_READ_REQ = 0x15,
60 CPL_TX_PKT_LSO = 0x16,
61 CPL_PCMD_READ = 0x17,
62 CPL_BARRIER = 0x18,
63 CPL_TID_RELEASE = 0x1A,
64
65 CPL_CLOSE_LISTSRV_RPL = 0x20,
66 CPL_ERROR = 0x21,
67 CPL_GET_TCB_RPL = 0x22,
68 CPL_L2T_WRITE_RPL = 0x23,
69 CPL_PCMD_READ_RPL = 0x24,
70 CPL_PCMD_RPL = 0x25,
71 CPL_PEER_CLOSE = 0x26,
72 CPL_RTE_DELETE_RPL = 0x27,
73 CPL_RTE_WRITE_RPL = 0x28,
74 CPL_RX_DDP_COMPLETE = 0x29,
75 CPL_RX_PHYS_ADDR = 0x2A,
76 CPL_RX_PKT = 0x2B,
77 CPL_RX_URG_NOTIFY = 0x2C,
78 CPL_SET_TCB_RPL = 0x2D,
79 CPL_SMT_WRITE_RPL = 0x2E,
80 CPL_TX_DATA_ACK = 0x2F,
81
82 CPL_ABORT_REQ_RSS = 0x30,
83 CPL_ABORT_RPL_RSS = 0x31,
84 CPL_CLOSE_CON_RPL = 0x32,
85 CPL_ISCSI_HDR = 0x33,
86 CPL_L2T_READ_RPL = 0x34,
87 CPL_RDMA_CQE = 0x35,
88 CPL_RDMA_CQE_READ_RSP = 0x36,
89 CPL_RDMA_CQE_ERR = 0x37,
90 CPL_RTE_READ_RPL = 0x38,
91 CPL_RX_DATA = 0x39,
92
93 CPL_ACT_OPEN_RPL = 0x40,
94 CPL_PASS_OPEN_RPL = 0x41,
95 CPL_RX_DATA_DDP = 0x42,
96 CPL_SMT_READ_RPL = 0x43,
97
98 CPL_ACT_ESTABLISH = 0x50,
99 CPL_PASS_ESTABLISH = 0x51,
100
101 CPL_PASS_ACCEPT_REQ = 0x70,
102
103 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */
104
105 CPL_TX_DMA_ACK = 0xA0,
106 CPL_RDMA_READ_REQ = 0xA1,
107 CPL_RDMA_TERMINATE = 0xA2,
108 CPL_TRACE_PKT = 0xA3,
109 CPL_RDMA_EC_STATUS = 0xA5,
110
111 NUM_CPL_CMDS /* must be last and previous entries must be sorted */
112};
113
114enum CPL_error {
115 CPL_ERR_NONE = 0,
116 CPL_ERR_TCAM_PARITY = 1,
117 CPL_ERR_TCAM_FULL = 3,
118 CPL_ERR_CONN_RESET = 20,
119 CPL_ERR_CONN_EXIST = 22,
120 CPL_ERR_ARP_MISS = 23,
121 CPL_ERR_BAD_SYN = 24,
122 CPL_ERR_CONN_TIMEDOUT = 30,
123 CPL_ERR_XMIT_TIMEDOUT = 31,
124 CPL_ERR_PERSIST_TIMEDOUT = 32,
125 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
126 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
127 CPL_ERR_RTX_NEG_ADVICE = 35,
128 CPL_ERR_PERSIST_NEG_ADVICE = 36,
129 CPL_ERR_ABORT_FAILED = 42,
130 CPL_ERR_GENERAL = 99
131};
132
133enum {
134 CPL_CONN_POLICY_AUTO = 0,
135 CPL_CONN_POLICY_ASK = 1,
136 CPL_CONN_POLICY_DENY = 3
137};
138
139enum {
140 ULP_MODE_NONE = 0,
141 ULP_MODE_TCP_DDP = 1,
142 ULP_MODE_ISCSI = 2,
143 ULP_MODE_RDMA = 4,
144 ULP_MODE_TCPDDP = 5
145};
146
147enum {
148 ULP_CRC_HEADER = 1 << 0,
149 ULP_CRC_DATA = 1 << 1
150};
151
152enum {
153 CPL_PASS_OPEN_ACCEPT,
154 CPL_PASS_OPEN_REJECT
155};
156
157enum {
158 CPL_ABORT_SEND_RST = 0,
159 CPL_ABORT_NO_RST,
160 CPL_ABORT_POST_CLOSE_REQ = 2
161};
162
163enum { /* TX_PKT_LSO ethernet types */
164 CPL_ETH_II,
165 CPL_ETH_II_VLAN,
166 CPL_ETH_802_3,
167 CPL_ETH_802_3_VLAN
168};
169
170enum { /* TCP congestion control algorithms */
171 CONG_ALG_RENO,
172 CONG_ALG_TAHOE,
173 CONG_ALG_NEWRENO,
174 CONG_ALG_HIGHSPEED
175};
176
177enum { /* RSS hash type */
178 RSS_HASH_NONE = 0,
179 RSS_HASH_2_TUPLE = 1 << 0,
180 RSS_HASH_4_TUPLE = 1 << 1
181};
182
183union opcode_tid {
184 __be32 opcode_tid;
185 __u8 opcode;
186};
187
188#define S_OPCODE 24
189#define V_OPCODE(x) ((x) << S_OPCODE)
190#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
191#define G_TID(x) ((x) & 0xFFFFFF)
192
193#define S_HASHTYPE 22
194#define M_HASHTYPE 0x3
195#define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
196
197#define S_QNUM 0
198#define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF)
199
200/* tid is assumed to be 24-bits */
201#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
202
203#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
204
205/* extract the TID from a CPL command */
206#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
207
208struct tcp_options {
209 __be16 mss;
210 __u8 wsf;
211#if defined(__LITTLE_ENDIAN_BITFIELD)
212 __u8 :5;
213 __u8 ecn:1;
214 __u8 sack:1;
215 __u8 tstamp:1;
216#else
217 __u8 tstamp:1;
218 __u8 sack:1;
219 __u8 ecn:1;
220 __u8 :5;
221#endif
222};
223
224struct rss_header {
225 __u8 opcode;
226#if defined(__LITTLE_ENDIAN_BITFIELD)
227 __u8 cpu_idx:6;
228 __u8 hash_type:2;
229#else
230 __u8 hash_type:2;
231 __u8 cpu_idx:6;
232#endif
233 __be16 cq_idx;
234 __be32 rss_hash_val;
235};
236
237#ifndef CHELSIO_FW
238struct work_request_hdr {
239 __be32 wr_hi;
240 __be32 wr_lo;
241};
242
243/* wr_hi fields */
244#define S_WR_SGE_CREDITS 0
245#define M_WR_SGE_CREDITS 0xFF
246#define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS)
247#define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS)
248
249#define S_WR_SGLSFLT 8
250#define M_WR_SGLSFLT 0xFF
251#define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT)
252#define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT)
253
254#define S_WR_BCNTLFLT 16
255#define M_WR_BCNTLFLT 0xF
256#define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
257#define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
258
259/* Applicable to BYPASS WRs only: the uP will added a CPL_BARRIER before
260 * and after the BYPASS WR if the ATOMIC bit is set.
261 */
262#define S_WR_ATOMIC 16
263#define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC)
264#define F_WR_ATOMIC V_WR_ATOMIC(1U)
265
266/* Applicable to BYPASS WRs only: the uP will flush buffered non abort
267 * related WRs.
268 */
269#define S_WR_FLUSH 17
270#define V_WR_FLUSH(x) ((x) << S_WR_FLUSH)
271#define F_WR_FLUSH V_WR_FLUSH(1U)
272
273#define S_WR_DATATYPE 20
274#define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
275#define F_WR_DATATYPE V_WR_DATATYPE(1U)
276
277#define S_WR_COMPL 21
278#define V_WR_COMPL(x) ((x) << S_WR_COMPL)
279#define F_WR_COMPL V_WR_COMPL(1U)
280
281#define S_WR_EOP 22
282#define V_WR_EOP(x) ((x) << S_WR_EOP)
283#define F_WR_EOP V_WR_EOP(1U)
284
285#define S_WR_SOP 23
286#define V_WR_SOP(x) ((x) << S_WR_SOP)
287#define F_WR_SOP V_WR_SOP(1U)
288
289#define S_WR_OP 24
290#define M_WR_OP 0xFF
291#define V_WR_OP(x) ((x) << S_WR_OP)
292#define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
293
294/* wr_lo fields */
295#define S_WR_LEN 0
296#define M_WR_LEN 0xFF
297#define V_WR_LEN(x) ((x) << S_WR_LEN)
298#define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN)
299
300#define S_WR_TID 8
301#define M_WR_TID 0xFFFFF
302#define V_WR_TID(x) ((x) << S_WR_TID)
303#define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID)
304
305#define S_WR_CR_FLUSH 30
306#define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH)
307#define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U)
308
309#define S_WR_GEN 31
310#define V_WR_GEN(x) ((x) << S_WR_GEN)
311#define F_WR_GEN V_WR_GEN(1U)
312
313# define WR_HDR struct work_request_hdr wr
314# define RSS_HDR
315#else
316# define WR_HDR
317# define RSS_HDR struct rss_header rss_hdr;
318#endif
319
320/* option 0 lower-half fields */
321#define S_CPL_STATUS 0
322#define M_CPL_STATUS 0xFF
323#define V_CPL_STATUS(x) ((x) << S_CPL_STATUS)
324#define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS)
325
326#define S_INJECT_TIMER 6
327#define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
328#define F_INJECT_TIMER V_INJECT_TIMER(1U)
329
330#define S_NO_OFFLOAD 7
331#define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD)
332#define F_NO_OFFLOAD V_NO_OFFLOAD(1U)
333
334#define S_ULP_MODE 8
335#define M_ULP_MODE 0xF
336#define V_ULP_MODE(x) ((x) << S_ULP_MODE)
337#define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
338
339#define S_RCV_BUFSIZ 12
340#define M_RCV_BUFSIZ 0x3FFF
341#define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
342#define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
343
344#define S_TOS 26
345#define M_TOS 0x3F
346#define V_TOS(x) ((x) << S_TOS)
347#define G_TOS(x) (((x) >> S_TOS) & M_TOS)
348
349/* option 0 upper-half fields */
350#define S_DELACK 0
351#define V_DELACK(x) ((x) << S_DELACK)
352#define F_DELACK V_DELACK(1U)
353
354#define S_NO_CONG 1
355#define V_NO_CONG(x) ((x) << S_NO_CONG)
356#define F_NO_CONG V_NO_CONG(1U)
357
358#define S_SRC_MAC_SEL 2
359#define M_SRC_MAC_SEL 0x3
360#define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL)
361#define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL)
362
363#define S_L2T_IDX 4
364#define M_L2T_IDX 0x7FF
365#define V_L2T_IDX(x) ((x) << S_L2T_IDX)
366#define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
367
368#define S_TX_CHANNEL 15
369#define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL)
370#define F_TX_CHANNEL V_TX_CHANNEL(1U)
371
372#define S_TCAM_BYPASS 16
373#define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS)
374#define F_TCAM_BYPASS V_TCAM_BYPASS(1U)
375
376#define S_NAGLE 17
377#define V_NAGLE(x) ((x) << S_NAGLE)
378#define F_NAGLE V_NAGLE(1U)
379
380#define S_WND_SCALE 18
381#define M_WND_SCALE 0xF
382#define V_WND_SCALE(x) ((x) << S_WND_SCALE)
383#define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
384
385#define S_KEEP_ALIVE 22
386#define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE)
387#define F_KEEP_ALIVE V_KEEP_ALIVE(1U)
388
389#define S_MAX_RETRANS 23
390#define M_MAX_RETRANS 0xF
391#define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS)
392#define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS)
393
394#define S_MAX_RETRANS_OVERRIDE 27
395#define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE)
396#define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U)
397
398#define S_MSS_IDX 28
399#define M_MSS_IDX 0xF
400#define V_MSS_IDX(x) ((x) << S_MSS_IDX)
401#define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
402
403/* option 1 fields */
404#define S_RSS_ENABLE 0
405#define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE)
406#define F_RSS_ENABLE V_RSS_ENABLE(1U)
407
408#define S_RSS_MASK_LEN 1
409#define M_RSS_MASK_LEN 0x7
410#define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
411#define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
412
413#define S_CPU_IDX 4
414#define M_CPU_IDX 0x3F
415#define V_CPU_IDX(x) ((x) << S_CPU_IDX)
416#define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
417
418#define S_MAC_MATCH_VALID 18
419#define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
420#define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U)
421
422#define S_CONN_POLICY 19
423#define M_CONN_POLICY 0x3
424#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
425#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
426
427#define S_SYN_DEFENSE 21
428#define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
429#define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
430
431#define S_VLAN_PRI 22
432#define M_VLAN_PRI 0x3
433#define V_VLAN_PRI(x) ((x) << S_VLAN_PRI)
434#define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI)
435
436#define S_VLAN_PRI_VALID 24
437#define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID)
438#define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U)
439
440#define S_PKT_TYPE 25
441#define M_PKT_TYPE 0x3
442#define V_PKT_TYPE(x) ((x) << S_PKT_TYPE)
443#define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE)
444
445#define S_MAC_MATCH 27
446#define M_MAC_MATCH 0x1F
447#define V_MAC_MATCH(x) ((x) << S_MAC_MATCH)
448#define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH)
449
450/* option 2 fields */
451#define S_CPU_INDEX 0
452#define M_CPU_INDEX 0x7F
453#define V_CPU_INDEX(x) ((x) << S_CPU_INDEX)
454#define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX)
455
456#define S_CPU_INDEX_VALID 7
457#define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID)
458#define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U)
459
460#define S_RX_COALESCE 8
461#define M_RX_COALESCE 0x3
462#define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
463#define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
464
465#define S_RX_COALESCE_VALID 10
466#define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
467#define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U)
468
469#define S_CONG_CONTROL_FLAVOR 11
470#define M_CONG_CONTROL_FLAVOR 0x3
471#define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR)
472#define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR)
473
474#define S_PACING_FLAVOR 13
475#define M_PACING_FLAVOR 0x3
476#define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR)
477#define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR)
478
479#define S_FLAVORS_VALID 15
480#define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID)
481#define F_FLAVORS_VALID V_FLAVORS_VALID(1U)
482
483#define S_RX_FC_DISABLE 16
484#define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
485#define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U)
486
487#define S_RX_FC_VALID 17
488#define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
489#define F_RX_FC_VALID V_RX_FC_VALID(1U)
490
491struct cpl_pass_open_req {
492 WR_HDR;
493 union opcode_tid ot;
494 __be16 local_port;
495 __be16 peer_port;
496 __be32 local_ip;
497 __be32 peer_ip;
498 __be32 opt0h;
499 __be32 opt0l;
500 __be32 peer_netmask;
501 __be32 opt1;
502};
503
504struct cpl_pass_open_rpl {
505 RSS_HDR
506 union opcode_tid ot;
507 __be16 local_port;
508 __be16 peer_port;
509 __be32 local_ip;
510 __be32 peer_ip;
511 __u8 resvd[7];
512 __u8 status;
513};
514
515struct cpl_pass_establish {
516 RSS_HDR
517 union opcode_tid ot;
518 __be16 local_port;
519 __be16 peer_port;
520 __be32 local_ip;
521 __be32 peer_ip;
522 __be32 tos_tid;
523 __be16 l2t_idx;
524 __be16 tcp_opt;
525 __be32 snd_isn;
526 __be32 rcv_isn;
527};
528
529/* cpl_pass_establish.tos_tid fields */
530#define S_PASS_OPEN_TID 0
531#define M_PASS_OPEN_TID 0xFFFFFF
532#define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
533#define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
534
535#define S_PASS_OPEN_TOS 24
536#define M_PASS_OPEN_TOS 0xFF
537#define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
538#define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
539
540/* cpl_pass_establish.l2t_idx fields */
541#define S_L2T_IDX16 5
542#define M_L2T_IDX16 0x7FF
543#define V_L2T_IDX16(x) ((x) << S_L2T_IDX16)
544#define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16)
545
546/* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */
547#define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
548#define G_TCPOPT_SACK(x) (((x) >> 6) & 1)
549#define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
550#define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
551#define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
552
553struct cpl_pass_accept_req {
554 RSS_HDR
555 union opcode_tid ot;
556 __be16 local_port;
557 __be16 peer_port;
558 __be32 local_ip;
559 __be32 peer_ip;
560 __be32 tos_tid;
561 struct tcp_options tcp_options;
562 __u8 dst_mac[6];
563 __be16 vlan_tag;
564 __u8 src_mac[6];
565#if defined(__LITTLE_ENDIAN_BITFIELD)
566 __u8 :3;
567 __u8 addr_idx:3;
568 __u8 port_idx:1;
569 __u8 exact_match:1;
570#else
571 __u8 exact_match:1;
572 __u8 port_idx:1;
573 __u8 addr_idx:3;
574 __u8 :3;
575#endif
576 __u8 rsvd;
577 __be32 rcv_isn;
578 __be32 rsvd2;
579};
580
581struct cpl_pass_accept_rpl {
582 WR_HDR;
583 union opcode_tid ot;
584 __be32 opt2;
585 __be32 rsvd;
586 __be32 peer_ip;
587 __be32 opt0h;
588 __be32 opt0l_status;
589};
590
591struct cpl_act_open_req {
592 WR_HDR;
593 union opcode_tid ot;
594 __be16 local_port;
595 __be16 peer_port;
596 __be32 local_ip;
597 __be32 peer_ip;
598 __be32 opt0h;
599 __be32 opt0l;
600 __be32 params;
601 __be32 opt2;
602};
603
604/* cpl_act_open_req.params fields */
605#define S_AOPEN_VLAN_PRI 9
606#define M_AOPEN_VLAN_PRI 0x3
607#define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI)
608#define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI)
609
610#define S_AOPEN_VLAN_PRI_VALID 11
611#define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID)
612#define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U)
613
614#define S_AOPEN_PKT_TYPE 12
615#define M_AOPEN_PKT_TYPE 0x3
616#define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE)
617#define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE)
618
619#define S_AOPEN_MAC_MATCH 14
620#define M_AOPEN_MAC_MATCH 0x1F
621#define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH)
622#define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH)
623
624#define S_AOPEN_MAC_MATCH_VALID 19
625#define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID)
626#define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U)
627
628#define S_AOPEN_IFF_VLAN 20
629#define M_AOPEN_IFF_VLAN 0xFFF
630#define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN)
631#define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN)
632
633struct cpl_act_open_rpl {
634 RSS_HDR
635 union opcode_tid ot;
636 __be16 local_port;
637 __be16 peer_port;
638 __be32 local_ip;
639 __be32 peer_ip;
640 __be32 atid;
641 __u8 rsvd[3];
642 __u8 status;
643};
644
645struct cpl_act_establish {
646 RSS_HDR
647 union opcode_tid ot;
648 __be16 local_port;
649 __be16 peer_port;
650 __be32 local_ip;
651 __be32 peer_ip;
652 __be32 tos_tid;
653 __be16 l2t_idx;
654 __be16 tcp_opt;
655 __be32 snd_isn;
656 __be32 rcv_isn;
657};
658
659struct cpl_get_tcb {
660 WR_HDR;
661 union opcode_tid ot;
662 __be16 cpuno;
663 __be16 rsvd;
664};
665
666struct cpl_get_tcb_rpl {
667 RSS_HDR
668 union opcode_tid ot;
669 __u8 rsvd;
670 __u8 status;
671 __be16 len;
672};
673
674struct cpl_set_tcb {
675 WR_HDR;
676 union opcode_tid ot;
677 __u8 reply;
678 __u8 cpu_idx;
679 __be16 len;
680};
681
682/* cpl_set_tcb.reply fields */
683#define S_NO_REPLY 7
684#define V_NO_REPLY(x) ((x) << S_NO_REPLY)
685#define F_NO_REPLY V_NO_REPLY(1U)
686
687struct cpl_set_tcb_field {
688 WR_HDR;
689 union opcode_tid ot;
690 __u8 reply;
691 __u8 cpu_idx;
692 __be16 word;
693 __be64 mask;
694 __be64 val;
695};
696
697struct cpl_set_tcb_rpl {
698 RSS_HDR
699 union opcode_tid ot;
700 __u8 rsvd[3];
701 __u8 status;
702};
703
704struct cpl_pcmd {
705 WR_HDR;
706 union opcode_tid ot;
707 __u8 rsvd[3];
708#if defined(__LITTLE_ENDIAN_BITFIELD)
709 __u8 src:1;
710 __u8 bundle:1;
711 __u8 channel:1;
712 __u8 :5;
713#else
714 __u8 :5;
715 __u8 channel:1;
716 __u8 bundle:1;
717 __u8 src:1;
718#endif
719 __be32 pcmd_parm[2];
720};
721
722struct cpl_pcmd_reply {
723 RSS_HDR
724 union opcode_tid ot;
725 __u8 status;
726 __u8 rsvd;
727 __be16 len;
728};
729
730struct cpl_close_con_req {
731 WR_HDR;
732 union opcode_tid ot;
733 __be32 rsvd;
734};
735
736struct cpl_close_con_rpl {
737 RSS_HDR
738 union opcode_tid ot;
739 __u8 rsvd[3];
740 __u8 status;
741 __be32 snd_nxt;
742 __be32 rcv_nxt;
743};
744
745struct cpl_close_listserv_req {
746 WR_HDR;
747 union opcode_tid ot;
748 __u8 rsvd0;
749 __u8 cpu_idx;
750 __be16 rsvd1;
751};
752
753struct cpl_close_listserv_rpl {
754 RSS_HDR
755 union opcode_tid ot;
756 __u8 rsvd[3];
757 __u8 status;
758};
759
760struct cpl_abort_req_rss {
761 RSS_HDR
762 union opcode_tid ot;
763 __be32 rsvd0;
764 __u8 rsvd1;
765 __u8 status;
766 __u8 rsvd2[6];
767};
768
769struct cpl_abort_req {
770 WR_HDR;
771 union opcode_tid ot;
772 __be32 rsvd0;
773 __u8 rsvd1;
774 __u8 cmd;
775 __u8 rsvd2[6];
776};
777
778struct cpl_abort_rpl_rss {
779 RSS_HDR
780 union opcode_tid ot;
781 __be32 rsvd0;
782 __u8 rsvd1;
783 __u8 status;
784 __u8 rsvd2[6];
785};
786
787struct cpl_abort_rpl {
788 WR_HDR;
789 union opcode_tid ot;
790 __be32 rsvd0;
791 __u8 rsvd1;
792 __u8 cmd;
793 __u8 rsvd2[6];
794};
795
796struct cpl_peer_close {
797 RSS_HDR
798 union opcode_tid ot;
799 __be32 rcv_nxt;
800};
801
802struct tx_data_wr {
803 __be32 wr_hi;
804 __be32 wr_lo;
805 __be32 len;
806 __be32 flags;
807 __be32 sndseq;
808 __be32 param;
809};
810
811/* tx_data_wr.param fields */
812#define S_TX_PORT 0
813#define M_TX_PORT 0x7
814#define V_TX_PORT(x) ((x) << S_TX_PORT)
815#define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
816
817#define S_TX_MSS 4
818#define M_TX_MSS 0xF
819#define V_TX_MSS(x) ((x) << S_TX_MSS)
820#define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
821
822#define S_TX_QOS 8
823#define M_TX_QOS 0xFF
824#define V_TX_QOS(x) ((x) << S_TX_QOS)
825#define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
826
827#define S_TX_SNDBUF 16
828#define M_TX_SNDBUF 0xFFFF
829#define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
830#define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
831
832struct cpl_tx_data {
833 union opcode_tid ot;
834 __be32 len;
835 __be32 rsvd;
836 __be16 urg;
837 __be16 flags;
838};
839
840/* cpl_tx_data.flags fields */
841#define S_TX_ULP_SUBMODE 6
842#define M_TX_ULP_SUBMODE 0xF
843#define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
844#define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
845
846#define S_TX_ULP_MODE 10
847#define M_TX_ULP_MODE 0xF
848#define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
849#define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
850
851#define S_TX_SHOVE 14
852#define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
853#define F_TX_SHOVE V_TX_SHOVE(1U)
854
855#define S_TX_MORE 15
856#define V_TX_MORE(x) ((x) << S_TX_MORE)
857#define F_TX_MORE V_TX_MORE(1U)
858
859/* additional tx_data_wr.flags fields */
860#define S_TX_CPU_IDX 0
861#define M_TX_CPU_IDX 0x3F
862#define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
863#define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
864
865#define S_TX_URG 16
866#define V_TX_URG(x) ((x) << S_TX_URG)
867#define F_TX_URG V_TX_URG(1U)
868
869#define S_TX_CLOSE 17
870#define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
871#define F_TX_CLOSE V_TX_CLOSE(1U)
872
873#define S_TX_INIT 18
874#define V_TX_INIT(x) ((x) << S_TX_INIT)
875#define F_TX_INIT V_TX_INIT(1U)
876
877#define S_TX_IMM_ACK 19
878#define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
879#define F_TX_IMM_ACK V_TX_IMM_ACK(1U)
880
881#define S_TX_IMM_DMA 20
882#define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
883#define F_TX_IMM_DMA V_TX_IMM_DMA(1U)
884
885struct cpl_tx_data_ack {
886 RSS_HDR
887 union opcode_tid ot;
888 __be32 ack_seq;
889};
890
891struct cpl_wr_ack {
892 RSS_HDR
893 union opcode_tid ot;
894 __be16 credits;
895 __be16 rsvd;
896 __be32 snd_nxt;
897 __be32 snd_una;
898};
899
900struct cpl_rdma_ec_status {
901 RSS_HDR
902 union opcode_tid ot;
903 __u8 rsvd[3];
904 __u8 status;
905};
906
907struct mngt_pktsched_wr {
908 __be32 wr_hi;
909 __be32 wr_lo;
910 __u8 mngt_opcode;
911 __u8 rsvd[7];
912 __u8 sched;
913 __u8 idx;
914 __u8 min;
915 __u8 max;
916 __u8 binding;
917 __u8 rsvd1[3];
918};
919
920struct cpl_iscsi_hdr {
921 RSS_HDR
922 union opcode_tid ot;
923 __be16 pdu_len_ddp;
924 __be16 len;
925 __be32 seq;
926 __be16 urg;
927 __u8 rsvd;
928 __u8 status;
929};
930
931/* cpl_iscsi_hdr.pdu_len_ddp fields */
932#define S_ISCSI_PDU_LEN 0
933#define M_ISCSI_PDU_LEN 0x7FFF
934#define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
935#define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
936
937#define S_ISCSI_DDP 15
938#define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
939#define F_ISCSI_DDP V_ISCSI_DDP(1U)
940
941struct cpl_rx_data {
942 RSS_HDR
943 union opcode_tid ot;
944 __be16 rsvd;
945 __be16 len;
946 __be32 seq;
947 __be16 urg;
948#if defined(__LITTLE_ENDIAN_BITFIELD)
949 __u8 dack_mode:2;
950 __u8 psh:1;
951 __u8 heartbeat:1;
952 __u8 :4;
953#else
954 __u8 :4;
955 __u8 heartbeat:1;
956 __u8 psh:1;
957 __u8 dack_mode:2;
958#endif
959 __u8 status;
960};
961
962struct cpl_rx_data_ack {
963 WR_HDR;
964 union opcode_tid ot;
965 __be32 credit_dack;
966};
967
968/* cpl_rx_data_ack.ack_seq fields */
969#define S_RX_CREDITS 0
970#define M_RX_CREDITS 0x7FFFFFF
971#define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
972#define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
973
974#define S_RX_MODULATE 27
975#define V_RX_MODULATE(x) ((x) << S_RX_MODULATE)
976#define F_RX_MODULATE V_RX_MODULATE(1U)
977
978#define S_RX_FORCE_ACK 28
979#define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
980#define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U)
981
982#define S_RX_DACK_MODE 29
983#define M_RX_DACK_MODE 0x3
984#define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
985#define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
986
987#define S_RX_DACK_CHANGE 31
988#define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
989#define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
990
991struct cpl_rx_urg_notify {
992 RSS_HDR
993 union opcode_tid ot;
994 __be32 seq;
995};
996
997struct cpl_rx_ddp_complete {
998 RSS_HDR
999 union opcode_tid ot;
1000 __be32 ddp_report;
1001};
1002
1003struct cpl_rx_data_ddp {
1004 RSS_HDR
1005 union opcode_tid ot;
1006 __be16 urg;
1007 __be16 len;
1008 __be32 seq;
1009 union {
1010 __be32 nxt_seq;
1011 __be32 ddp_report;
1012 } __U;
1013 __be32 ulp_crc;
1014 __be32 ddpvld_status;
1015};
1016
1017/* cpl_rx_data_ddp.ddpvld_status fields */
1018#define S_DDP_STATUS 0
1019#define M_DDP_STATUS 0xFF
1020#define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
1021#define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS)
1022
1023#define S_DDP_VALID 15
1024#define M_DDP_VALID 0x1FFFF
1025#define V_DDP_VALID(x) ((x) << S_DDP_VALID)
1026#define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
1027
1028#define S_DDP_PPOD_MISMATCH 15
1029#define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1030#define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U)
1031
1032#define S_DDP_PDU 16
1033#define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1034#define F_DDP_PDU V_DDP_PDU(1U)
1035
1036#define S_DDP_LLIMIT_ERR 17
1037#define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1038#define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U)
1039
1040#define S_DDP_PPOD_PARITY_ERR 18
1041#define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1042#define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U)
1043
1044#define S_DDP_PADDING_ERR 19
1045#define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1046#define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U)
1047
1048#define S_DDP_HDRCRC_ERR 20
1049#define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1050#define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U)
1051
1052#define S_DDP_DATACRC_ERR 21
1053#define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1054#define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U)
1055
1056#define S_DDP_INVALID_TAG 22
1057#define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1058#define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U)
1059
1060#define S_DDP_ULIMIT_ERR 23
1061#define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1062#define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U)
1063
1064#define S_DDP_OFFSET_ERR 24
1065#define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1066#define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U)
1067
1068#define S_DDP_COLOR_ERR 25
1069#define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1070#define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U)
1071
1072#define S_DDP_TID_MISMATCH 26
1073#define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1074#define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U)
1075
1076#define S_DDP_INVALID_PPOD 27
1077#define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1078#define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U)
1079
1080#define S_DDP_ULP_MODE 28
1081#define M_DDP_ULP_MODE 0xF
1082#define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1083#define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1084
1085/* cpl_rx_data_ddp.ddp_report fields */
1086#define S_DDP_OFFSET 0
1087#define M_DDP_OFFSET 0x3FFFFF
1088#define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1089#define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1090
1091#define S_DDP_URG 24
1092#define V_DDP_URG(x) ((x) << S_DDP_URG)
1093#define F_DDP_URG V_DDP_URG(1U)
1094
1095#define S_DDP_PSH 25
1096#define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1097#define F_DDP_PSH V_DDP_PSH(1U)
1098
1099#define S_DDP_BUF_COMPLETE 26
1100#define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1101#define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U)
1102
1103#define S_DDP_BUF_TIMED_OUT 27
1104#define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1105#define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U)
1106
1107#define S_DDP_BUF_IDX 28
1108#define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1109#define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1110
1111struct cpl_tx_pkt {
1112 WR_HDR;
1113 __be32 cntrl;
1114 __be32 len;
1115};
1116
1117struct cpl_tx_pkt_lso {
1118 WR_HDR;
1119 __be32 cntrl;
1120 __be32 len;
1121
1122 __be32 rsvd;
1123 __be32 lso_info;
1124};
1125
1126/* cpl_tx_pkt*.cntrl fields */
1127#define S_TXPKT_VLAN 0
1128#define M_TXPKT_VLAN 0xFFFF
1129#define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN)
1130#define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1131
1132#define S_TXPKT_INTF 16
1133#define M_TXPKT_INTF 0xF
1134#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1135#define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1136
1137#define S_TXPKT_IPCSUM_DIS 20
1138#define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS)
1139#define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U)
1140
1141#define S_TXPKT_L4CSUM_DIS 21
1142#define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS)
1143#define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U)
1144
1145#define S_TXPKT_VLAN_VLD 22
1146#define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD)
1147#define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U)
1148
1149#define S_TXPKT_LOOPBACK 23
1150#define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1151#define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1152
1153#define S_TXPKT_OPCODE 24
1154#define M_TXPKT_OPCODE 0xFF
1155#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1156#define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1157
1158/* cpl_tx_pkt_lso.lso_info fields */
1159#define S_LSO_MSS 0
1160#define M_LSO_MSS 0x3FFF
1161#define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1162#define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1163
1164#define S_LSO_ETH_TYPE 14
1165#define M_LSO_ETH_TYPE 0x3
1166#define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE)
1167#define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE)
1168
1169#define S_LSO_TCPHDR_WORDS 16
1170#define M_LSO_TCPHDR_WORDS 0xF
1171#define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS)
1172#define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS)
1173
1174#define S_LSO_IPHDR_WORDS 20
1175#define M_LSO_IPHDR_WORDS 0xF
1176#define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS)
1177#define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS)
1178
1179#define S_LSO_IPV6 24
1180#define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1181#define F_LSO_IPV6 V_LSO_IPV6(1U)
1182
1183struct cpl_trace_pkt {
1184#ifdef CHELSIO_FW
1185 __u8 rss_opcode;
1186#if defined(__LITTLE_ENDIAN_BITFIELD)
1187 __u8 err:1;
1188 __u8 :7;
1189#else
1190 __u8 :7;
1191 __u8 err:1;
1192#endif
1193 __u8 rsvd0;
1194#if defined(__LITTLE_ENDIAN_BITFIELD)
1195 __u8 qid:4;
1196 __u8 :4;
1197#else
1198 __u8 :4;
1199 __u8 qid:4;
1200#endif
1201 __be32 tstamp;
1202#endif /* CHELSIO_FW */
1203
1204 __u8 opcode;
1205#if defined(__LITTLE_ENDIAN_BITFIELD)
1206 __u8 iff:4;
1207 __u8 :4;
1208#else
1209 __u8 :4;
1210 __u8 iff:4;
1211#endif
1212 __u8 rsvd[4];
1213 __be16 len;
1214};
1215
1216struct cpl_rx_pkt {
1217 RSS_HDR
1218 __u8 opcode;
1219#if defined(__LITTLE_ENDIAN_BITFIELD)
1220 __u8 iff:4;
1221 __u8 csum_valid:1;
1222 __u8 ipmi_pkt:1;
1223 __u8 vlan_valid:1;
1224 __u8 fragment:1;
1225#else
1226 __u8 fragment:1;
1227 __u8 vlan_valid:1;
1228 __u8 ipmi_pkt:1;
1229 __u8 csum_valid:1;
1230 __u8 iff:4;
1231#endif
1232 __be16 csum;
1233 __be16 vlan;
1234 __be16 len;
1235};
1236
1237struct cpl_l2t_write_req {
1238 WR_HDR;
1239 union opcode_tid ot;
1240 __be32 params;
1241 __u8 rsvd[2];
1242 __u8 dst_mac[6];
1243};
1244
1245/* cpl_l2t_write_req.params fields */
1246#define S_L2T_W_IDX 0
1247#define M_L2T_W_IDX 0x7FF
1248#define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
1249#define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)
1250
1251#define S_L2T_W_VLAN 11
1252#define M_L2T_W_VLAN 0xFFF
1253#define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN)
1254#define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN)
1255
1256#define S_L2T_W_IFF 23
1257#define M_L2T_W_IFF 0xF
1258#define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF)
1259#define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF)
1260
1261#define S_L2T_W_PRIO 27
1262#define M_L2T_W_PRIO 0x7
1263#define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO)
1264#define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO)
1265
1266struct cpl_l2t_write_rpl {
1267 RSS_HDR
1268 union opcode_tid ot;
1269 __u8 status;
1270 __u8 rsvd[3];
1271};
1272
1273struct cpl_l2t_read_req {
1274 WR_HDR;
1275 union opcode_tid ot;
1276 __be16 rsvd;
1277 __be16 l2t_idx;
1278};
1279
1280struct cpl_l2t_read_rpl {
1281 RSS_HDR
1282 union opcode_tid ot;
1283 __be32 params;
1284 __u8 rsvd[2];
1285 __u8 dst_mac[6];
1286};
1287
1288/* cpl_l2t_read_rpl.params fields */
1289#define S_L2T_R_PRIO 0
1290#define M_L2T_R_PRIO 0x7
1291#define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO)
1292#define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO)
1293
1294#define S_L2T_R_VLAN 8
1295#define M_L2T_R_VLAN 0xFFF
1296#define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN)
1297#define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN)
1298
1299#define S_L2T_R_IFF 20
1300#define M_L2T_R_IFF 0xF
1301#define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF)
1302#define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF)
1303
1304#define S_L2T_STATUS 24
1305#define M_L2T_STATUS 0xFF
1306#define V_L2T_STATUS(x) ((x) << S_L2T_STATUS)
1307#define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS)
1308
1309struct cpl_smt_write_req {
1310 WR_HDR;
1311 union opcode_tid ot;
1312 __u8 rsvd0;
1313#if defined(__LITTLE_ENDIAN_BITFIELD)
1314 __u8 mtu_idx:4;
1315 __u8 iff:4;
1316#else
1317 __u8 iff:4;
1318 __u8 mtu_idx:4;
1319#endif
1320 __be16 rsvd2;
1321 __be16 rsvd3;
1322 __u8 src_mac1[6];
1323 __be16 rsvd4;
1324 __u8 src_mac0[6];
1325};
1326
1327struct cpl_smt_write_rpl {
1328 RSS_HDR
1329 union opcode_tid ot;
1330 __u8 status;
1331 __u8 rsvd[3];
1332};
1333
1334struct cpl_smt_read_req {
1335 WR_HDR;
1336 union opcode_tid ot;
1337 __u8 rsvd0;
1338#if defined(__LITTLE_ENDIAN_BITFIELD)
1339 __u8 :4;
1340 __u8 iff:4;
1341#else
1342 __u8 iff:4;
1343 __u8 :4;
1344#endif
1345 __be16 rsvd2;
1346};
1347
1348struct cpl_smt_read_rpl {
1349 RSS_HDR
1350 union opcode_tid ot;
1351 __u8 status;
1352#if defined(__LITTLE_ENDIAN_BITFIELD)
1353 __u8 mtu_idx:4;
1354 __u8 :4;
1355#else
1356 __u8 :4;
1357 __u8 mtu_idx:4;
1358#endif
1359 __be16 rsvd2;
1360 __be16 rsvd3;
1361 __u8 src_mac1[6];
1362 __be16 rsvd4;
1363 __u8 src_mac0[6];
1364};
1365
1366struct cpl_rte_delete_req {
1367 WR_HDR;
1368 union opcode_tid ot;
1369 __be32 params;
1370};
1371
1372/* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */
1373#define S_RTE_REQ_LUT_IX 8
1374#define M_RTE_REQ_LUT_IX 0x7FF
1375#define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1376#define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1377
1378#define S_RTE_REQ_LUT_BASE 19
1379#define M_RTE_REQ_LUT_BASE 0x7FF
1380#define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1381#define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1382
1383#define S_RTE_READ_REQ_SELECT 31
1384#define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1385#define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U)
1386
1387struct cpl_rte_delete_rpl {
1388 RSS_HDR
1389 union opcode_tid ot;
1390 __u8 status;
1391 __u8 rsvd[3];
1392};
1393
1394struct cpl_rte_write_req {
1395 WR_HDR;
1396 union opcode_tid ot;
1397#if defined(__LITTLE_ENDIAN_BITFIELD)
1398 __u8 :6;
1399 __u8 write_tcam:1;
1400 __u8 write_l2t_lut:1;
1401#else
1402 __u8 write_l2t_lut:1;
1403 __u8 write_tcam:1;
1404 __u8 :6;
1405#endif
1406 __u8 rsvd[3];
1407 __be32 lut_params;
1408 __be16 rsvd2;
1409 __be16 l2t_idx;
1410 __be32 netmask;
1411 __be32 faddr;
1412};
1413
1414/* cpl_rte_write_req.lut_params fields */
1415#define S_RTE_WRITE_REQ_LUT_IX 10
1416#define M_RTE_WRITE_REQ_LUT_IX 0x7FF
1417#define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX)
1418#define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX)
1419
1420#define S_RTE_WRITE_REQ_LUT_BASE 21
1421#define M_RTE_WRITE_REQ_LUT_BASE 0x7FF
1422#define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE)
1423#define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE)
1424
1425struct cpl_rte_write_rpl {
1426 RSS_HDR
1427 union opcode_tid ot;
1428 __u8 status;
1429 __u8 rsvd[3];
1430};
1431
1432struct cpl_rte_read_req {
1433 WR_HDR;
1434 union opcode_tid ot;
1435 __be32 params;
1436};
1437
1438struct cpl_rte_read_rpl {
1439 RSS_HDR
1440 union opcode_tid ot;
1441 __u8 status;
1442 __u8 rsvd0;
1443 __be16 l2t_idx;
1444#if defined(__LITTLE_ENDIAN_BITFIELD)
1445 __u8 :7;
1446 __u8 select:1;
1447#else
1448 __u8 select:1;
1449 __u8 :7;
1450#endif
1451 __u8 rsvd2[3];
1452 __be32 addr;
1453};
1454
1455struct cpl_tid_release {
1456 WR_HDR;
1457 union opcode_tid ot;
1458 __be32 rsvd;
1459};
1460
1461struct cpl_barrier {
1462 WR_HDR;
1463 __u8 opcode;
1464 __u8 rsvd[7];
1465};
1466
1467struct cpl_rdma_read_req {
1468 __u8 opcode;
1469 __u8 rsvd[15];
1470};
1471
1472struct cpl_rdma_terminate {
1473#ifdef CHELSIO_FW
1474 __u8 opcode;
1475 __u8 rsvd[2];
1476#if defined(__LITTLE_ENDIAN_BITFIELD)
1477 __u8 rspq:3;
1478 __u8 :5;
1479#else
1480 __u8 :5;
1481 __u8 rspq:3;
1482#endif
1483 __be32 tid_len;
1484#endif
1485 __be32 msn;
1486 __be32 mo;
1487 __u8 data[0];
1488};
1489
1490/* cpl_rdma_terminate.tid_len fields */
1491#define S_FLIT_CNT 0
1492#define M_FLIT_CNT 0xFF
1493#define V_FLIT_CNT(x) ((x) << S_FLIT_CNT)
1494#define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT)
1495
1496#define S_TERM_TID 8
1497#define M_TERM_TID 0xFFFFF
1498#define V_TERM_TID(x) ((x) << S_TERM_TID)
1499#define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
1500
1501/* ULP_TX opcodes */
1502enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 };
1503
1504#define S_ULPTX_CMD 28
1505#define M_ULPTX_CMD 0xF
1506#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
1507
1508#define S_ULPTX_NFLITS 0
1509#define M_ULPTX_NFLITS 0xFF
1510#define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
1511
1512struct ulp_mem_io {
1513 WR_HDR;
1514 __be32 cmd_lock_addr;
1515 __be32 len;
1516};
1517
1518 /* ulp_mem_io.cmd_lock_addr fields */
1519#define S_ULP_MEMIO_ADDR 0
1520#define M_ULP_MEMIO_ADDR 0x7FFFFFF
1521#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
1522
1523#define S_ULP_MEMIO_LOCK 27
1524#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
1525#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
1526
1527 /* ulp_mem_io.len fields */
1528#define S_ULP_MEMIO_DATA_LEN 28
1529#define M_ULP_MEMIO_DATA_LEN 0xF
1530#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
1531
1532struct ulp_txpkt {
1533 __be32 cmd_dest;
1534 __be32 len;
1535};
1536
1537 /* ulp_txpkt.cmd_dest fields */
1538#define S_ULP_TXPKT_DEST 24
1539#define M_ULP_TXPKT_DEST 0xF
1540#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
1541
1542#endif /* T3_CPL_H */
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