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bktr_core.c (51694) bktr_core.c (52593)
1/* $FreeBSD: head/sys/dev/bktr/bktr_core.c 51694 1999-09-26 22:06:20Z roger $ */
1/* $FreeBSD: head/sys/dev/bktr/bktr_core.c 52593 1999-10-28 13:58:17Z roger $ */
2
3/*
4 * This is part of the Driver for Video Capture Cards (Frame grabbers)
5 * and TV Tuner cards using the Brooktree Bt848, Bt848A, Bt849A, Bt878, Bt879
6 * chipset.
7 * Copyright Roger Hardiman and Amancio Hasty.
8 *
9 * bktr_core : This deals with the Bt848/849/878/879 PCI Frame Grabber,

--- 1832 unchanged lines hidden (view full) ---

1842 }
1843 *(unsigned long *)arg = temp;
1844
1845 /* after every channel change, we must restart the MSP34xx */
1846 /* audio chip to reselect NICAM STEREO or MONO audio */
1847 if ( bktr->card.msp3400c )
1848 msp_autodetect( bktr );
1849
2
3/*
4 * This is part of the Driver for Video Capture Cards (Frame grabbers)
5 * and TV Tuner cards using the Brooktree Bt848, Bt848A, Bt849A, Bt878, Bt879
6 * chipset.
7 * Copyright Roger Hardiman and Amancio Hasty.
8 *
9 * bktr_core : This deals with the Bt848/849/878/879 PCI Frame Grabber,

--- 1832 unchanged lines hidden (view full) ---

1842 }
1843 *(unsigned long *)arg = temp;
1844
1845 /* after every channel change, we must restart the MSP34xx */
1846 /* audio chip to reselect NICAM STEREO or MONO audio */
1847 if ( bktr->card.msp3400c )
1848 msp_autodetect( bktr );
1849
1850 /* after every channel change, we must restart the DPL35xx */
1851 if ( bktr->card.dpl3518a )
1852 dpl_autodetect( bktr );
1853
1850 temp_mute( bktr, FALSE );
1851 break;
1852
1853 case TVTUNER_GETCHNL:
1854 *(unsigned long *)arg = bktr->tuner.channel;
1855 break;
1856
1857 case TVTUNER_SETTYPE:

--- 22 unchanged lines hidden (view full) ---

1880 }
1881 *(unsigned long *)arg = temp;
1882
1883 /* after every channel change, we must restart the MSP34xx */
1884 /* audio chip to reselect NICAM STEREO or MONO audio */
1885 if ( bktr->card.msp3400c )
1886 msp_autodetect( bktr );
1887
1854 temp_mute( bktr, FALSE );
1855 break;
1856
1857 case TVTUNER_GETCHNL:
1858 *(unsigned long *)arg = bktr->tuner.channel;
1859 break;
1860
1861 case TVTUNER_SETTYPE:

--- 22 unchanged lines hidden (view full) ---

1884 }
1885 *(unsigned long *)arg = temp;
1886
1887 /* after every channel change, we must restart the MSP34xx */
1888 /* audio chip to reselect NICAM STEREO or MONO audio */
1889 if ( bktr->card.msp3400c )
1890 msp_autodetect( bktr );
1891
1892 /* after every channel change, we must restart the DPL35xx */
1893 if ( bktr->card.dpl3518a )
1894 dpl_autodetect( bktr );
1895
1888 temp_mute( bktr, FALSE );
1889 break;
1890
1891 case TVTUNER_GETFREQ:
1892 *(unsigned long *)arg = bktr->tuner.frequency;
1893 break;
1894
1895 case TVTUNER_GETCHNLSET:

--- 1835 unchanged lines hidden (view full) ---

3731 if (smbus_readb(bktr->i2c_sc.smbus, addr, cmd, &result))
3732 return (-1);
3733
3734 return ((int)((unsigned char)result));
3735}
3736
3737#define IICBUS(bktr) ((bktr)->i2c_sc.iicbus)
3738
1896 temp_mute( bktr, FALSE );
1897 break;
1898
1899 case TVTUNER_GETFREQ:
1900 *(unsigned long *)arg = bktr->tuner.frequency;
1901 break;
1902
1903 case TVTUNER_GETCHNLSET:

--- 1835 unchanged lines hidden (view full) ---

3739 if (smbus_readb(bktr->i2c_sc.smbus, addr, cmd, &result))
3740 return (-1);
3741
3742 return ((int)((unsigned char)result));
3743}
3744
3745#define IICBUS(bktr) ((bktr)->i2c_sc.iicbus)
3746
3739/* The MSP34xx Audio chip require i2c bus writes of up to 5 bytes which the */
3740/* bt848 automated i2c bus controller cannot handle */
3747/* The MSP34xx and DPL35xx Audio chip require i2c bus writes of up */
3748/* to 5 bytes which the bt848 automated i2c bus controller cannot handle */
3741/* Therefore we need low level control of the i2c bus hardware */
3742
3749/* Therefore we need low level control of the i2c bus hardware */
3750
3743/* Write to the MSP registers */
3751/* Write to the MSP or DPL registers */
3744void
3752void
3745msp_write(bktr_ptr_t bktr, unsigned char dev, unsigned int addr, unsigned int data)
3753msp_dpl_write(bktr_ptr_t bktr, int i2c_addr, unsigned char dev, unsigned int addr, unsigned int data)
3746{
3747 unsigned char addr_l, addr_h, data_h, data_l ;
3748
3749 addr_h = (addr >>8) & 0xff;
3750 addr_l = addr & 0xff;
3751 data_h = (data >>8) & 0xff;
3752 data_l = data & 0xff;
3753
3754{
3755 unsigned char addr_l, addr_h, data_h, data_l ;
3756
3757 addr_h = (addr >>8) & 0xff;
3758 addr_l = addr & 0xff;
3759 data_h = (data >>8) & 0xff;
3760 data_l = data & 0xff;
3761
3754 iicbus_start(IICBUS(bktr), bktr->msp_addr, 0 /* no timeout? */);
3762 iicbus_start(IICBUS(bktr), i2c_addr, 0 /* no timeout? */);
3755
3756 iicbus_write_byte(IICBUS(bktr), dev, 0);
3757 iicbus_write_byte(IICBUS(bktr), addr_h, 0);
3758 iicbus_write_byte(IICBUS(bktr), addr_l, 0);
3759 iicbus_write_byte(IICBUS(bktr), data_h, 0);
3760 iicbus_write_byte(IICBUS(bktr), data_l, 0);
3761
3762 iicbus_stop(IICBUS(bktr));
3763
3764 return;
3765}
3766
3763
3764 iicbus_write_byte(IICBUS(bktr), dev, 0);
3765 iicbus_write_byte(IICBUS(bktr), addr_h, 0);
3766 iicbus_write_byte(IICBUS(bktr), addr_l, 0);
3767 iicbus_write_byte(IICBUS(bktr), data_h, 0);
3768 iicbus_write_byte(IICBUS(bktr), data_l, 0);
3769
3770 iicbus_stop(IICBUS(bktr));
3771
3772 return;
3773}
3774
3767/* Write to the MSP registers */
3775/* Read from the MSP or DPL registers */
3768unsigned int
3776unsigned int
3769msp_read(bktr_ptr_t bktr, unsigned char dev, unsigned int addr)
3777msp_dpl_read(bktr_ptr_t bktr, int i2c_addr, unsigned char dev, unsigned int addr)
3770{
3771 unsigned int data;
3772 unsigned char addr_l, addr_h, dev_r;
3773 int read;
3774 u_char data_read[2];
3775
3776 addr_h = (addr >>8) & 0xff;
3777 addr_l = addr & 0xff;
3778 dev_r = dev+1;
3779
3780 /* XXX errors ignored */
3778{
3779 unsigned int data;
3780 unsigned char addr_l, addr_h, dev_r;
3781 int read;
3782 u_char data_read[2];
3783
3784 addr_h = (addr >>8) & 0xff;
3785 addr_l = addr & 0xff;
3786 dev_r = dev+1;
3787
3788 /* XXX errors ignored */
3781 iicbus_start(IICBUS(bktr), bktr->msp_addr, 0 /* no timeout? */);
3789 iicbus_start(IICBUS(bktr), i2c_addr, 0 /* no timeout? */);
3782
3783 iicbus_write_byte(IICBUS(bktr), dev_r, 0);
3784 iicbus_write_byte(IICBUS(bktr), addr_h, 0);
3785 iicbus_write_byte(IICBUS(bktr), addr_l, 0);
3786
3790
3791 iicbus_write_byte(IICBUS(bktr), dev_r, 0);
3792 iicbus_write_byte(IICBUS(bktr), addr_h, 0);
3793 iicbus_write_byte(IICBUS(bktr), addr_l, 0);
3794
3787 iicbus_repeated_start(IICBUS(bktr), bktr->msp_addr +1, 0 /* no timeout? */);
3795 iicbus_repeated_start(IICBUS(bktr), i2c_addr +1, 0 /* no timeout? */);
3788 iicbus_read(IICBUS(bktr), data_read, 2, &read, IIC_LAST_READ, 0);
3789 iicbus_stop(IICBUS(bktr));
3790
3791 data = (data_read[0]<<8) | data_read[1];
3792
3793 return (data);
3794}
3795
3796 iicbus_read(IICBUS(bktr), data_read, 2, &read, IIC_LAST_READ, 0);
3797 iicbus_stop(IICBUS(bktr));
3798
3799 data = (data_read[0]<<8) | data_read[1];
3800
3801 return (data);
3802}
3803
3796/* Reset the MSP chip */
3804/* Reset the MSP or DPL chip */
3797/* The user can block the reset (which is handy if you initialise the
3805/* The user can block the reset (which is handy if you initialise the
3798 * MSP audio in another operating system first (eg in Windows)
3806 * MSP and/or DPL audio in another operating system first (eg in Windows)
3799 */
3800void
3807 */
3808void
3801msp_reset( bktr_ptr_t bktr )
3809msp_dpl_reset( bktr_ptr_t bktr, int i2c_addr )
3802{
3803
3804#ifndef BKTR_NO_MSP_RESET
3805 /* put into reset mode */
3810{
3811
3812#ifndef BKTR_NO_MSP_RESET
3813 /* put into reset mode */
3806 iicbus_start(IICBUS(bktr), bktr->msp_addr, 0 /* no timeout? */);
3814 iicbus_start(IICBUS(bktr), i2c_addr, 0 /* no timeout? */);
3807 iicbus_write_byte(IICBUS(bktr), 0x00, 0);
3808 iicbus_write_byte(IICBUS(bktr), 0x80, 0);
3809 iicbus_write_byte(IICBUS(bktr), 0x00, 0);
3810 iicbus_stop(IICBUS(bktr));
3811
3812 /* put back to operational mode */
3815 iicbus_write_byte(IICBUS(bktr), 0x00, 0);
3816 iicbus_write_byte(IICBUS(bktr), 0x80, 0);
3817 iicbus_write_byte(IICBUS(bktr), 0x00, 0);
3818 iicbus_stop(IICBUS(bktr));
3819
3820 /* put back to operational mode */
3813 iicbus_start(IICBUS(bktr), bktr->msp_addr, 0 /* no timeout? */);
3821 iicbus_start(IICBUS(bktr), i2c_addr, 0 /* no timeout? */);
3814 iicbus_write_byte(IICBUS(bktr), 0x00, 0);
3815 iicbus_write_byte(IICBUS(bktr), 0x00, 0);
3816 iicbus_write_byte(IICBUS(bktr), 0x00, 0);
3817 iicbus_stop(IICBUS(bktr));
3818#endif
3819 return;
3820}
3821

--- 192 unchanged lines hidden (view full) ---

4014 DELAY( BITD ); /* release clock */
4015 }
4016
4017 *data=byte;
4018 return 0;
4019}
4020#undef BITD
4021
3822 iicbus_write_byte(IICBUS(bktr), 0x00, 0);
3823 iicbus_write_byte(IICBUS(bktr), 0x00, 0);
3824 iicbus_write_byte(IICBUS(bktr), 0x00, 0);
3825 iicbus_stop(IICBUS(bktr));
3826#endif
3827 return;
3828}
3829

--- 192 unchanged lines hidden (view full) ---

4022 DELAY( BITD ); /* release clock */
4023 }
4024
4025 *data=byte;
4026 return 0;
4027}
4028#undef BITD
4029
4022/* Write to the MSP registers */
4023void msp_write( bktr_ptr_t bktr, unsigned char dev, unsigned int addr, unsigned int data){
4024 unsigned int msp_w_addr = bktr->msp_addr;
4030/* Write to the MSP or DPL registers */
4031void msp_dpl_write( bktr_ptr_t bktr, int i2c_addr, unsigned char dev, unsigned int addr,
4032 unsigned int data){
4033 unsigned int msp_w_addr = i2c_addr;
4025 unsigned char addr_l, addr_h, data_h, data_l ;
4026 addr_h = (addr >>8) & 0xff;
4027 addr_l = addr & 0xff;
4028 data_h = (data >>8) & 0xff;
4029 data_l = data & 0xff;
4030
4031 i2c_start(bktr);
4032 i2c_write_byte(bktr, msp_w_addr);
4033 i2c_write_byte(bktr, dev);
4034 i2c_write_byte(bktr, addr_h);
4035 i2c_write_byte(bktr, addr_l);
4036 i2c_write_byte(bktr, data_h);
4037 i2c_write_byte(bktr, data_l);
4038 i2c_stop(bktr);
4039}
4040
4034 unsigned char addr_l, addr_h, data_h, data_l ;
4035 addr_h = (addr >>8) & 0xff;
4036 addr_l = addr & 0xff;
4037 data_h = (data >>8) & 0xff;
4038 data_l = data & 0xff;
4039
4040 i2c_start(bktr);
4041 i2c_write_byte(bktr, msp_w_addr);
4042 i2c_write_byte(bktr, dev);
4043 i2c_write_byte(bktr, addr_h);
4044 i2c_write_byte(bktr, addr_l);
4045 i2c_write_byte(bktr, data_h);
4046 i2c_write_byte(bktr, data_l);
4047 i2c_stop(bktr);
4048}
4049
4041/* Write to the MSP registers */
4042unsigned int msp_read(bktr_ptr_t bktr, unsigned char dev, unsigned int addr){
4050/* Read from the MSP or DPL registers */
4051unsigned int msp_dpl_read(bktr_ptr_t bktr, int i2c_addr, unsigned char dev, unsigned int addr){
4043 unsigned int data;
4044 unsigned char addr_l, addr_h, data_1, data_2, dev_r ;
4045 addr_h = (addr >>8) & 0xff;
4046 addr_l = addr & 0xff;
4047 dev_r = dev+1;
4048
4049 i2c_start(bktr);
4052 unsigned int data;
4053 unsigned char addr_l, addr_h, data_1, data_2, dev_r ;
4054 addr_h = (addr >>8) & 0xff;
4055 addr_l = addr & 0xff;
4056 dev_r = dev+1;
4057
4058 i2c_start(bktr);
4050 i2c_write_byte(bktr,bktr->msp_addr);
4059 i2c_write_byte(bktr,i2c_addr);
4051 i2c_write_byte(bktr,dev_r);
4052 i2c_write_byte(bktr,addr_h);
4053 i2c_write_byte(bktr,addr_l);
4054
4055 i2c_start(bktr);
4060 i2c_write_byte(bktr,dev_r);
4061 i2c_write_byte(bktr,addr_h);
4062 i2c_write_byte(bktr,addr_l);
4063
4064 i2c_start(bktr);
4056 i2c_write_byte(bktr,bktr->msp_addr+1);
4065 i2c_write_byte(bktr,i2c_addr+1);
4057 i2c_read_byte(bktr,&data_1, 0);
4058 i2c_read_byte(bktr,&data_2, 1);
4059 i2c_stop(bktr);
4060 data = (data_1<<8) | data_2;
4061 return data;
4062}
4063
4066 i2c_read_byte(bktr,&data_1, 0);
4067 i2c_read_byte(bktr,&data_2, 1);
4068 i2c_stop(bktr);
4069 data = (data_1<<8) | data_2;
4070 return data;
4071}
4072
4064/* Reset the MSP chip */
4073/* Reset the MSP or DPL chip */
4065/* The user can block the reset (which is handy if you initialise the
4066 * MSP audio in another operating system first (eg in Windows)
4067 */
4074/* The user can block the reset (which is handy if you initialise the
4075 * MSP audio in another operating system first (eg in Windows)
4076 */
4068void msp_reset( bktr_ptr_t bktr ) {
4077void msp_dpl_reset( bktr_ptr_t bktr, int i2c_addr ) {
4069
4070#ifndef BKTR_NO_MSP_RESET
4071 /* put into reset mode */
4072 i2c_start(bktr);
4078
4079#ifndef BKTR_NO_MSP_RESET
4080 /* put into reset mode */
4081 i2c_start(bktr);
4073 i2c_write_byte(bktr, bktr->msp_addr);
4082 i2c_write_byte(bktr, i2c_addr);
4074 i2c_write_byte(bktr, 0x00);
4075 i2c_write_byte(bktr, 0x80);
4076 i2c_write_byte(bktr, 0x00);
4077 i2c_stop(bktr);
4078
4079 /* put back to operational mode */
4080 i2c_start(bktr);
4083 i2c_write_byte(bktr, 0x00);
4084 i2c_write_byte(bktr, 0x80);
4085 i2c_write_byte(bktr, 0x00);
4086 i2c_stop(bktr);
4087
4088 /* put back to operational mode */
4089 i2c_start(bktr);
4081 i2c_write_byte(bktr, bktr->msp_addr);
4090 i2c_write_byte(bktr, i2c_addr);
4082 i2c_write_byte(bktr, 0x00);
4083 i2c_write_byte(bktr, 0x00);
4084 i2c_write_byte(bktr, 0x00);
4085 i2c_stop(bktr);
4086#endif
4087 return;
4088
4089}

--- 93 unchanged lines hidden --- 		4091 i2c_write_byte(bktr, 0x00);
4092 i2c_write_byte(bktr, 0x00);
4093 i2c_write_byte(bktr, 0x00);
4094 i2c_stop(bktr);
4095#endif
4096 return;
4097
4098}

--- 93 unchanged lines hidden ---