| ar5416reg.h (188976) | ar5416reg.h (188979) |
|---|---|
| 1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * | 1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * |
| 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h 188976 2009-02-24 00:33:08Z sam $ | 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h 188979 2009-02-24 01:07:06Z sam $ |
| 18 */ 19#ifndef _DEV_ATH_AR5416REG_H 20#define _DEV_ATH_AR5416REG_H 21 22#include <dev/ath/ath_hal/ar5212/ar5212reg.h> 23 24/* 25 * Register added starting with the AR5416 26 */ 27#define AR_MIRT 0x0020 /* interrupt rate threshold */ 28#define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29#define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 30#define AR_GTXTO 0x0064 /* global transmit timeout */ 31#define AR_GTTM 0x0068 /* global transmit timeout mode */ 32#define AR_CST 0x006C /* carrier sense timeout */ 33#define AR_MAC_LED 0x1f04 /* LED control */ | 18 */ 19#ifndef _DEV_ATH_AR5416REG_H 20#define _DEV_ATH_AR5416REG_H 21 22#include <dev/ath/ath_hal/ar5212/ar5212reg.h> 23 24/* 25 * Register added starting with the AR5416 26 */ 27#define AR_MIRT 0x0020 /* interrupt rate threshold */ 28#define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29#define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 30#define AR_GTXTO 0x0064 /* global transmit timeout */ 31#define AR_GTTM 0x0068 /* global transmit timeout mode */ 32#define AR_CST 0x006C /* carrier sense timeout */ 33#define AR_MAC_LED 0x1f04 /* LED control */ |
| 34#define AR_WA 0x4004 /* PCIE work-arounds */ 35#define AR_PCIE_PM_CTRL 0x4014 |
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| 34#define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 35#define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 36#define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 37#define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 38#define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 39#define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 40#define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 41#define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ --- 138 unchanged lines hidden (view full) --- 180#define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 181#define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 182#define AR_MAC_LED_ASSOC 0x00000c00 183#define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ 184#define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ 185#define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */ 186#define AR_MAC_LED_ASSOC_S 10 187 | 36#define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 37#define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 38#define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 39#define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 40#define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 41#define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 42#define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 43#define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ --- 138 unchanged lines hidden (view full) --- 182#define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 183#define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 184#define AR_MAC_LED_ASSOC 0x00000c00 185#define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ 186#define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ 187#define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */ 188#define AR_MAC_LED_ASSOC_S 10 189 |
| 190#define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ 191#define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ 192#define AR_WA_ANALOG_SHIFT 0x00100000 193#define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ 194 195#define AR_WA_DEFAULT 0x0000073f 196#define AR9280_WA_DEFAULT 0x0040073f 197#define AR9285_WA_DEFAULT 0x004a05cb 198 199#define AR_PCIE_PM_CTRL_ENA 0x00080000 200 |
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| 188#define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 189#define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ 190#define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 191#define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ 192#define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ 193#define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 194#define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 195#define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ --- 348 unchanged lines hidden --- | 201#define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 202#define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ 203#define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 204#define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ 205#define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ 206#define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 207#define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 208#define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ --- 348 unchanged lines hidden --- |