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ata-dma.c (89917) ata-dma.c (90215)
1/*-
2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
1/*-
2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 89917 2002-01-28 13:17:10Z sos $
28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 90215 2002-02-04 19:23:40Z sos $
29 */
30
31#include "pci.h"
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/ata.h>
35#include <sys/bio.h>
36#include <sys/malloc.h>
37#include <sys/bus.h>
38#include <sys/disk.h>
39#include <sys/devicestat.h>
40#include <vm/vm.h>
41#include <vm/pmap.h>
42#include <pci/pcivar.h>
43#include <machine/bus.h>
44#include <sys/rman.h>
45#include <dev/ata/ata-all.h>
46
47/* prototypes */
29 */
30
31#include "pci.h"
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/ata.h>
35#include <sys/bio.h>
36#include <sys/malloc.h>
37#include <sys/bus.h>
38#include <sys/disk.h>
39#include <sys/devicestat.h>
40#include <vm/vm.h>
41#include <vm/pmap.h>
42#include <pci/pcivar.h>
43#include <machine/bus.h>
44#include <sys/rman.h>
45#include <dev/ata/ata-all.h>
46
47/* prototypes */
48static void cyrix_timing(struct ata_softc *, int, int);
49static void promise_timing(struct ata_softc *, int, int);
50static void hpt_timing(struct ata_softc *, int, int);
48static void cyrix_timing(struct ata_channel *, int, int);
49static void promise_timing(struct ata_channel *, int, int);
50static void hpt_timing(struct ata_channel *, int, int);
51
52/* misc defines */
53#ifdef __alpha__
54#undef vtophys
55#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
56#endif
51
52/* misc defines */
53#ifdef __alpha__
54#undef vtophys
55#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
56#endif
57#define ATAPI_DEVICE(scp, device) \
58 ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || \
59 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
57#define ATAPI_DEVICE(ch, device) \
58 ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || \
59 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE))
60
60
61
62void *
61void *
63ata_dmaalloc(struct ata_softc *scp, int device)
62ata_dmaalloc(struct ata_channel *ch, int device)
64{
65 void *dmatab;
66
67 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) {
68 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
69 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
63{
64 void *dmatab;
65
66 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) {
67 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
68 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
70 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n");
69 ata_printf(ch, device, "dmatab crosses page boundary, no DMA\n");
71 free(dmatab, M_DEVBUF);
72 dmatab = NULL;
73 }
74 }
75 return dmatab;
76}
77
78void
70 free(dmatab, M_DEVBUF);
71 dmatab = NULL;
72 }
73 }
74 return dmatab;
75}
76
77void
79ata_dmainit(struct ata_softc *scp, int device,
78ata_dmainit(struct ata_channel *ch, int device,
80 int apiomode, int wdmamode, int udmamode)
81{
79 int apiomode, int wdmamode, int udmamode)
80{
82 device_t parent = device_get_parent(scp->dev);
83 int devno = (scp->channel << 1) + ATA_DEV(device);
81 struct ata_device *atadev = &ch->device[ATA_DEV(device)];
82 device_t parent = device_get_parent(ch->dev);
83 int devno = (ch->unit << 1) + ATA_DEV(device);
84 int error;
85
86 /* set our most pessimistic default mode */
84 int error;
85
86 /* set our most pessimistic default mode */
87 scp->mode[ATA_DEV(device)] = ATA_PIO;
87 atadev->mode = ATA_PIO;
88
88
89 if (!scp->r_bmio)
89 if (!ch->r_bmio)
90 return;
91
92 /* if simplex controller, only allow DMA on primary channel */
90 return;
91
92 /* if simplex controller, only allow DMA on primary channel */
93 if (scp->channel == 1) {
94 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
95 ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) &
93 if (ch->unit == 1) {
94 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
95 ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
96 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
96 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
97 if (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
98 ata_printf(scp, device, "simplex device, DMA on primary only\n");
97 if (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
98 ata_prtdev(atadev, "simplex device, DMA on primary only\n");
99 return;
100 }
101 }
102
103 /* DMA engine address alignment is usually 1 word (2 bytes) */
99 return;
100 }
101 }
102
103 /* DMA engine address alignment is usually 1 word (2 bytes) */
104 scp->alignment = 0x1;
104 ch->alignment = 0x1;
105
106#if 1
105
106#if 1
107 if (udmamode > 2 && !ATA_PARAM(scp, device)->hwres_cblid) {
108 ata_printf(scp, device,
109 "DMA limited to UDMA33, non-ATA66 compliant cable\n");
107 if (udmamode > 2 && !ch->device[ATA_DEV(device)].param->hwres_cblid) {
108 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
110 udmamode = 2;
111 }
112#endif
109 udmamode = 2;
110 }
111#endif
113 switch (scp->chiptype) {
112 switch (ch->chiptype) {
114
115 case 0x248a8086: /* Intel ICH3 mobile */
116 case 0x248b8086: /* Intel ICH3 */
117 case 0x244a8086: /* Intel ICH2 mobile */
118 case 0x244b8086: /* Intel ICH2 */
119 if (udmamode >= 5) {
120 int32_t mask48, new48;
121 int16_t word54;
122
123 word54 = pci_read_config(parent, 0x54, 2);
124 if (word54 & (0x10 << devno)) {
113
114 case 0x248a8086: /* Intel ICH3 mobile */
115 case 0x248b8086: /* Intel ICH3 */
116 case 0x244a8086: /* Intel ICH2 mobile */
117 case 0x244b8086: /* Intel ICH2 */
118 if (udmamode >= 5) {
119 int32_t mask48, new48;
120 int16_t word54;
121
122 word54 = pci_read_config(parent, 0x54, 2);
123 if (word54 & (0x10 << devno)) {
125 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
126 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
127 if (bootverbose)
128 ata_printf(scp, device, "%s setting UDMA5 on Intel chip\n",
124 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
125 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
126 if (bootverbose)
127 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
129 (error) ? "failed" : "success");
130 if (!error) {
131 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
132 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
133 pci_write_config(parent, 0x48,
134 (pci_read_config(parent, 0x48, 4) &
135 ~mask48) | new48, 4);
128 (error) ? "failed" : "success");
129 if (!error) {
130 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
131 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
132 pci_write_config(parent, 0x48,
133 (pci_read_config(parent, 0x48, 4) &
134 ~mask48) | new48, 4);
136 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
137 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
135 pci_write_config(parent, 0x54, word54 | (0x1000<136 atadev->mode = ATA_UDMA5;
138 return;
139 }
140 }
141 }
142 /* make sure eventual ATA100 mode from the BIOS is disabled */
143 pci_write_config(parent, 0x54,
144 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
145 /* FALLTHROUGH */
146
137 return;
138 }
139 }
140 }
141 /* make sure eventual ATA100 mode from the BIOS is disabled */
142 pci_write_config(parent, 0x54,
143 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
144 /* FALLTHROUGH */
145
147 case 0x24118086: /* Intel ICH */
148 case 0x76018086: /* Intel ICH */
146 case 0x24118086: /* Intel ICH */
147 case 0x76018086: /* Intel ICH */
149 if (udmamode >= 4) {
150 int32_t mask48, new48;
151 int16_t word54;
152
153 word54 = pci_read_config(parent, 0x54, 2);
154 if (word54 & (0x10 << devno)) {
148 if (udmamode >= 4) {
149 int32_t mask48, new48;
150 int16_t word54;
151
152 word54 = pci_read_config(parent, 0x54, 2);
153 if (word54 & (0x10 << devno)) {
155 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
156 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY);
157 if (bootverbose)
158 ata_printf(scp, device, "%s setting UDMA4 on Intel chip\n",
154 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
155 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
156 if (bootverbose)
157 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
159 (error) ? "failed" : "success");
160 if (!error) {
161 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
162 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
163 pci_write_config(parent, 0x48,
164 (pci_read_config(parent, 0x48, 4) &
165 ~mask48) | new48, 4);
166 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
158 (error) ? "failed" : "success");
159 if (!error) {
160 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
161 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
162 pci_write_config(parent, 0x48,
163 (pci_read_config(parent, 0x48, 4) &
164 ~mask48) | new48, 4);
165 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
167 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
166 atadev->mode = ATA_UDMA4;
168 return;
169 }
170 }
167 return;
168 }
169 }
171 }
170 }
172 /* make sure eventual ATA66 mode from the BIOS is disabled */
173 pci_write_config(parent, 0x54,
174 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
175 /* FALLTHROUGH */
176
177 case 0x71118086: /* Intel PIIX4 */
178 case 0x84CA8086: /* Intel PIIX4 */
179 case 0x71998086: /* Intel PIIX4e */
180 case 0x24218086: /* Intel ICH0 */
181 if (udmamode >= 2) {
182 int32_t mask48, new48;
183
171 /* make sure eventual ATA66 mode from the BIOS is disabled */
172 pci_write_config(parent, 0x54,
173 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
174 /* FALLTHROUGH */
175
176 case 0x71118086: /* Intel PIIX4 */
177 case 0x84CA8086: /* Intel PIIX4 */
178 case 0x71998086: /* Intel PIIX4e */
179 case 0x24218086: /* Intel ICH0 */
180 if (udmamode >= 2) {
181 int32_t mask48, new48;
182
184 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
183 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
185 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
186 if (bootverbose)
184 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
185 if (bootverbose)
187 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n",
186 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
188 (error) ? "failed" : "success");
189 if (!error) {
190 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
191 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
192 pci_write_config(parent, 0x48,
193 (pci_read_config(parent, 0x48, 4) &
194 ~mask48) | new48, 4);
187 (error) ? "failed" : "success");
188 if (!error) {
189 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
190 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
191 pci_write_config(parent, 0x48,
192 (pci_read_config(parent, 0x48, 4) &
193 ~mask48) | new48, 4);
195 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
194 atadev->mode = ATA_UDMA2;
196 return;
197 }
198 }
199 /* make sure eventual ATA33 mode from the BIOS is disabled */
200 pci_write_config(parent, 0x48,
201 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
202 /* FALLTHROUGH */
203
204 case 0x70108086: /* Intel PIIX3 */
205 if (wdmamode >= 2 && apiomode >= 4) {
206 int32_t mask40, new40, mask44, new44;
207
208 /* if SITRE not set doit for both channels */
195 return;
196 }
197 }
198 /* make sure eventual ATA33 mode from the BIOS is disabled */
199 pci_write_config(parent, 0x48,
200 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
201 /* FALLTHROUGH */
202
203 case 0x70108086: /* Intel PIIX3 */
204 if (wdmamode >= 2 && apiomode >= 4) {
205 int32_t mask40, new40, mask44, new44;
206
207 /* if SITRE not set doit for both channels */
209 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) {
208 if (!((pci_read_config(parent,0x40,4)>>(ch->unit<<8))&0x4000)) {
210 new40 = pci_read_config(parent, 0x40, 4);
211 new44 = pci_read_config(parent, 0x44, 4);
212 if (!(new40 & 0x00004000)) {
213 new44 &= ~0x0000000f;
214 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
215 }
216 if (!(new40 & 0x40000000)) {
217 new44 &= ~0x000000f0;
218 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
219 }
220 new40 |= 0x40004000;
221 pci_write_config(parent, 0x40, new40, 4);
222 pci_write_config(parent, 0x44, new44, 4);
223 }
209 new40 = pci_read_config(parent, 0x40, 4);
210 new44 = pci_read_config(parent, 0x44, 4);
211 if (!(new40 & 0x00004000)) {
212 new44 &= ~0x0000000f;
213 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
214 }
215 if (!(new40 & 0x40000000)) {
216 new44 &= ~0x000000f0;
217 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
218 }
219 new40 |= 0x40004000;
220 pci_write_config(parent, 0x40, new40, 4);
221 pci_write_config(parent, 0x44, new44, 4);
222 }
224 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
223 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
225 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
226 if (bootverbose)
224 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
225 if (bootverbose)
227 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n",
226 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
228 (error) ? "failed" : "success");
229 if (!error) {
230 if (device == ATA_MASTER) {
231 mask40 = 0x0000330f;
232 new40 = 0x00002307;
233 mask44 = 0;
234 new44 = 0;
235 }
236 else {
237 mask40 = 0x000000f0;
238 new40 = 0x00000070;
239 mask44 = 0x0000000f;
240 new44 = 0x0000000b;
241 }
227 (error) ? "failed" : "success");
228 if (!error) {
229 if (device == ATA_MASTER) {
230 mask40 = 0x0000330f;
231 new40 = 0x00002307;
232 mask44 = 0;
233 new44 = 0;
234 }
235 else {
236 mask40 = 0x000000f0;
237 new40 = 0x00000070;
238 mask44 = 0x0000000f;
239 new44 = 0x0000000b;
240 }
242 if (scp->channel) {
241 if (ch->unit) {
243 mask40 <<= 16;
244 new40 <<= 16;
245 mask44 <<= 4;
246 new44 <<= 4;
247 }
248 pci_write_config(parent, 0x40,
249 (pci_read_config(parent, 0x40, 4) & ~mask40)|
242 mask40 <<= 16;
243 new40 <<= 16;
244 mask44 <<= 4;
245 new44 <<= 4;
246 }
247 pci_write_config(parent, 0x40,
248 (pci_read_config(parent, 0x40, 4) & ~mask40)|
250 new40, 4);
249 new40, 4);
251 pci_write_config(parent, 0x44,
252 (pci_read_config(parent, 0x44, 4) & ~mask44)|
250 pci_write_config(parent, 0x44,
251 (pci_read_config(parent, 0x44, 4) & ~mask44)|
253 new44, 4);
254 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
252 new44, 4);
253 atadev->mode = ATA_WDMA2;
255 return;
256 }
257 }
258 /* we could set PIO mode timings, but we assume the BIOS did that */
259 break;
260
261 case 0x12308086: /* Intel PIIX */
262 if (wdmamode >= 2 && apiomode >= 4) {
263 int32_t word40;
264
265 word40 = pci_read_config(parent, 0x40, 4);
254 return;
255 }
256 }
257 /* we could set PIO mode timings, but we assume the BIOS did that */
258 break;
259
260 case 0x12308086: /* Intel PIIX */
261 if (wdmamode >= 2 && apiomode >= 4) {
262 int32_t word40;
263
264 word40 = pci_read_config(parent, 0x40, 4);
266 word40 >>= scp->channel * 16;
265 word40 >>= ch->unit * 16;
267
268 /* Check for timing config usable for DMA on controller */
269 if (!((word40 & 0x3300) == 0x2300 &&
270 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
271 break;
272
266
267 /* Check for timing config usable for DMA on controller */
268 if (!((word40 & 0x3300) == 0x2300 &&
269 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
270 break;
271
273 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
272 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
274 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
275 if (bootverbose)
273 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
274 if (bootverbose)
276 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n",
275 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
277 (error) ? "failed" : "success");
278 if (!error) {
276 (error) ? "failed" : "success");
277 if (!error) {
279 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
278 atadev->mode = ATA_WDMA2;
280 return;
281 }
282 }
283 break;
284
285 case 0x522910b9: /* AcerLabs Aladdin IV/V */
286 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
287 if (pci_get_revid(parent) < 0xc2 &&
279 return;
280 }
281 }
282 break;
283
284 case 0x522910b9: /* AcerLabs Aladdin IV/V */
285 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
286 if (pci_get_revid(parent) < 0xc2 &&
288 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) {
289 ata_printf(scp, device,
290 "Aladdin: two atapi devices on this channel, no DMA\n");
287 ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
288 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
291 break;
292 }
293 if (udmamode >= 5 && pci_get_revid(parent) >= 0xc4) {
289 break;
290 }
291 if (udmamode >= 5 && pci_get_revid(parent) >= 0xc4) {
294 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
292 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
295 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
296 if (bootverbose)
293 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
294 if (bootverbose)
297 ata_printf(scp, device, "%s setting UDMA5 on Acer chip\n",
295 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
298 (error) ? "failed" : "success");
299 if (!error) {
300 int32_t word54 = pci_read_config(parent, 0x54, 4);
301
302 pci_write_config(parent, 0x4b,
303 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
304 word54 &= ~(0x000f000f << (devno << 2));
305 word54 |= (0x000f0005 << (devno << 2));
306 pci_write_config(parent, 0x54, word54, 4);
307 pci_write_config(parent, 0x53,
308 pci_read_config(parent, 0x53, 1) | 0x03, 1);
296 (error) ? "failed" : "success");
297 if (!error) {
298 int32_t word54 = pci_read_config(parent, 0x54, 4);
299
300 pci_write_config(parent, 0x4b,
301 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
302 word54 &= ~(0x000f000f << (devno << 2));
303 word54 |= (0x000f0005 << (devno << 2));
304 pci_write_config(parent, 0x54, word54, 4);
305 pci_write_config(parent, 0x53,
306 pci_read_config(parent, 0x53, 1) | 0x03, 1);
309 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
307 atadev->mode = ATA_UDMA5;
310 return;
311 }
312 }
313 if (udmamode >= 4 && pci_get_revid(parent) >= 0xc2) {
308 return;
309 }
310 }
311 if (udmamode >= 4 && pci_get_revid(parent) >= 0xc2) {
314 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
312 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
315 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
316 if (bootverbose)
313 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
314 if (bootverbose)
317 ata_printf(scp, device, "%s setting UDMA4 on Acer chip\n",
315 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
318 (error) ? "failed" : "success");
319 if (!error) {
320 int32_t word54 = pci_read_config(parent, 0x54, 4);
321
322 pci_write_config(parent, 0x4b,
323 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
324 word54 &= ~(0x000f000f << (devno << 2));
325 word54 |= (0x00080005 << (devno << 2));
326 pci_write_config(parent, 0x54, word54, 4);
327 pci_write_config(parent, 0x53,
328 pci_read_config(parent, 0x53, 1) | 0x03, 1);
316 (error) ? "failed" : "success");
317 if (!error) {
318 int32_t word54 = pci_read_config(parent, 0x54, 4);
319
320 pci_write_config(parent, 0x4b,
321 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
322 word54 &= ~(0x000f000f << (devno << 2));
323 word54 |= (0x00080005 << (devno << 2));
324 pci_write_config(parent, 0x54, word54, 4);
325 pci_write_config(parent, 0x53,
326 pci_read_config(parent, 0x53, 1) | 0x03, 1);
329 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
327 atadev->mode = ATA_UDMA4;
330 return;
331 }
332 }
333 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) {
328 return;
329 }
330 }
331 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) {
334 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
332 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
335 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
336 if (bootverbose)
333 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
334 if (bootverbose)
337 ata_printf(scp, device, "%s setting UDMA2 on Acer chip\n",
335 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
338 (error) ? "failed" : "success");
339 if (!error) {
340 int32_t word54 = pci_read_config(parent, 0x54, 4);
341
342 word54 &= ~(0x000f000f << (devno << 2));
343 word54 |= (0x000a0005 << (devno << 2));
344 pci_write_config(parent, 0x54, word54, 4);
345 pci_write_config(parent, 0x53,
346 pci_read_config(parent, 0x53, 1) | 0x03, 1);
336 (error) ? "failed" : "success");
337 if (!error) {
338 int32_t word54 = pci_read_config(parent, 0x54, 4);
339
340 word54 &= ~(0x000f000f << (devno << 2));
341 word54 |= (0x000a0005 << (devno << 2));
342 pci_write_config(parent, 0x54, word54, 4);
343 pci_write_config(parent, 0x53,
344 pci_read_config(parent, 0x53, 1) | 0x03, 1);
347 scp->flags |= ATA_ATAPI_DMA_RO;
348 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
345 ch->flags |= ATA_ATAPI_DMA_RO;
346 atadev->mode = ATA_UDMA2;
349 return;
350 }
351 }
352
353 /* make sure eventual UDMA mode from the BIOS is disabled */
354 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
355 ~(0x0008 << (devno << 2)), 2);
356
357 if (wdmamode >= 2 && apiomode >= 4) {
347 return;
348 }
349 }
350
351 /* make sure eventual UDMA mode from the BIOS is disabled */
352 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
353 ~(0x0008 << (devno << 2)), 2);
354
355 if (wdmamode >= 2 && apiomode >= 4) {
358 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
356 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
359 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
360 if (bootverbose)
357 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
358 if (bootverbose)
361 ata_printf(scp, device, "%s setting WDMA2 on Acer chip\n",
359 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
362 (error) ? "failed" : "success");
363 if (!error) {
364 pci_write_config(parent, 0x53,
365 pci_read_config(parent, 0x53, 1) | 0x03, 1);
360 (error) ? "failed" : "success");
361 if (!error) {
362 pci_write_config(parent, 0x53,
363 pci_read_config(parent, 0x53, 1) | 0x03, 1);
366 scp->flags |= ATA_ATAPI_DMA_RO;
367 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
364 ch->flags |= ATA_ATAPI_DMA_RO;
365 atadev->mode = ATA_WDMA2;
368 return;
369 }
370 }
371 pci_write_config(parent, 0x53,
372 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
373 /* we could set PIO mode timings, but we assume the BIOS did that */
374 break;
375
376 case 0x74111022: /* AMD 766 */
377 if (udmamode >= 5) {
366 return;
367 }
368 }
369 pci_write_config(parent, 0x53,
370 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
371 /* we could set PIO mode timings, but we assume the BIOS did that */
372 break;
373
374 case 0x74111022: /* AMD 766 */
375 if (udmamode >= 5) {
378 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
376 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
379 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
380 if (bootverbose)
377 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
378 if (bootverbose)
381 ata_printf(scp, device, "%s setting UDMA5 on AMD chip\n",
379 ata_prtdev(atadev, "%s setting UDMA5 on AMD chip\n",
382 (error) ? "failed" : "success");
383 if (!error) {
380 (error) ? "failed" : "success");
381 if (!error) {
384 pci_write_config(parent, 0x53 - devno, 0xc6, 1);
385 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
382 pci_write_config(parent, 0x53 - devno, 0xc6, 1);
383 atadev->mode = ATA_UDMA5;
386 return;
387 }
388 }
389 /* FALLTHROUGH */
390
391 case 0x74091022: /* AMD 756 */
392 if (udmamode >= 4) {
384 return;
385 }
386 }
387 /* FALLTHROUGH */
388
389 case 0x74091022: /* AMD 756 */
390 if (udmamode >= 4) {
393 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
391 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
394 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
395 if (bootverbose)
392 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
393 if (bootverbose)
396 ata_printf(scp, device, "%s setting UDMA4 on AMD chip\n",
394 ata_prtdev(atadev, "%s setting UDMA4 on AMD chip\n",
397 (error) ? "failed" : "success");
398 if (!error) {
395 (error) ? "failed" : "success");
396 if (!error) {
399 pci_write_config(parent, 0x53 - devno, 0xc5, 1);
400 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
397 pci_write_config(parent, 0x53 - devno, 0xc5, 1);
398 atadev->mode = ATA_UDMA4;
401 return;
402 }
403 }
404 goto via_82c586;
405
406 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 , 8231, 8233 */
407 {
408 int via_modes[4][7] = {

--- 28 unchanged lines hidden (view full) ---

437via_82c586:
438 udmamode = imin(udmamode, 2);
439 reg_val = via_modes[0];
440 }
441 else
442 udmamode = 0;
443
444 if (udmamode >= 6) {
399 return;
400 }
401 }
402 goto via_82c586;
403
404 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 , 8231, 8233 */
405 {
406 int via_modes[4][7] = {

--- 28 unchanged lines hidden (view full) ---

435via_82c586:
436 udmamode = imin(udmamode, 2);
437 reg_val = via_modes[0];
438 }
439 else
440 udmamode = 0;
441
442 if (udmamode >= 6) {
445 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
443 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
446 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
447 if (bootverbose)
444 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
445 if (bootverbose)
448 ata_printf(scp, device, "%s setting UDMA6 on VIA chip\n",
446 ata_prtdev(atadev, "%s setting UDMA6 on VIA chip\n",
449 (error) ? "failed" : "success");
450 if (!error) {
451 pci_write_config(parent, 0x53 - devno, reg_val[6], 1);
447 (error) ? "failed" : "success");
448 if (!error) {
449 pci_write_config(parent, 0x53 - devno, reg_val[6], 1);
452 scp->mode[ATA_DEV(device)] = ATA_UDMA6;
450 atadev->mode = ATA_UDMA6;
453 return;
454 }
455 }
456 if (udmamode >= 5) {
451 return;
452 }
453 }
454 if (udmamode >= 5) {
457 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
455 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
458 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
459 if (bootverbose)
456 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
457 if (bootverbose)
460 ata_printf(scp, device, "%s setting UDMA5 on VIA chip\n",
458 ata_prtdev(atadev, "%s setting UDMA5 on VIA chip\n",
461 (error) ? "failed" : "success");
462 if (!error) {
463 pci_write_config(parent, 0x53 - devno, reg_val[5], 1);
459 (error) ? "failed" : "success");
460 if (!error) {
461 pci_write_config(parent, 0x53 - devno, reg_val[5], 1);
464 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
462 atadev->mode = ATA_UDMA5;
465 return;
466 }
467 }
468 if (udmamode >= 4) {
463 return;
464 }
465 }
466 if (udmamode >= 4) {
469 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
467 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
470 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
471 if (bootverbose)
468 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
469 if (bootverbose)
472 ata_printf(scp, device, "%s setting UDMA4 on VIA chip\n",
470 ata_prtdev(atadev, "%s setting UDMA4 on VIA chip\n",
473 (error) ? "failed" : "success");
474 if (!error) {
475 pci_write_config(parent, 0x53 - devno, reg_val[4], 1);
471 (error) ? "failed" : "success");
472 if (!error) {
473 pci_write_config(parent, 0x53 - devno, reg_val[4], 1);
476 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
474 atadev->mode = ATA_UDMA4;
477 return;
478 }
479 }
480 if (udmamode >= 2) {
475 return;
476 }
477 }
478 if (udmamode >= 2) {
481 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
479 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
482 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
483 if (bootverbose)
480 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
481 if (bootverbose)
484 ata_printf(scp, device, "%s setting UDMA2 on VIA chip\n",
482 ata_prtdev(atadev, "%s setting UDMA2 on VIA chip\n",
485 (error) ? "failed" : "success");
486 if (!error) {
487 pci_write_config(parent, 0x53 - devno, reg_val[2], 1);
483 (error) ? "failed" : "success");
484 if (!error) {
485 pci_write_config(parent, 0x53 - devno, reg_val[2], 1);
488 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
486 atadev->mode = ATA_UDMA2;
489 return;
490 }
491 }
492
493 }
494 if (wdmamode >= 2 && apiomode >= 4) {
487 return;
488 }
489 }
490
491 }
492 if (wdmamode >= 2 && apiomode >= 4) {
495 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
493 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
496 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
497 if (bootverbose)
494 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
495 if (bootverbose)
498 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n",
496 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
499 (error) ? "failed" : "success",
497 (error) ? "failed" : "success",
500 (scp->chiptype == 0x74091022) ? "AMD" : "VIA");
498 (ch->chiptype == 0x74091022) ? "AMD" : "VIA");
501 if (!error) {
499 if (!error) {
502 pci_write_config(parent, 0x53 - devno, 0x0b, 1);
503 pci_write_config(parent, 0x4b - devno, 0x31, 1);
504 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
500 pci_write_config(parent, 0x53 - devno, 0x0b, 1);
501 pci_write_config(parent, 0x4b - devno, 0x31, 1);
502 atadev->mode = ATA_WDMA2;
505 return;
506 }
507 }
508 /* we could set PIO mode timings, but we assume the BIOS did that */
509 break;
510
511 case 0x55131039: /* SiS 5591 */
503 return;
504 }
505 }
506 /* we could set PIO mode timings, but we assume the BIOS did that */
507 break;
508
509 case 0x55131039: /* SiS 5591 */
512 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
513 ata_find_dev(parent, 0x06331039, 0x00) || /* SiS 633 */
514 ata_find_dev(parent, 0x06351039, 0x00) || /* SiS 635 */
515 ata_find_dev(parent, 0x06401039, 0x00) || /* SiS 640 */
516 ata_find_dev(parent, 0x06451039, 0x00) || /* SiS 645 */
517 ata_find_dev(parent, 0x06501039, 0x00) || /* SiS 650 */
518 ata_find_dev(parent, 0x07301039, 0x00) || /* SiS 730 */
519 ata_find_dev(parent, 0x07331039, 0x00) || /* SiS 733 */
520 ata_find_dev(parent, 0x07351039, 0x00) || /* SiS 735 */
521 ata_find_dev(parent, 0x07401039, 0x00) || /* SiS 740 */
522 ata_find_dev(parent, 0x07451039, 0x00) || /* SiS 745 */
523 ata_find_dev(parent, 0x07501039, 0x00)) { /* SiS 750 */
510 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
511 ata_find_dev(parent, 0x06331039, 0x00) || /* SiS 633 */
512 ata_find_dev(parent, 0x06351039, 0x00) || /* SiS 635 */
513 ata_find_dev(parent, 0x06401039, 0x00) || /* SiS 640 */
514 ata_find_dev(parent, 0x06451039, 0x00) || /* SiS 645 */
515 ata_find_dev(parent, 0x06501039, 0x00) || /* SiS 650 */
516 ata_find_dev(parent, 0x07301039, 0x00) || /* SiS 730 */
517 ata_find_dev(parent, 0x07331039, 0x00) || /* SiS 733 */
518 ata_find_dev(parent, 0x07351039, 0x00) || /* SiS 735 */
519 ata_find_dev(parent, 0x07401039, 0x00) || /* SiS 740 */
520 ata_find_dev(parent, 0x07451039, 0x00) || /* SiS 745 */
521 ata_find_dev(parent, 0x07501039, 0x00)) { /* SiS 750 */
524 int8_t reg = 0x40 + (devno << 1);
525 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
526
527 if (udmamode >= 5) {
522 int8_t reg = 0x40 + (devno << 1);
523 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
524
525 if (udmamode >= 5) {
528 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
526 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
529 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
530 if (bootverbose)
527 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
528 if (bootverbose)
531 ata_printf(scp, device, "%s setting UDMA5 on SiS chip\n",
529 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
532 (error) ? "failed" : "success");
533 if (!error) {
534 pci_write_config(parent, reg, val | 0x8000, 2);
530 (error) ? "failed" : "success");
531 if (!error) {
532 pci_write_config(parent, reg, val | 0x8000, 2);
535 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
533 atadev->mode = ATA_UDMA5;
536 return;
537 }
538 }
539 if (udmamode >= 4) {
534 return;
535 }
536 }
537 if (udmamode >= 4) {
540 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
538 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
541 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
542 if (bootverbose)
539 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
540 if (bootverbose)
543 ata_printf(scp, device, "%s setting UDMA4 on SiS chip\n",
541 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
544 (error) ? "failed" : "success");
545 if (!error) {
546 pci_write_config(parent, reg, val | 0x9000, 2);
542 (error) ? "failed" : "success");
543 if (!error) {
544 pci_write_config(parent, reg, val | 0x9000, 2);
547 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
545 atadev->mode = ATA_UDMA4;
548 return;
549 }
550 }
551 if (udmamode >= 2) {
546 return;
547 }
548 }
549 if (udmamode >= 2) {
552 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
550 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
553 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
554 if (bootverbose)
551 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
552 if (bootverbose)
555 ata_printf(scp, device, "%s setting UDMA2 on SiS chip\n",
553 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
556 (error) ? "failed" : "success");
557 if (!error) {
558 pci_write_config(parent, reg, val | 0xb000, 2);
554 (error) ? "failed" : "success");
555 if (!error) {
556 pci_write_config(parent, reg, val | 0xb000, 2);
559 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
557 atadev->mode = ATA_UDMA2;
560 return;
561 }
562 }
563 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
564 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
565 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
566 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
567 int8_t reg = 0x40 + (devno << 1);
568 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
569
570 if (udmamode >= 4) {
558 return;
559 }
560 }
561 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
562 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
563 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
564 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
565 int8_t reg = 0x40 + (devno << 1);
566 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
567
568 if (udmamode >= 4) {
571 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
569 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
572 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
573 if (bootverbose)
570 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
571 if (bootverbose)
574 ata_printf(scp, device, "%s setting UDMA4 on SiS chip\n",
572 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
575 (error) ? "failed" : "success");
576 if (!error) {
577 pci_write_config(parent, reg, val | 0x9000, 2);
573 (error) ? "failed" : "success");
574 if (!error) {
575 pci_write_config(parent, reg, val | 0x9000, 2);
578 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
576 atadev->mode = ATA_UDMA4;
579 return;
580 }
581 }
582 if (udmamode >= 2) {
577 return;
578 }
579 }
580 if (udmamode >= 2) {
583 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
581 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
584 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
585 if (bootverbose)
582 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
583 if (bootverbose)
586 ata_printf(scp, device, "%s setting UDMA2 on SiS chip\n",
584 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
587 (error) ? "failed" : "success");
588 if (!error) {
589 pci_write_config(parent, reg, val | 0xa000, 2);
585 (error) ? "failed" : "success");
586 if (!error) {
587 pci_write_config(parent, reg, val | 0xa000, 2);
590 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
588 atadev->mode = ATA_UDMA2;
591 return;
592 }
593 }
594 } else if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) {
589 return;
590 }
591 }
592 } else if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) {
595 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
593 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
596 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
597 if (bootverbose)
594 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
595 if (bootverbose)
598 ata_printf(scp, device, "%s setting UDMA2 on SiS chip\n",
596 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
599 (error) ? "failed" : "success");
600 if (!error) {
601 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
597 (error) ? "failed" : "success");
598 if (!error) {
599 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
602 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
600 atadev->mode = ATA_UDMA2;
603 return;
604 }
605 }
606 if (wdmamode >=2 && apiomode >= 4) {
601 return;
602 }
603 }
604 if (wdmamode >=2 && apiomode >= 4) {
607 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
605 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
608 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
609 if (bootverbose)
606 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
607 if (bootverbose)
610 ata_printf(scp, device, "%s setting WDMA2 on SiS chip\n",
608 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
611 (error) ? "failed" : "success");
612 if (!error) {
613 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
609 (error) ? "failed" : "success");
610 if (!error) {
611 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
614 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
612 atadev->mode = ATA_WDMA2;
615 return;
616 }
617 }
618 /* we could set PIO mode timings, but we assume the BIOS did that */
619 break;
620
621 case 0x06491095: /* CMD 649 ATA100 controller */
622 if (udmamode >= 5) {
623 u_int8_t umode;
624
613 return;
614 }
615 }
616 /* we could set PIO mode timings, but we assume the BIOS did that */
617 break;
618
619 case 0x06491095: /* CMD 649 ATA100 controller */
620 if (udmamode >= 5) {
621 u_int8_t umode;
622
625 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
623 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
626 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
627 if (bootverbose)
624 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
625 if (bootverbose)
628 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n",
626 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
629 (error) ? "failed" : "success");
630 if (!error) {
627 (error) ? "failed" : "success");
628 if (!error) {
631 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
629 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
632 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
633 umode |= (device == ATA_MASTER ? 0x05 : 0x0a);
630 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
631 umode |= (device == ATA_MASTER ? 0x05 : 0x0a);
634 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
635 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
632 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
633 atadev->mode = ATA_UDMA5;
636 return;
637 }
638 }
639 /* FALLTHROUGH */
640
641 case 0x06481095: /* CMD 648 ATA66 controller */
642 if (udmamode >= 4) {
643 u_int8_t umode;
644
634 return;
635 }
636 }
637 /* FALLTHROUGH */
638
639 case 0x06481095: /* CMD 648 ATA66 controller */
640 if (udmamode >= 4) {
641 u_int8_t umode;
642
645 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
643 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
646 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
647 if (bootverbose)
644 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
645 if (bootverbose)
648 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n",
646 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
649 (error) ? "failed" : "success");
650 if (!error) {
647 (error) ? "failed" : "success");
648 if (!error) {
651 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
649 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
652 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
653 umode |= (device == ATA_MASTER ? 0x15 : 0x4a);
650 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
651 umode |= (device == ATA_MASTER ? 0x15 : 0x4a);
654 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
655 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
652 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
653 atadev->mode = ATA_UDMA4;
656 return;
657 }
658 }
659 if (udmamode >= 2) {
660 u_int8_t umode;
661
654 return;
655 }
656 }
657 if (udmamode >= 2) {
658 u_int8_t umode;
659
662 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
660 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
663 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
664 if (bootverbose)
661 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
662 if (bootverbose)
665 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n",
663 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
666 (error) ? "failed" : "success");
667 if (!error) {
664 (error) ? "failed" : "success");
665 if (!error) {
668 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1);
666 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
669 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
670 umode |= (device == ATA_MASTER ? 0x11 : 0x42);
667 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
668 umode |= (device == ATA_MASTER ? 0x11 : 0x42);
671 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1);
672 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
669 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
670 atadev->mode = ATA_UDMA2;
673 return;
674 }
675 }
676 /* make sure eventual UDMA mode from the BIOS is disabled */
671 return;
672 }
673 }
674 /* make sure eventual UDMA mode from the BIOS is disabled */
677 pci_write_config(parent, scp->channel ? 0x7b : 0x73,
678 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)&
675 pci_write_config(parent, ch->unit ? 0x7b : 0x73,
676 pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1)&
679 ~(device == ATA_MASTER ? 0x35 : 0xca), 1);
680 /* FALLTHROUGH */
681
682 case 0x06461095: /* CMD 646 ATA controller */
683 if (wdmamode >= 2 && apiomode >= 4) {
677 ~(device == ATA_MASTER ? 0x35 : 0xca), 1);
678 /* FALLTHROUGH */
679
680 case 0x06461095: /* CMD 646 ATA controller */
681 if (wdmamode >= 2 && apiomode >= 4) {
684 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
682 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
685 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
686 if (bootverbose)
683 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
684 if (bootverbose)
687 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n",
685 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
688 error ? "failed" : "success");
689 if (!error) {
690 int32_t offset = (devno < 3) ? (devno << 1) : 7;
691
692 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
686 error ? "failed" : "success");
687 if (!error) {
688 int32_t offset = (devno < 3) ? (devno << 1) : 7;
689
690 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
693 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
691 atadev->mode = ATA_WDMA2;
694 return;
695 }
696 }
697 /* we could set PIO mode timings, but we assume the BIOS did that */
698 break;
699
700 case 0xc6931080: /* Cypress 82c693 ATA controller */
701 if (wdmamode >= 2 && apiomode >= 4) {
692 return;
693 }
694 }
695 /* we could set PIO mode timings, but we assume the BIOS did that */
696 break;
697
698 case 0xc6931080: /* Cypress 82c693 ATA controller */
699 if (wdmamode >= 2 && apiomode >= 4) {
702 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
700 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
703 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
704 if (bootverbose)
701 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
702 if (bootverbose)
705 ata_printf(scp, device, "%s setting WDMA2 on Cypress chip\n",
703 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
706 error ? "failed" : "success");
707 if (!error) {
704 error ? "failed" : "success");
705 if (!error) {
708 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2);
709 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
706 pci_write_config(ch->dev, ch->unit ? 0x4e:0x4c, 0x2020, 2);
707 atadev->mode = ATA_WDMA2;
710 return;
711 }
712 }
713 /* we could set PIO mode timings, but we assume the BIOS did that */
714 break;
715
716 case 0x01021078: /* Cyrix 5530 ATA33 controller */
708 return;
709 }
710 }
711 /* we could set PIO mode timings, but we assume the BIOS did that */
712 break;
713
714 case 0x01021078: /* Cyrix 5530 ATA33 controller */
717 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */
715 ch->alignment = 0xf; /* DMA engine requires 16 byte alignment */
718 if (udmamode >= 2) {
716 if (udmamode >= 2) {
719 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
717 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
720 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
721 if (bootverbose)
718 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
719 if (bootverbose)
722 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n",
720 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
723 (error) ? "failed" : "success");
724 if (!error) {
721 (error) ? "failed" : "success");
722 if (!error) {
725 cyrix_timing(scp, devno, ATA_UDMA2);
726 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
723 cyrix_timing(ch, devno, ATA_UDMA2);
724 atadev->mode = ATA_UDMA2;
727 return;
728 }
729 }
730 if (wdmamode >= 2 && apiomode >= 4) {
725 return;
726 }
727 }
728 if (wdmamode >= 2 && apiomode >= 4) {
731 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
729 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
732 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
733 if (bootverbose)
730 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
731 if (bootverbose)
734 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n",
732 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
735 (error) ? "failed" : "success");
736 if (!error) {
733 (error) ? "failed" : "success");
734 if (!error) {
737 cyrix_timing(scp, devno, ATA_WDMA2);
738 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
735 cyrix_timing(ch, devno, ATA_WDMA2);
736 atadev->mode = ATA_WDMA2;
739 return;
740 }
741 }
737 return;
738 }
739 }
742 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
740 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
743 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
744 ATA_WAIT_READY);
745 if (bootverbose)
741 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
742 ATA_WAIT_READY);
743 if (bootverbose)
746 ata_printf(scp, device, "%s setting %s on Cyrix chip\n",
744 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
747 (error) ? "failed" : "success",
748 ata_mode2str(ATA_PIO0 + apiomode));
745 (error) ? "failed" : "success",
746 ata_mode2str(ATA_PIO0 + apiomode));
749 cyrix_timing(scp, devno, ATA_PIO0 + apiomode);
750 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode;
747 cyrix_timing(ch, devno, ATA_PIO0 + apiomode);
748 atadev->mode = ATA_PIO0 + apiomode;
751 return;
752
753 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
754 if (udmamode >= 2) {
749 return;
750
751 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
752 if (udmamode >= 2) {
755 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
753 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
756 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
757 if (bootverbose)
754 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
755 if (bootverbose)
758 ata_printf(scp, device,
759 "%s setting UDMA2 on ServerWorks chip\n",
756 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
760 (error) ? "failed" : "success");
761 if (!error) {
762 u_int16_t reg56;
763
764 pci_write_config(parent, 0x54,
765 pci_read_config(parent, 0x54, 1) |
766 (0x01 << devno), 1);
767 reg56 = pci_read_config(parent, 0x56, 2);
768 reg56 &= ~(0xf << (devno * 4));
769 reg56 |= (0x2 << (devno * 4));
770 pci_write_config(parent, 0x56, reg56, 2);
757 (error) ? "failed" : "success");
758 if (!error) {
759 u_int16_t reg56;
760
761 pci_write_config(parent, 0x54,
762 pci_read_config(parent, 0x54, 1) |
763 (0x01 << devno), 1);
764 reg56 = pci_read_config(parent, 0x56, 2);
765 reg56 &= ~(0xf << (devno * 4));
766 reg56 |= (0x2 << (devno * 4));
767 pci_write_config(parent, 0x56, reg56, 2);
771 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
768 atadev->mode = ATA_UDMA2;
772 return;
773 }
774 }
775 if (wdmamode >= 2 && apiomode >= 4) {
769 return;
770 }
771 }
772 if (wdmamode >= 2 && apiomode >= 4) {
776 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
773 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
777 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
778 if (bootverbose)
774 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
775 if (bootverbose)
779 ata_printf(scp, device,
780 "%s setting WDMA2 on ServerWorks chip\n",
776 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
781 (error) ? "failed" : "success");
782 if (!error) {
777 (error) ? "failed" : "success");
778 if (!error) {
783 int offset = (scp->channel * 2) + (device == ATA_MASTER);
779 int offset = (ch->unit * 2) + (device == ATA_MASTER);
784 int word44 = pci_read_config(parent, 0x44, 4);
785
786 pci_write_config(parent, 0x54,
787 pci_read_config(parent, 0x54, 1) &
788 ~(0x01 << devno), 1);
789 word44 &= ~(0xff << (offset << 8));
790 word44 |= (0x20 << (offset << 8));
791 pci_write_config(parent, 0x44, 0x20, 4);
780 int word44 = pci_read_config(parent, 0x44, 4);
781
782 pci_write_config(parent, 0x54,
783 pci_read_config(parent, 0x54, 1) &
784 ~(0x01 << devno), 1);
785 word44 &= ~(0xff << (offset << 8));
786 word44 |= (0x20 << (offset << 8));
787 pci_write_config(parent, 0x44, 0x20, 4);
792 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
788 atadev->mode = ATA_WDMA2;
793 return;
794 }
795 }
796 /* we could set PIO mode timings, but we assume the BIOS did that */
797 break;
798
799 case 0x4d69105a: /* Promise TX2 ATA133 controllers */
789 return;
790 }
791 }
792 /* we could set PIO mode timings, but we assume the BIOS did that */
793 break;
794
795 case 0x4d69105a: /* Promise TX2 ATA133 controllers */
800 ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
801 if (udmamode >= 6 && !(ATA_INB(scp->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
802 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
796 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
797 if (udmamode >= 6 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
798 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
803 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
804 if (bootverbose)
799 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
800 if (bootverbose)
805 ata_printf(scp, device, "%s setting UDMA6 on Promise chip\n",
801 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
806 (error) ? "failed" : "success");
807 if (!error) {
802 (error) ? "failed" : "success");
803 if (!error) {
808 scp->mode[ATA_DEV(device)] = ATA_UDMA6;
804 atadev->mode = ATA_UDMA6;
809 return;
810 }
811 }
812 /* FALLTHROUGH */
813
814 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
815 case 0x6268105a: /* Promise TX2 ATA100 controllers */
805 return;
806 }
807 }
808 /* FALLTHROUGH */
809
810 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
811 case 0x6268105a: /* Promise TX2 ATA100 controllers */
816 ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
817 if (udmamode >= 5 && !(ATA_INB(scp->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
818 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
812 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
813 if (udmamode >= 5 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
814 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
819 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
820 if (bootverbose)
815 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
816 if (bootverbose)
821 ata_printf(scp, device, "%s setting UDMA5 on Promise chip\n",
817 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
822 (error) ? "failed" : "success");
823 if (!error) {
818 (error) ? "failed" : "success");
819 if (!error) {
824 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
820 atadev->mode = ATA_UDMA5;
825 return;
826 }
827 }
821 return;
822 }
823 }
828 ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
829 if (udmamode >= 4 && !(ATA_INB(scp->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
830 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
824 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
825 if (udmamode >= 4 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
826 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
831 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
832 if (bootverbose)
827 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
828 if (bootverbose)
833 ata_printf(scp, device, "%s setting UDMA4 on Promise chip\n",
829 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
834 (error) ? "failed" : "success");
835 if (!error) {
830 (error) ? "failed" : "success");
831 if (!error) {
836 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
832 atadev->mode = ATA_UDMA4;
837 return;
838 }
839 }
840 if (udmamode >= 2) {
833 return;
834 }
835 }
836 if (udmamode >= 2) {
841 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
837 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
842 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
843 if (bootverbose)
838 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
839 if (bootverbose)
844 ata_printf(scp, device, "%s setting %s on Promise chip\n",
845 (error) ? "failed" : "success", "UDMA2");
840 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
841 (error) ? "failed" : "success");
846 if (!error) {
842 if (!error) {
847 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
843 atadev->mode = ATA_UDMA2;
848 return;
849 }
850 }
851 if (wdmamode >= 2 && apiomode >= 4) {
844 return;
845 }
846 }
847 if (wdmamode >= 2 && apiomode >= 4) {
852 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
848 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
853 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
854 if (bootverbose)
849 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
850 if (bootverbose)
855 ata_printf(scp, device, "%s setting %s on Promise chip\n",
856 (error) ? "failed" : "success", "WDMA2");
851 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
852 (error) ? "failed" : "success");
857 if (!error) {
853 if (!error) {
858 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
854 atadev->mode = ATA_WDMA2;
859 return;
860 }
861 }
862 break;
863
864 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
865 case 0x0d30105a: /* Promise OEM ATA100 controllers */
855 return;
856 }
857 }
858 break;
859
860 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
861 case 0x0d30105a: /* Promise OEM ATA100 controllers */
866 if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 &&
867 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){
868 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
862 if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 &&
863 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){
864 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
869 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
870 if (bootverbose)
865 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
866 if (bootverbose)
871 ata_printf(scp, device, "%s setting UDMA5 on Promise chip\n",
867 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
872 (error) ? "failed" : "success");
873 if (!error) {
868 (error) ? "failed" : "success");
869 if (!error) {
874 promise_timing(scp, devno, ATA_UDMA5);
875 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
870 promise_timing(ch, devno, ATA_UDMA5);
871 atadev->mode = ATA_UDMA5;
876 return;
877 }
878 }
879 /* FALLTHROUGH */
880
881 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
872 return;
873 }
874 }
875 /* FALLTHROUGH */
876
877 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
882 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 &&
883 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){
884 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
878 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 &&
879 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){
880 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
885 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
886 if (bootverbose)
881 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
882 if (bootverbose)
887 ata_printf(scp, device, "%s setting UDMA4 on Promise chip\n",
883 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
888 (error) ? "failed" : "success");
889 if (!error) {
884 (error) ? "failed" : "success");
885 if (!error) {
890 promise_timing(scp, devno, ATA_UDMA4);
891 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
886 promise_timing(ch, devno, ATA_UDMA4);
887 atadev->mode = ATA_UDMA4;
892 return;
893 }
894 }
895 /* FALLTHROUGH */
896
897 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
888 return;
889 }
890 }
891 /* FALLTHROUGH */
892
893 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
898 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) {
899 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
894 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) {
895 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
900 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
901 if (bootverbose)
896 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
897 if (bootverbose)
902 ata_printf(scp, device, "%s setting UDMA2 on Promise chip\n",
898 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
903 (error) ? "failed" : "success");
904 if (!error) {
899 (error) ? "failed" : "success");
900 if (!error) {
905 promise_timing(scp, devno, ATA_UDMA2);
906 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
901 promise_timing(ch, devno, ATA_UDMA2);
902 atadev->mode = ATA_UDMA2;
907 return;
908 }
909 }
903 return;
904 }
905 }
910 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) {
911 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
906 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) {
907 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
912 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
913 if (bootverbose)
908 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
909 if (bootverbose)
914 ata_printf(scp, device, "%s setting WDMA2 on Promise chip\n",
910 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
915 (error) ? "failed" : "success");
916 if (!error) {
911 (error) ? "failed" : "success");
912 if (!error) {
917 promise_timing(scp, devno, ATA_WDMA2);
918 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
913 promise_timing(ch, devno, ATA_WDMA2);
914 atadev->mode = ATA_WDMA2;
919 return;
920 }
921 }
915 return;
916 }
917 }
922 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
918 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
923 ATA_PIO0 + apiomode,
924 ATA_C_F_SETXFER, ATA_WAIT_READY);
925 if (bootverbose)
919 ATA_PIO0 + apiomode,
920 ATA_C_F_SETXFER, ATA_WAIT_READY);
921 if (bootverbose)
926 ata_printf(scp, device, "%s setting PIO%d on Promise chip\n",
922 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
927 (error) ? "failed" : "success",
928 (apiomode >= 0) ? apiomode : 0);
923 (error) ? "failed" : "success",
924 (apiomode >= 0) ? apiomode : 0);
929 promise_timing(scp, devno, ATA_PIO0 + apiomode);
930 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode;
925 promise_timing(ch, devno, ATA_PIO0 + apiomode);
926 atadev->mode = ATA_PIO0 + apiomode;
931 return;
932
933 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
927 return;
928
929 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
934 if (!ATAPI_DEVICE(scp, device) &&
930 if (!ATAPI_DEVICE(ch, device) &&
935 udmamode >= 6 && pci_get_revid(parent) >= 0x05 &&
931 udmamode >= 6 && pci_get_revid(parent) >= 0x05 &&
936 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) {
937 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
932 !(pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01:0x02))) {
933 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
938 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
939 if (bootverbose)
934 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
935 if (bootverbose)
940 ata_printf(scp, device, "%s setting UDMA6 on HighPoint chip\n",
936 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
941 (error) ? "failed" : "success");
942 if (!error) {
937 (error) ? "failed" : "success");
938 if (!error) {
943 hpt_timing(scp, devno, ATA_UDMA6);
944 scp->mode[ATA_DEV(device)] = ATA_UDMA6;
939 hpt_timing(ch, devno, ATA_UDMA6);
940 atadev->mode = ATA_UDMA6;
945 return;
946 }
947 }
941 return;
942 }
943 }
948 if (!ATAPI_DEVICE(scp, device) &&
944 if (!ATAPI_DEVICE(ch, device) &&
949 udmamode >= 5 && pci_get_revid(parent) >= 0x03 &&
945 udmamode >= 5 && pci_get_revid(parent) >= 0x03 &&
950 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) {
951 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
946 !(pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01:0x02))) {
947 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
952 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
953 if (bootverbose)
948 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
949 if (bootverbose)
954 ata_printf(scp, device, "%s setting UDMA5 on HighPoint chip\n",
950 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
955 (error) ? "failed" : "success");
956 if (!error) {
951 (error) ? "failed" : "success");
952 if (!error) {
957 hpt_timing(scp, devno, ATA_UDMA5);
958 scp->mode[ATA_DEV(device)] = ATA_UDMA5;
953 hpt_timing(ch, devno, ATA_UDMA5);
954 atadev->mode = ATA_UDMA5;
959 return;
960 }
961 }
955 return;
956 }
957 }
962 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 &&
963 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) {
964 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
958 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 &&
959 !(pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01:0x02))) {
960 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
965 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
966 if (bootverbose)
961 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
962 if (bootverbose)
967 ata_printf(scp, device, "%s setting UDMA4 on HighPoint chip\n",
963 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
968 (error) ? "failed" : "success");
969 if (!error) {
964 (error) ? "failed" : "success");
965 if (!error) {
970 hpt_timing(scp, devno, ATA_UDMA4);
971 scp->mode[ATA_DEV(device)] = ATA_UDMA4;
966 hpt_timing(ch, devno, ATA_UDMA4);
967 atadev->mode = ATA_UDMA4;
972 return;
973 }
974 }
968 return;
969 }
970 }
975 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) {
976 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
971 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) {
972 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
977 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
978 if (bootverbose)
973 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
974 if (bootverbose)
979 ata_printf(scp, device, "%s setting UDMA2 on HighPoint chip\n",
975 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
980 (error) ? "failed" : "success");
981 if (!error) {
976 (error) ? "failed" : "success");
977 if (!error) {
982 hpt_timing(scp, devno, ATA_UDMA2);
983 scp->mode[ATA_DEV(device)] = ATA_UDMA2;
978 hpt_timing(ch, devno, ATA_UDMA2);
979 atadev->mode = ATA_UDMA2;
984 return;
985 }
986 }
980 return;
981 }
982 }
987 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) {
988 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
983 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) {
984 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
989 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
990 if (bootverbose)
985 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
986 if (bootverbose)
991 ata_printf(scp, device, "%s setting WDMA2 on HighPoint chip\n",
987 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
992 (error) ? "failed" : "success");
993 if (!error) {
988 (error) ? "failed" : "success");
989 if (!error) {
994 hpt_timing(scp, devno, ATA_WDMA2);
995 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
990 hpt_timing(ch, devno, ATA_WDMA2);
991 atadev->mode = ATA_WDMA2;
996 return;
997 }
998 }
992 return;
993 }
994 }
999 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
995 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1000 ATA_PIO0 + apiomode,
1001 ATA_C_F_SETXFER, ATA_WAIT_READY);
1002 if (bootverbose)
996 ATA_PIO0 + apiomode,
997 ATA_C_F_SETXFER, ATA_WAIT_READY);
998 if (bootverbose)
1003 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n",
999 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
1004 (error) ? "failed" : "success",
1005 (apiomode >= 0) ? apiomode : 0);
1000 (error) ? "failed" : "success",
1001 (apiomode >= 0) ? apiomode : 0);
1006 hpt_timing(scp, devno, ATA_PIO0 + apiomode);
1007 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode;
1002 hpt_timing(ch, devno, ATA_PIO0 + apiomode);
1003 atadev->mode = ATA_PIO0 + apiomode;
1008 return;
1009
1010 default: /* unknown controller chip */
1011 /* better not try generic DMA on ATAPI devices it almost never works */
1004 return;
1005
1006 default: /* unknown controller chip */
1007 /* better not try generic DMA on ATAPI devices it almost never works */
1012 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) ||
1013 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE))
1008 if ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
1009 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE))
1014 break;
1015
1016 /* if controller says its setup for DMA take the easy way out */
1017 /* the downside is we dont know what DMA mode we are in */
1018 if ((udmamode >= 0 || wdmamode > 1) &&
1010 break;
1011
1012 /* if controller says its setup for DMA take the easy way out */
1013 /* the downside is we dont know what DMA mode we are in */
1014 if ((udmamode >= 0 || wdmamode > 1) &&
1019 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) &
1015 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
1020 ((device==ATA_MASTER) ?
1021 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
1016 ((device==ATA_MASTER) ?
1017 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
1022 scp->mode[ATA_DEV(device)] = ATA_DMA;
1018 atadev->mode = ATA_DMA;
1023 return;
1024 }
1025
1026 /* well, we have no support for this, but try anyways */
1019 return;
1020 }
1021
1022 /* well, we have no support for this, but try anyways */
1027 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) {
1028 error = ata_command(scp, device, ATA_C_SETFEATURES, 0,
1023 if ((wdmamode >= 2 && apiomode >= 4) && ch->r_bmio) {
1024 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1029 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1030 if (bootverbose)
1025 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1026 if (bootverbose)
1031 ata_printf(scp, device, "%s setting WDMA2 on generic chip\n",
1027 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
1032 (error) ? "failed" : "success");
1033 if (!error) {
1028 (error) ? "failed" : "success");
1029 if (!error) {
1034 scp->mode[ATA_DEV(device)] = ATA_WDMA2;
1030 atadev->mode = ATA_WDMA2;
1035 return;
1036 }
1037 }
1038 }
1031 return;
1032 }
1033 }
1034 }
1039 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1035 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1040 ATA_C_F_SETXFER,ATA_WAIT_READY);
1041 if (bootverbose)
1036 ATA_C_F_SETXFER,ATA_WAIT_READY);
1037 if (bootverbose)
1042 ata_printf(scp, device, "%s setting PIO%d on generic chip\n",
1038 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
1043 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1044 if (!error)
1039 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1040 if (!error)
1045 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode;
1041 atadev->mode = ATA_PIO0 + apiomode;
1046 else {
1047 if (bootverbose)
1042 else {
1043 if (bootverbose)
1048 ata_printf(scp, device, "using PIO mode set by BIOS\n");
1049 scp->mode[ATA_DEV(device)] = ATA_PIO;
1044 ata_prtdev(atadev, "using PIO mode set by BIOS\n");
1045 atadev->mode = ATA_PIO;
1050 }
1051}
1052
1053int
1046 }
1047}
1048
1049int
1054ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab,
1050ata_dmasetup(struct ata_channel *ch, int device, struct ata_dmaentry *dmatab,
1055 caddr_t data, int32_t count)
1056{
1057 u_int32_t dma_count, dma_base;
1058 int i = 0;
1059
1051 caddr_t data, int32_t count)
1052{
1053 u_int32_t dma_count, dma_base;
1054 int i = 0;
1055
1060 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) {
1061 ata_printf(scp, device, "non aligned DMA transfer attempted\n");
1056 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
1057 ata_printf(ch, device, "non aligned DMA transfer attempted\n");
1062 return -1;
1063 }
1064
1065 if (!count) {
1058 return -1;
1059 }
1060
1061 if (!count) {
1066 ata_printf(scp, device, "zero length DMA transfer attempted\n");
1062 ata_printf(ch, device, "zero length DMA transfer attempted\n");
1067 return -1;
1068 }
1069
1070 dma_base = vtophys(data);
1071 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1072 data += dma_count;
1073 count -= dma_count;
1074
1075 while (count) {
1076 dmatab[i].base = dma_base;
1077 dmatab[i].count = (dma_count & 0xffff);
1078 i++;
1079 if (i >= ATA_DMA_ENTRIES) {
1063 return -1;
1064 }
1065
1066 dma_base = vtophys(data);
1067 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1068 data += dma_count;
1069 count -= dma_count;
1070
1071 while (count) {
1072 dmatab[i].base = dma_base;
1073 dmatab[i].count = (dma_count & 0xffff);
1074 i++;
1075 if (i >= ATA_DMA_ENTRIES) {
1080 ata_printf(scp, device, "too many segments in DMA table\n");
1076 ata_printf(ch, device, "too many segments in DMA table\n");
1081 return -1;
1082 }
1083 dma_base = vtophys(data);
1084 dma_count = imin(count, PAGE_SIZE);
1085 data += imin(count, PAGE_SIZE);
1086 count -= imin(count, PAGE_SIZE);
1087 }
1088 dmatab[i].base = dma_base;
1089 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1090 return 0;
1091}
1092
1093void
1077 return -1;
1078 }
1079 dma_base = vtophys(data);
1080 dma_count = imin(count, PAGE_SIZE);
1081 data += imin(count, PAGE_SIZE);
1082 count -= imin(count, PAGE_SIZE);
1083 }
1084 dmatab[i].base = dma_base;
1085 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1086 return 0;
1087}
1088
1089void
1094ata_dmastart(struct ata_softc *scp, int device,
1090ata_dmastart(struct ata_channel *ch, int device,
1095 struct ata_dmaentry *dmatab, int dir)
1096{
1091 struct ata_dmaentry *dmatab, int dir)
1092{
1097 scp->flags |= ATA_DMA_ACTIVE;
1098 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab));
1099 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1100 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
1101 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) |
1093 ch->flags |= ATA_DMA_ACTIVE;
1094 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab));
1095 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1096 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1097 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1102 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1098 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1103 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT,
1104 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1099 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1100 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1105}
1106
1107int
1101}
1102
1103int
1108ata_dmadone(struct ata_softc *scp)
1104ata_dmadone(struct ata_channel *ch)
1109{
1110 int error;
1111
1105{
1106 int error;
1107
1112 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT,
1113 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1114 scp->flags &= ~ATA_DMA_ACTIVE;
1115 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT);
1116 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT,
1108 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1109 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1110 ch->flags &= ~ATA_DMA_ACTIVE;
1111 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1112 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1117 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1118 return error & ATA_BMSTAT_MASK;
1119}
1120
1121int
1113 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1114 return error & ATA_BMSTAT_MASK;
1115}
1116
1117int
1122ata_dmastatus(struct ata_softc *scp)
1118ata_dmastatus(struct ata_channel *ch)
1123{
1119{
1124 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1120 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1125}
1126
1127static void
1121}
1122
1123static void
1128cyrix_timing(struct ata_softc *scp, int devno, int mode)
1124cyrix_timing(struct ata_channel *ch, int devno, int mode)
1129{
1130 u_int32_t reg20 = 0x0000e132;
1131 u_int32_t reg24 = 0x00017771;
1132
1133 switch (mode) {
1134 case ATA_PIO0: reg20 = 0x0000e132; break;
1135 case ATA_PIO1: reg20 = 0x00018121; break;
1136 case ATA_PIO2: reg20 = 0x00024020; break;
1137 case ATA_PIO3: reg20 = 0x00032010; break;
1138 case ATA_PIO4: reg20 = 0x00040010; break;
1139 case ATA_WDMA2: reg24 = 0x00002020; break;
1140 case ATA_UDMA2: reg24 = 0x00911030; break;
1141 }
1125{
1126 u_int32_t reg20 = 0x0000e132;
1127 u_int32_t reg24 = 0x00017771;
1128
1129 switch (mode) {
1130 case ATA_PIO0: reg20 = 0x0000e132; break;
1131 case ATA_PIO1: reg20 = 0x00018121; break;
1132 case ATA_PIO2: reg20 = 0x00024020; break;
1133 case ATA_PIO3: reg20 = 0x00032010; break;
1134 case ATA_PIO4: reg20 = 0x00040010; break;
1135 case ATA_WDMA2: reg24 = 0x00002020; break;
1136 case ATA_UDMA2: reg24 = 0x00911030; break;
1137 }
1142 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20);
1143 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24);
1138 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x20, reg20);
1139 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x24, reg24);
1144}
1145
1146static void
1140}
1141
1142static void
1147promise_timing(struct ata_softc *scp, int devno, int mode)
1143promise_timing(struct ata_channel *ch, int devno, int mode)
1148{
1149 u_int32_t timing = 0;
1150 struct promise_timing {
1151 u_int8_t pa:4;
1152 u_int8_t prefetch:1;
1153 u_int8_t iordy:1;
1154 u_int8_t errdy:1;
1155 u_int8_t syncin:1;

--- 7 unchanged lines hidden (view full) ---

1163 u_int8_t reserved:8;
1164 } *t = (struct promise_timing*)&timing;
1165
1166 t->iordy = 1; t->iordyp = 1;
1167 if (mode >= ATA_DMA) {
1168 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1169 }
1170
1144{
1145 u_int32_t timing = 0;
1146 struct promise_timing {
1147 u_int8_t pa:4;
1148 u_int8_t prefetch:1;
1149 u_int8_t iordy:1;
1150 u_int8_t errdy:1;
1151 u_int8_t syncin:1;

--- 7 unchanged lines hidden (view full) ---

1159 u_int8_t reserved:8;
1160 } *t = (struct promise_timing*)&timing;
1161
1162 t->iordy = 1; t->iordyp = 1;
1163 if (mode >= ATA_DMA) {
1164 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1165 }
1166
1171 switch (scp->chiptype) {
1167 switch (ch->chiptype) {
1172 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1173 switch (mode) {
1174 default:
1168 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1169 switch (mode) {
1170 default:
1175 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1176 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1177 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1178 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1179 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1180 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1181 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1171 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1172 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1173 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1174 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1175 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1176 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1177 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1182 }
1183 break;
1184
1185 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1186 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1187 case 0x0d30105a: /* Promise OEM ATA 100 */
1188 switch (mode) {
1189 default:
1178 }
1179 break;
1180
1181 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1182 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1183 case 0x0d30105a: /* Promise OEM ATA 100 */
1184 switch (mode) {
1185 default:
1190 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1191 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1192 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1193 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1194 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1195 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1196 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1197 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1198 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1186 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1187 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1188 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1189 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1190 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1191 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1192 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1193 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1194 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1199 }
1200 break;
1201 }
1195 }
1196 break;
1197 }
1202 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
1198 pci_write_config(device_get_parent(ch->dev), 0x60 + (devno<<2), timing, 4);
1203}
1204
1205static void
1199}
1200
1201static void
1206hpt_timing(struct ata_softc *scp, int devno, int mode)
1202hpt_timing(struct ata_channel *ch, int devno, int mode)
1207{
1203{
1208 device_t parent = device_get_parent(scp->dev);
1204 device_t parent = device_get_parent(ch->dev);
1209 u_int32_t timing;
1210 if (pci_get_revid(parent) >= 0x05) { /* HPT372 */
1211 switch (mode) {
1205 u_int32_t timing;
1206 if (pci_get_revid(parent) >= 0x05) { /* HPT372 */
1207 switch (mode) {
1212 case ATA_PIO0: timing = 0x0d029d5e; break;
1213 case ATA_PIO1: timing = 0x0d029d26; break;
1214 case ATA_PIO2: timing = 0x0c829ca6; break;
1215 case ATA_PIO3: timing = 0x0c829c84; break;
1216 case ATA_PIO4: timing = 0x0c829c62; break;
1208 case ATA_PIO0: timing = 0x0d029d5e; break;
1209 case ATA_PIO1: timing = 0x0d029d26; break;
1210 case ATA_PIO2: timing = 0x0c829ca6; break;
1211 case ATA_PIO3: timing = 0x0c829c84; break;
1212 case ATA_PIO4: timing = 0x0c829c62; break;
1217 case ATA_WDMA2: timing = 0x2c829262; break;
1213 case ATA_WDMA2: timing = 0x2c829262; break;
1218 case ATA_UDMA2: timing = 0x1c91dc62; break;
1219 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1220 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1221 case ATA_UDMA6: timing = 0x1c81dc62; break;
1214 case ATA_UDMA2: timing = 0x1c91dc62; break;
1215 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1216 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1217 case ATA_UDMA6: timing = 0x1c81dc62; break;
1222 default: timing = 0x0d029d5e;
1223 }
1224 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1225 pci_write_config(parent, 0x5b, 0x20, 1);
1226 }
1227 else if (pci_get_revid(parent) >= 0x03) { /* HPT370 */
1228 switch (mode) {
1229 case ATA_PIO0: timing = 0x06914e57; break;
1230 case ATA_PIO1: timing = 0x06914e43; break;
1231 case ATA_PIO2: timing = 0x06514e33; break;
1232 case ATA_PIO3: timing = 0x06514e22; break;
1233 case ATA_PIO4: timing = 0x06514e21; break;
1218 default: timing = 0x0d029d5e;
1219 }
1220 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1221 pci_write_config(parent, 0x5b, 0x20, 1);
1222 }
1223 else if (pci_get_revid(parent) >= 0x03) { /* HPT370 */
1224 switch (mode) {
1225 case ATA_PIO0: timing = 0x06914e57; break;
1226 case ATA_PIO1: timing = 0x06914e43; break;
1227 case ATA_PIO2: timing = 0x06514e33; break;
1228 case ATA_PIO3: timing = 0x06514e22; break;
1229 case ATA_PIO4: timing = 0x06514e21; break;
1234 case ATA_WDMA2: timing = 0x26514e21; break;
1235 case ATA_UDMA2: timing = 0x16494e31; break;
1236 case ATA_UDMA4: timing = 0x16454e31; break;
1237 case ATA_UDMA5: timing = 0x16454e31; break;
1230 case ATA_WDMA2: timing = 0x26514e21; break;
1231 case ATA_UDMA2: timing = 0x16494e31; break;
1232 case ATA_UDMA4: timing = 0x16454e31; break;
1233 case ATA_UDMA5: timing = 0x16454e31; break;
1238 default: timing = 0x06514e57;
1239 }
1240 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1241 pci_write_config(parent, 0x5b, 0x22, 1);
1242 }
1243 else { /* HPT36[68] */
1244 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1245 case 0x85: /* 25Mhz */

--- 42 unchanged lines hidden --- 		1234 default: timing = 0x06514e57;
1235 }
1236 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1237 pci_write_config(parent, 0x5b, 0x22, 1);
1238 }
1239 else { /* HPT36[68] */
1240 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1241 case 0x85: /* 25Mhz */

--- 42 unchanged lines hidden ---