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if_ale.c (217542) if_ale.c (219902)
1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 14 unchanged lines hidden (view full) ---

23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
29
30#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 14 unchanged lines hidden (view full) ---

23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/ale/if_ale.c 217542 2011-01-18 16:27:40Z jhb $");
31__FBSDID("$FreeBSD: head/sys/dev/ale/if_ale.c 219902 2011-03-23 13:10:15Z jhb $");
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/endian.h>
37#include <sys/kernel.h>
38#include <sys/malloc.h>
39#include <sys/mbuf.h>

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325 int i, vpdc;
326
327 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
328 if ((reg & SPI_VPD_ENB) != 0) {
329 reg &= ~SPI_VPD_ENB;
330 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
331 }
332
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/endian.h>
37#include <sys/kernel.h>
38#include <sys/malloc.h>
39#include <sys/mbuf.h>

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325 int i, vpdc;
326
327 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
328 if ((reg & SPI_VPD_ENB) != 0) {
329 reg &= ~SPI_VPD_ENB;
330 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
331 }
332
333 if (pci_find_extcap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
333 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
334 /*
335 * PCI VPD capability found, let TWSI reload EEPROM.
336 * This will set ethernet address of controller.
337 */
338 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
339 TWSI_CTRL_SW_LD_START);
340 for (i = 100; i > 0; i--) {
341 DELAY(1000);

--- 197 unchanged lines hidden (view full) ---

539
540 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq);
541 if (error != 0) {
542 device_printf(dev, "cannot allocate IRQ resources.\n");
543 goto fail;
544 }
545
546 /* Get DMA parameters from PCIe device control register. */
334 /*
335 * PCI VPD capability found, let TWSI reload EEPROM.
336 * This will set ethernet address of controller.
337 */
338 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
339 TWSI_CTRL_SW_LD_START);
340 for (i = 100; i > 0; i--) {
341 DELAY(1000);

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539
540 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq);
541 if (error != 0) {
542 device_printf(dev, "cannot allocate IRQ resources.\n");
543 goto fail;
544 }
545
546 /* Get DMA parameters from PCIe device control register. */
547 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
547 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
548 sc->ale_flags |= ALE_FLAG_PCIE;
549 burst = pci_read_config(dev, i + 0x08, 2);
550 /* Max read request size. */
551 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) <<
552 DMA_CFG_RD_BURST_SHIFT;
553 /* Max payload size. */
554 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) <<
555 DMA_CFG_WR_BURST_SHIFT;

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586 ifp->if_ioctl = ale_ioctl;
587 ifp->if_start = ale_start;
588 ifp->if_init = ale_init;
589 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1;
590 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
591 IFQ_SET_READY(&ifp->if_snd);
592 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4;
593 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO;
548 sc->ale_flags |= ALE_FLAG_PCIE;
549 burst = pci_read_config(dev, i + 0x08, 2);
550 /* Max read request size. */
551 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) <<
552 DMA_CFG_RD_BURST_SHIFT;
553 /* Max payload size. */
554 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) <<
555 DMA_CFG_WR_BURST_SHIFT;

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586 ifp->if_ioctl = ale_ioctl;
587 ifp->if_start = ale_start;
588 ifp->if_init = ale_init;
589 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1;
590 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
591 IFQ_SET_READY(&ifp->if_snd);
592 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4;
593 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO;
594 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
594 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
595 sc->ale_flags |= ALE_FLAG_PMCAP;
596 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
597 }
598 ifp->if_capenable = ifp->if_capabilities;
599
600 /* Set up MII bus. */
601 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange,
602 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY,

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1464{
1465 struct ifnet *ifp;
1466 uint32_t reg, pmcs;
1467 uint16_t pmstat;
1468 int pmc;
1469
1470 ALE_LOCK_ASSERT(sc);
1471
595 sc->ale_flags |= ALE_FLAG_PMCAP;
596 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
597 }
598 ifp->if_capenable = ifp->if_capabilities;
599
600 /* Set up MII bus. */
601 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange,
602 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY,

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1464{
1465 struct ifnet *ifp;
1466 uint32_t reg, pmcs;
1467 uint16_t pmstat;
1468 int pmc;
1469
1470 ALE_LOCK_ASSERT(sc);
1471
1472 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1472 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1473 /* Disable WOL. */
1474 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1475 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1476 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1477 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1478 /* Force PHY power down. */
1479 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1480 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |

--- 62 unchanged lines hidden (view full) ---

1543 struct ale_softc *sc;
1544 struct ifnet *ifp;
1545 int pmc;
1546 uint16_t pmstat;
1547
1548 sc = device_get_softc(dev);
1549
1550 ALE_LOCK(sc);
1473 /* Disable WOL. */
1474 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1475 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1476 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1477 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1478 /* Force PHY power down. */
1479 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1480 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |

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1543 struct ale_softc *sc;
1544 struct ifnet *ifp;
1545 int pmc;
1546 uint16_t pmstat;
1547
1548 sc = device_get_softc(dev);
1549
1550 ALE_LOCK(sc);
1551 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1551 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1552 /* Disable PME and clear PME status. */
1553 pmstat = pci_read_config(sc->ale_dev,
1554 pmc + PCIR_POWER_STATUS, 2);
1555 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1556 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1557 pci_write_config(sc->ale_dev,
1558 pmc + PCIR_POWER_STATUS, pmstat, 2);
1559 }

--- 1555 unchanged lines hidden --- 		1552 /* Disable PME and clear PME status. */
1553 pmstat = pci_read_config(sc->ale_dev,
1554 pmc + PCIR_POWER_STATUS, 2);
1555 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1556 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1557 pci_write_config(sc->ale_dev,
1558 pmc + PCIR_POWER_STATUS, pmstat, 2);
1559 }

--- 1555 unchanged lines hidden ---